The Design Process

The design process is composed of six discrete steps (see Table 3-1), including:

1. System Level Architecture – To start off the design process, a system architect develops an idea of what chip their team is trying to design. This process frequently starts with input from the business and marketing team indicating a market or customer need. The system architect needs to decide specifically what the chip will do, what technologies, materials, and components will be used to build the chip, and how the team will evaluate whether a chip is a success. This is like what a real estate developer and an architect would do in the construction industry. At the beginning of a project, they would start by deciding what to build (A movie theater? A gym? A house?). Once this decision has been made, they’ll need to answer questions like how many rooms should this building have? How big should each room be? How many floors? What materials will be used? Ultimately, the developer and architect need to ensure that what they are building will accomplish the task it was built for and fall within budgetary constraints. Like an architect in the construction industry, a system architect doesn’t just make a list of what they want, send their requirements to other teams, and call it a day; they will continue to monitor the progress throughout the design process and guide their team as they move through each step of the way. The system architect isn’t simply working with the engineering teams, they also have to interface with the business and marketing teams to be sure their product meets the demands of the market and falls within budget.

2. Front End Design – After hammering out higher level details and before construction can begin, engineers will need to create detailed models of the system. This starts with a high-level model of overall behavior and graduates to more specific models and detailed schematics. Where will the plumbing go? How will the electrical wiring connect to the grid? What materials will be used for the ceiling and the floors? In silicon engineering, this is the stage where logic design engineers buckle down and fill in the details. For digital systems or components, you may hear this called logic design or RTL Design (register transfer level). In the early days of the semiconductor industry, designers would manually position individual transistors to create individual Boolean logic gates.

Today, design engineers use Hardware Description Languages (HDL) like VHDL or Verilog/SystemVerilog RTL to describe what they want the circuit to do (RTL Register Transfer Level, 2021). HDL’s are specialized computer “programming” languages used to describe the physical structure of ICs and electronic systems (Tucker, 1994). Physical design tools translate these languages into the individual gates and transistors for a given function. At the conclusion of this stage, designers should have completed a virtual version of a chip that should, in theory, serve its purpose flawlessly in the real world.

3. Design Verification – As with construction, silicon design is a capital-intensive industry. You would not want to have an architect hammer out some schematics on the back of a napkin and just start building, especially if you were building multiple units. To ensure a successful project, you would want to verify that, if built, these schematics will translate into a fully functional structure(s). In semiconductors, a single chip design may be used for thousands or millions of units that must be manufactured, shipped, assembled, and integrated into a larger system. It is at this stage that engineers verify what the design team has built.

Verifying a complex design is a difficult task, so difficult, in fact, that it takes up over half of the total design time for an average SoC – 56% of labor time by some 2020 estimates (Foster, 2021). Verification is critical because chip manufacturing is so expensive - design teams have to know they got it right. SoCs (system on chip) are a type of IC that includes an entire system on a single substrate. Instead of building a main processor and peripheral chips like memory ICs and GPUs separately before connecting them to one another, SoCs contain all of the necessary circuitry on the same chip – we’ll cover them in greater detail later on.

Because there are so many potential test cases, or ways the device might be used, it is nearly impossible to verify a design for every possible scenario. There are numerous techniques, however, that are effective in different cases.

By and large, the most common verification methodology is functional verification, which simulates a design using SystemVerilog HDL code (Wile, Goss, & Roesner, 2005). The same HDL language that physical design tools can translate into physical gates and wires can be used by front-end verification tools to simulate the exact behavior of the circuit.

Functional verification is, quite simply, verifying the design does what it is supposed to do in any possible condition. For a simple AND gate, this is almost trivial. But for a billion-gate processor chip, it's not so simple. How can you possibly test every condition? To help manage this complexity, verification engineers created a new way to do verification, called UVM (Universal Verification Methodology). In this methodology, verification engineers build a model of each part of the system. Outputs of the design are then compared against this model to determine if the circuit is behaving as expected. UVM even has the capability to collect statistics on which portions of the design have been verified, and which have not.

Any flaws in the design should result in an incorrect output from a given testbench input, which can then be identified and corrected through debugging (Wile, Goss, & Roesner, 2005). As you can imagine, this is a very time- and resource-intensive process. In one sense, you have to build your chip twice – once to create the “golden model” you're comparing against, and again for the actual implementation that you’ll manufacture.

An alternative, or supplemental, verification methodology, emulation uses FPGAs (more on this in later chapters) to program a design and observe a circuit in the real world (Chang et al., 2009). This can be especially useful for applications that are dealing with real physical signals. For example, if you're designing an audio processor, functional verification tools can tell you that you should expect a 24-bit number as the correct output for a given set of inputs. This is great if your end customer is a Mathematics Professor at MIT, but what you really want to know is "How does it sound?" To do this, an FPGA emulator can be “programmed” with the newly designed audio processor so you can listen directly through your headphones or speaker.

FPGA stands for Field Programmable Gate Array – the key word here being “programmable.” Because an emulator has a bunch of non-essential circuitry your end chip won’t need, it will almost certainly be slower and consume more power than the final product. The point is not to build something ready for market, but rather a testable prototype as close to the real deal as possible. The emulation process is clunky and expensive, but the results are more tangible.

Another verification method, formal verification, uses mathematical reasoning and proofs in lieu of a simulation to verify that an RTL design will perform its desired function without directly testing any input-output scenarios. While simulation-based verification techniques apply a trial-and-error approach, guessing and testing as many scenarios as possible, formal verification tries to test a design using algorithms that theoretically cover all possible input-output combinations (Sanghavi, 2010). In formal verification, you establish the rules that govern proper behavior of the design (i.e., signal A is always the inverse of signal B, or clock X is always twice the frequency of clock Y), and the tool checks that the design abides by all these rules. With greater design complexity, however, this type of verification becomes prohibitively difficult, limiting its usage at higher ends of the market (Sanghavi, 2010).

Part of the design process includes choosing the right verification strategy for different parts of the chip. Some simple input/output relationships may be effectively verified with formal verification, while a real-time video engine may require a complex emulation platform.

4. Physical Design – This is the stage at which the chip is physically built. You have constructed a high-level model, written your RTL code and verified that it operates as expected. Chips are ultimately made of millions of transistors and other electrical components. How exactly does that RTL code turn into wires and transistors?

Advanced EDA (electronic design automation) tools bring what your front-end design team has built into the real world. This is an incredibly complex process, and can sometimes take as long as the front-end design phase. We can break physical design into five constituent steps:

• High Level Synthesis (HLS) – This is the stage that marks the end of front-end design and the beginning of back-end design. At this stage, the chip has been described in an RTL language (like VHDL or Verilog), and you've simulated that it should work as intended. physical design engineers are now ready to convert that RTL code into transistors and wires using Synthesis. For a billion-gate design, synthesis is an incredibly complex process. It can take many hours or even days to complete the process. Take Synopsys (SNPS), a leading developer of synthesis tools - with a $50 billion market cap as of January 2021, you know this is a difficult and costly problem to solve. By converting from one language to another, physical, or “back-end,” design engineers can manipulate the front-end design team’s work and complete the next stage of the design process.

• Design Netlist – The product of high-level synthesis is a netlist, a list of the electronic components in a circuit and all the nodes to which they are connected. Keeping our list of semiconductor vernacular up-to-date, circuit nodes are any individual element that an electrical signal can be sent to, whether they be interconnects, transistors, or other components that make up the circuit. These are not to be confused with technology nodes, which describe successive generations of manufacturing technology required to manufacture smaller ICs and transistors. If a chip exists as a two-dimensional network of electronic components strategically placed in an IC or on a circuit board, the netlist is a written description of which components are connected to which, like a list of driving directions without “left” or “right.” Unlike a design schematic that would show the relative position of each component relative to one another, a netlist’s main purpose is to describe information about connectivity (Holt, n.d.).

• Floorplanning – At this stage of the physical design process, Physical Design Engineers decide where everything should be located. A given design may include blocks of memory and large logic blocks that need to read and write data to those memories. Floorplanning ensures that those blocks are placed near each other. The physical design engineer must figure out which components should be clustered or placed apart and which combinations will result in the least area and the most speed (remember PPAC!). If the netlist is a list of all the things we need inside a building, floorplanning is where we decide where to put the furniture, the TV, the desk, etc. to maximize the efficient use of our limited space.

• Place-and-Route – First, during placement, engineers decide exactly where to put all the electronic components and circuitry. Once they’ve decided that a large logic block needs to reside in a particular area of the chip, a placement tool is used to allocate specific locations for each and every logic gate. If you could break up your furniture into smaller constituent parts, this is the step where you would decide where each of these subcomponents would go. Placement is followed by routing, where CAD tools integrate all the wiring required to connect the placed components. Some critical wiring like power supplies or high precision signals may actually be routed by hand. Recall that the netlist specifies every gate in the design and how it is connected, so routing merely implements all of those connections with physical wires.

• So now we’re done, right? Everything is hooked up and matches the netlist, so what is left to do? While the functional components that make up our chip have been positioned and connected to one another, we have yet to analyze a critical aspect of our new design – its timing.

• Clock-tree Synthesis (CTS) – During Clock-Tree Synthesis, engineers make sure that the electrical signaling that delivers information around the circuit “clocks” evenly, or as intended, throughout the chip (VLSI Guide, 2018). Clock frequency, or clock rate, a common measurement of processor speed and performance, assesses how quickly a signal travels through an IC, which determines how quickly it can execute instructions (Howe, 1994). Processors are such complicated circuit designs that engineers have come up with techniques to manage that complexity. One of those techniques is called synchronous design. Synchronous design uses a common “clock” across all circuits. It is important that signals do not reach the different components of a chip at the incorrect times, or the chip may be slow or fail to perform as intended. The clock ensures that this happens and that all parts of the system receive the clock signal at the same time. If one side of a chip thinks it is computing a result for one clock cycle, but another side of the chip has already completed that same clock cycle, computation errors can result.

• You can visualize this process as a line of firefighters trying to put out a fire with pails of water, as depicted in Figure 3-3. The line works most optimally if everyone hands their pail of water at the same time. The line starts with a firefighter who scoops water out of a tank and into a pail, then passes it to the second firefighter in line. This first firefighter then grabs another pail and hands it to the second firefighter as the second firefighter hands the first pail to a third firefighter and prepares to receive the second pail. Each pail gets passed to the next firefighter in line along the “critical path,” until it gets to the last firefighter who is positioned next to the fire. That firefighter throws the water “signal” onto the fire. If one firefighter takes too long to pass a pail to the next person in line, they will not have enough time to turn around and receive the next pail. As the speed of the pail passing ramps up, the firefighters are more likely to drop water or be forced to slow down the chain. In a similar fashion, if the timing for part of the chip is “offbeat” from the clock that sets the processing cadence for the rest of the device, instructions may not complete in time for the next clock edge (also known as capture edge). Failure is not necessarily an inevitable outcome here – just because a firefighter slows down or can’t get their pacing right doesn’t mean they can’t put out the fire. Rather, the system will slow down as more quickly executed instructions are forced to wait for those that were delayed. Though failure may not result, such timing issues can have a significantly detrimental effect on system performance and are a critical consideration in chip design.

The diagram exhibits 9 firefighters, part of a critical patch, attempting to quell a fire via pails of water labeled signal from a tank labeled instructions and data. A timing issue among the fourth to sixth persons leads them to drop a pail of water.

A common simulation method to compute and verify the expected timing of digital circuits is called static timing analysis (STA). STA ensures that all logic paths are properly timed relative to each other so there is never a chance of a timing error.

We will discuss signals and clock frequency in greater detail in the upcoming chapters Analog, Memory, and Common Chip Architectures.

5. Validation (also called Physical Verification or Back-End Verification) – Once a circuit is ready for manufacture, as a GDS Design file is generated that includes all the necessary information required by the fab, including transistor configuration, interconnect network, and other functional components that will be etched onto the silicon substrate. Before generating a GDS file to send to a semiconductor factory, or fab, validation engineers need to double check that a chip is manufacturable. They do this using EDA (Electronic Design Automation) software tools like Design Rule Checkers (DRC) to verify that the chip complies with all the rules of the chosen foundry. Constraints can vary from chip size to how closely wires and transistors can be placed to each other. You can think of these validation engineers like an Inspector checking your “prototype” housing unit before building the rest of the housing community.

6. GDS ll Generation – GDS ll is a standardized format that is used to send a finished design to the fab at the end of the IC design cycle (Rubin, 1993). Think of it like a Word or Excel file you might send to your manager when you’re done with a project, except that the file includes the culmination of millions of dollars of engineering ingenuity and a final chip design ready to be manufactured. Physical design engineers working on digital projects will often use the phrase “RTL-to-GDS” to describe what they do. This is referring to the physical design process that turns front end RTL design into ready-for-manufacture GDS. In many companies, this process of creating the GDS file and sending it to the foundry is still called tapeout. This term has its origins back in the early days of the semiconductor industry, when a final GDS file was put onto a big magnetic tape and shipped to the foundry or perhaps just walked across the street in Silicon Valley from the engineering building to the fab. Thankfully, today those files are sent via FTP across the world in minutes.

Please note that in Figure 3-4 illustrating our chip design construction analogy, we’ve depicted steps 4 and 5 as fully packaged with leads for the sake of illustration. In the real world, the physical design process would result in a chip layout, not a fully completed and packaged IC.

Manufacturing – The i’s are dotted, t’s are crossed, your team sent the finished GDS ll file to the fab and it is time to build an IC. When it comes to microelectronics, this is no small task. Billions of interconnected transistors and other electrical components can fit onto a single chip, and the manufacturing process is neither simple, nor cheap. It can also take an incredibly long time. Modern processes may take over 12–16 weeks from when you send the GDS file until you have finished wafers. We will cover many of these processes and technologies in the following chapter Semiconductor Manufacturing Process.

I recognize this is a lot of information to absorb so, to review briefly, the six steps of the semiconductor design process are

1. 1.

   System level architecture.

    
2. 2.

   Front end design.

    
3. 3.

   Design verification.

    
4. 4.

   Physical design.

    
5. 5.

   Validation.

    
6. 6.

   GDS design file sent to fab for manufacturing.

    

A chart exhibits the 6 steps of each circuit creation and housing construction for comparison. System-level architecture leads to manufacturing and assembly, while building architecture leads to a housing community.

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