Manufacturing Overview

Semiconductor manufacturing is a highly complex and ultra-precise process that requires specialized chip factories called wafer fabs filled with hundreds of millions or billions of dollars of cutting-edge equipment. The product of this complex process can be a few dozen to several hundred to several thousand finished ICs per wafer, depending on the die area and batch yield.

Unique processes are used to manufacture different types of semiconductor devices. You can think of these as the “recipes” for successful manufacturing. Each recipe is made up of steps leveraging a combination of technologies to successfully take a design from GDS to reality. Within the industry, these process recipes are called technology nodes, process nodes, or just nodes. The term node refers to the minimum feature size for a given generation of process technology. Feature sizes are measured in nanometers (nm), or one billionth of a meter. To put that in perspective, a sheet of paper or a strand of human hair is about 100,000 nanometers thick (NNI, n.d.). A wafer fab running an advanced 3nm node, for example, can produce chips with many more transistors than one running a 90nm node, since each transistor is significantly smaller (PCMag, n.d.).

Each time a process technology enables a smaller transistor size, a new node is born. If you hear an engineer or a news anchor discuss Intel’s old “14nm node” vs. TSMC’s groundbreaking “5nm node,” what they are discussing is TSMC’s ability to make transistors with dimensions as small as 5nm, while Intel can only fabricate ICs with feature sizes as small as 14nm. The industry naming system for advanced technology based on gate lengths is deceiving and does not reflect true feature dimensions, which are many nm behind. For simplicity, however, and perhaps to avoid any outraged emails from the marketing departments at TSMC or GlobalFoundries, we will assume that these measurements are accurate (IRDS, 2020). The most advanced technology node in development is the 2nm process node, which Samsung plans to put into production in 2025 (Shilov, 2021).

Figure 4-1 breaks down 2019 SIA and BCG data describing which generations of manufacturing technologies (nodes) are being used to create which types of semiconductor devices. Memory chips with smaller feature sizes, repetitive feature sets, and simpler architectures are manufactured using the most advanced nodes, while discrete, analog, optoelectronics, and sensors (DAO) devices are made using older, less advanced technologies (Varas et al., 2021). Listed next to each process node along the x-axis is the percentage of wafer runs currently running at that node. Less than 2% of all wafer runs in 2019 were running on 10nm equipment and process technology, 37% of all nodes were running 10–22nm manufacturing technology, and so on and so forth. Notice that while the most advanced nodes get all the notoriety, lots of chips are manufactured in decades-old nodes larger than 90nm. A wafer run is a single run-through of the semiconductor manufacturing process, from initial wafer fabrication to when the individual die are cut apart from each other during wafer dicing, we’ll discuss these processes in detail in the coming sections.

A stacked vertical column chart represents global manufacturing capacity versus manufacturing process node. The highest percentages of 100, 79, and 76 are in logic in fewer than 10 nanometers, memory in 10 to 22, and analog + O S D in more than 180.

The manufacturing process is divided into two subsections – front-end manufacturing and back-end manufacturing. Taken very simplistically, front-end manufacturing puts your desired circuit onto a silicon wafer, and back-end manufacturing gets the individual chips on that wafer ready for a customer's system. We'll explore each in detail in the coming sections.

Front-End Manufacturing

The first step in front-end manufacturing is called wafer fabrication. A wafer is a thin slice of semiconductor or substrate on which any number of chips are built. Silicon wafers are created by first melting a combination of silica and carbon down and shaping them into cylindrical objects called ingots (Stahlkocher, 2004). Ingots are then sliced into thin, unfinished wafers, ready to be used for manufacturing. Wafers used in manufacturing are typically round with a flat edge, allowing engineers and equipment to handle the wafer more easily. We can see ingots (left) and wafers (right) on display in Figure 4-2.

Wafers have doubled in diameter over the last several decades, from 150mm in the 1980s to 300mm in use today, though there is a concerted push to adopt 450mm wafers as a way to increase efficiency and boost production (more die per wafer) (AnySilicon, 2021). Like stamps on a postage sheet, a single wafer can contain hundreds or even thousands of chips by the end of the manufacturing process, which are later cut apart into individual die in a process called wafer dicing. We can see a processed wafer and its constituent die pictured in Figure 4-3.

A photograph of an upright ingot and a photograph of the components of a silicon wafer in a glass encasing.

A photograph of the die of a processed wafer. On the right is a photograph of a postage stamp with images of a right-facing horse in a barren land in a 5 by 5 formation.

In general terms, the wafer fabrication process can be thought of as like building a layer cake one layer at a time. This is oversimplifying things, but in essence, the different steps of the front-end manufacturing process are meant to build intricate combinations of substrates, circuitry, and other materials one on top of the other with the precision and accuracy needed to make a fully functioning chip.

We could spend volumes breaking down the steps of front-end wafer fabrication into countless processes, subprocesses, and technologies (don’t worry, that wasn’t a threat), but for our purposes, we can group most major front-end wafer fabrication processes into four major categories:

1. Deposition: This category encompasses a set of processes that adds materials called thin films onto a wafer’s surface (STMicroelectronics, 2000). This is accomplished by employing a multitude of technologies such as atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), and electrochemical deposition (ECD), to name a few. You don’t need to know each of these processes, just understand that there are a lot of them. To properly deposit material layers onto the wafer’s surface, the wafer is heated in a furnace filled with oxide gas through a process called oxidation. In our cake analogy, deposition is where we add successive layers of pastry or frosting.

We can see ALD, MBE, and ECD machines pictured left to right in Figure 4-4. It doesn’t take a PhD in Engineering to tell that such equipment is intricate and expensive. Filled with hundreds of these machines, you can also start to see how a modern manufacturing facility can cost billions of dollars.

Three photographs of atomic layer deposition, molecular beam epitaxy, and electro-chemical deposition machines in well-lit indoor environments. A coat-wearing professional operates the third machine.

To better illustrate what is going on in deposition, we can zoom and analyze what is happening in a common process called Physical Vapor Deposition (PVD), which is pictured in Figure 4-5. In this process, the wafer substrate is placed in a vacuum chamber across from a piece of material called a sputtering target. Sputtering gas is pushed into the chamber and aimed at the sputtering target. Atoms from the sputter target are subsequently knocked off the sputtering target and are directed at the surface of the wafer substrate, where a coat of materials called thin films are formed. Other deposition processes may use liquids or other materials for “layer-building”, but this is a great example of the mechanisms by which deposition processes work in general.

A schematic diagram exhibits the sputtering target at the top of a vacuum chamber, the rise and fall of A r + and sputtered target atoms in the center as sputtering gas moves rightward, and a thin film on a substrate at the bottom.

2. Patterning/Lithography: This step encompasses any process that shapes or alters the material on the wafer. During the photolithography process, illustrated in Figures 4-6 and 4-7, the wafer and its constituent materials first are coated with a chemical called photoresist, which breaks down in reaction to light (Valentine, 2019). From there, a giant machine called a stepper aligns a photomask over the wafer. This photomask is specific to a single layer of the process for a given chip design. The stepper then passes light at a unique wavelength (commonly deep Ultraviolet) through the photomask and onto the wafer. The presence of the photomask creates a desired pattern on the wafer which softens the photoresist in regions exposed to this light. Similarly, during electron beam (e-beam) lithography, a beam of electrons – instead of light – is shined through a mask and leaves an imprint on the wafer (Rai-Choudhury, 1997). We can see pictures of both a stepper and a photomask in Figure 4-8.

This pattern-etching process can happen dozens of times, with some advanced runs requiring over 75 different masks to produce a single design. Once the photoresist has been removed, metal or other materials can be deposited into the remaining areas to form wires connecting individual transistors and functional features to one another. You can think of patterning or lithographic processes like drawing a picture using a stencil, except here the stencil is the mask and the pen is a beam of light or electrons.

This may sound like boring manufacturing details, but lithography is a critical bottleneck technology that’s enabled geometric scaling to keep pace with Moore’s prediction over the last several decades. Each generation of lithographic equipment enables fabs to etch smaller substrate features and pack more transistors on each chip, which improves speed, lowers costs, and boosts power efficiency across the board. In order to successfully implement the most advanced process nodes, lithographic equipment suppliers have had to continually find new and creative ways to make ever smaller patterns and transistors. One of the ways has been to use shorter light wavelengths as with EUV lithography, which has been in development since the 1980s and has only recently gone into production for high volume manufacturing (Samsung, 2020).

To grasp why lithography is so critical, it's important to understand the wavelength of the light that is typically used. For many years, the main light source for lithography had a wavelength of 193 nanometers. Light can only directly etch features as large as its own wavelength, which became a serious issue as foundries moved below the 250nm node (Samuel, 2018). Optical workarounds and the use of multiples of photomasks have allowed fabs to etch smaller patterns than the 193nm light wavelength would directly allow, but as semiconductor feature sizes dropped lower and lower, performing lithography with light at a wavelength of 193 nm became increasingly difficult (Samuel, 2018). This necessitated the need for EUV, which operates at a much smaller wavelength of 13.5nm (ASML, 2022).

As this technology has advanced, lithography equipment has become incredibly expensive, with individual EUV systems integrating components from a global network of more than 5,000 specialized suppliers and costing as much as $150 million apiece (Varas et al., 2021)!

As manufacturers pursue smaller and smaller nodes, you can expect continued innovation in lithographic technology. I’m sure SEUV (Super Extreme Ultraviolet Lithography) is just around the corner.

A flow diagram exhibits the photoresist application on a substrate, light exposure with masks, and developer application. The output leads to the creation of negative photoresist from exposed photoresist.

An exploded-view drawing of a photolithography machine. The labeled parts are the light source, illumination lens, photomask, projection lens, and wafer alignment sheet.

A photograph of a stepper called AutoStep 200 in a warm-colored room. On the right is a photograph of a rectangular photomask on a glass stand.

3. Removal: While deposition adds thin film materials to the wafer, removal, you guessed it, removes them. Once a “picture” of the circuitry is imprinted onto the deposited and patterned photoresist and underlying thin film layer, a removal process like wet etching or dry etching and chemical-mechanical planarization (CMP) are used to wash away the photoresist material that is no longer needed, leaving an area that can be later filled with the desired metals, oxides, transistors, or passive components on the underlying wafer material. Wet etching uses liquid compounds, while dry etching uses gaseous compounds to dissolve unprotected thin film materials and “etch” a pattern of the underlying circuitry (STMicroelectronics, 2000).

4. Physical Property Alteration: This encompasses processes that modify the electrical or physical properties of the wafer responsible for the behavior and performance of transistors and other functional components. Processes like this include doping, rapid thermal annealing, ultraviolet light processing (UVP), and others. During doping, materials creatively named dopants are shot under the surface of the wafer in a process called ion implantation or ion introduction. These materials create positive and negative charges that are used to facilitate control and conductivity of the overlaying transistors and other circuitry (STMicroelectronics, 2000). As we discussed in Chapter 2, dopants are vital to the healthy functioning of transistors, which require a charge differential to operate their gate and control their channel.

Cycling – Pre- and Post-Metal

This cycle then repeats as many times as required, with some high-end chips requiring hundreds of steps for a single production run. Figure 4-9 summarizes the front-end manufacturing process in six major steps, which can be used across both FEOL pre-metal and BEOL post-metal processes.

A diagram exhibits the front-end manufacturing steps, namely, water surface, deposition, patterning, lithography, removal slash etching, and doping. The process is repeated until the wafer is ready.

In the early stages of front-end manufacturing, transistors are directly etched into the wafer in the “pre-metal” Front-end of the Line (FEOL) portions of the wafer fabrication process.

After the transistor array is formed, the wafer undergoes Back-end of the Line (BEOL) processing, where metallic interconnect materials, usually made from aluminum or copper, are deposited in layers separated by dielectric materials using the same four processes used for FEOL manufacturing (Singer, 2020). The dielectric materials insulate the metal interconnects from one another and provide structural support (Singer, 2020). These interconnects connect individual components to one another to form logic gates and other circuitry that ties the system together (Singer, 2020). Modern devices can have as many as 15 layers, with upper layers connected using vertical via structures to connect them to underlying components. Lower-level local and upper-level global interconnects are pictured in Figures 4-10 and 4-11, while the BEOL post-metal process is illustrated in Figure 4-12.

A close-up photograph with an applied vignette of the connected components on a wafer.

An illustration of the wafer components, namely, global interconnect, contact stud, wood line, local interconnect, and diffusion.

A diagram exhibits a T-shaped level 2 with a metal line topside and a via-labeled part atop a level 1 platform on 2 out of 4 transistors. The diagram below is of a layered block labeled as dielectric materials, vias, copper lines, transistors, and silicon.

The entire front-end manufacturing process for a complex wafer can require several dozen mask layers and take weeks to finish. These challenges are reflected in the industry’s cost distribution, with front-end manufacturing machinery comprising 60% of the $62 billion in 2020 spent on semiconductor production equipment as a whole (Precedence Research, 2021). Each successive node brings an added layer of complexity which makes wafer probing, yield, and failure analysis even more crucial to meeting production goals and keeping unit costs low. We cover these in the next section.

Wafer Probing, Yield, and Failure Analysis

At the conclusion of the front-end manufacturing process and before the back-end manufacturing process can begin, a process called wafer probing may be implemented. In simple terms, you have this wafer, packed with hundreds or thousands of die of your latest design. But does it actually work?

Wafer probing uses a device called a wafer prober to electrically test wafer die before final packaging, assembly, and testing is done. In some cases, the back-end process is so lengthy and expensive, manufacturers want to test the wafer beforehand, so they only send tested and functional die through the back-end process. In other types of wafer processing such as Chip-Scale Packaging, the entire wafer is packaged, and testing is done afterwards.

When initial probing is done, two types of tests are performed – parametric testing of the fabrication processes and wafer testing to ensure each individual die is defect-free and fully functional (STMicroelectronics, 2000). At such a small scale, a single particle landing on the surface of an unprotected die, a tiny vibration near fab machinery that misaligns a wafer, flaws in a chip design, or any number of issues can ruin the functionality of a die or even an entire wafer.

Parametric testing measures several key circuit parameters on a test circuit structure to ensure the process is performing as expected. The manufacturer needs to ensure that all the basic parameters like resistances and device thresholds are within their standard tolerances. Foundries typically add small circuit structures in between each die which are measured during this parametric testing phase. This in-between space is called the scribe line. When the wafer is diced into individual chips, the scribe line provides the space for sawing, and its test structures are destroyed. But the structures have served their purpose, and the customer is none the wiser.

Even if everything is done correctly, at least some of the die on a wafer will not work. Wafer testing enables fabs to identify dysfunctional die for disposal, measure performance, and track recurring errors so that processes can be improved. As one example, it is not uncommon for failures to be clustered in either the center of a wafer, or near the edges. This can help identify issues with fab equipment which may be contributing to these failures.

Testing enables failure analysis engineers to derive and analyze yield, an important statistic of which there are two types – line yield and die yield. Line yield, also known as wafer yield, measures the number of wafers that successfully make it to wafer probing without being thrown out. If there’s a major issue in the line, a manufacturer may have to scrap an entire wafer. For example, during testing of the structures in the scribe line, it may be determined that a fundamental parameter is way off. Die yield measures the number of functional die divided by the total number of potential die that make it to wafer probing (Backer et al., 2018). Together, they measure end-to-end yield, which holistically accounts for the efficacy of the entire front-end manufacturing process (Backer et al., 2018). For a new manufacturing line of chips, yield will generally start lower and gradually increase as the equipment is properly calibrated and manufacturing engineers have time to adjust processing steps. For the most advanced processes, initial yield may be less than 50%. Yield optimization has long been considered one of the most critical performance objectives – yield increases, even small ones, can drive down unit manufacturing costs and boost margins (Integrated Circuit Engineering Corporation, n.d.). End-to-end yield optimization across both line yield and die yield can be a strong competitive advantage (Backer et al., 2018).

Why is yield improvement so important? Take a hypothetical case where your chip is manufactured on wafers that cost $1000 each, and you can sell each chip for $3 (sorry, this section will involve a bit of math…). Let’s assume at 100% yield, you can get 1000 functional chips out of each wafer. Then, you would collect $3000 in revenue assuming all the die could be sold. That’s $2000 in profit off your $1000 wafer cost. But at a die yield of 80%, you’re left with just 800 chips at $3 a piece, or $2400 in revenue, yielding $1400 in profit and 58% growth profit margin (after the $1000 cost of the wafers). If we can increase die yield to 95%, which is achievable for more mature processes, our revenue increases to $2850, profit is $1850, and gross margin increases to 65%. That may not seem like a lot, but gross margin is one of the critical financial metrics in the semiconductor industry, and a 7% increase in gross margin is a massive improvement that can have a big impact on a company’s profitability and stock market valuation.

In Figure 4-13, we can see wafers with progressively smaller die and their respective yields. Because tiny contaminants or slight movements can permanently ruin a given die, smaller die sizes typically result in higher yields, since failure is more likely to be contained in a smaller portion of the overall wafer area. Defective die are often marked with a black dot so they can be tossed out or sold at a discounted price if still semi-functional (this is called inking).

A diagram exhibits 3 wafers with die sizes of 40 by 40, 20 by 20, and 10 by 10 millimeters and yields of 35.7%, 75.7%, and 94.2%, respectively. The first has 10 good and 18 bad, the second has 103 good and 33 bad, and the third has 620 good and 38 bad die

With such complex manufacturing processes at nanometer scales, wafer fabrication must be ultraprecise. The process is so sensitive that almost all fab manufacturing is done in clean rooms with air filtration that shrinks the number of airborne particles to 1,000 times fewer than a sterile hospital operating room (Intel, 2018). If you ever see photos or video of semiconductor workers in the head-to-toe white “bunny suits,” that’s a clean room. Fabs are mostly housed in single-floor structures or near to the ground in order to prevent the impact of footsteps from reducing yield and output (Turley, 2002). Vibrations are such a critical issue that fab equipment is frequently mounted on springs or air suspension systems, especially in earthquake-prone areas such as California and Japan.

Specialized air purification and construction requirements add to the enormous cost of equipment and persistent re-tooling, which makes up the majority of a new fab’s price tag (McKinsey & Company, 2020). A single fab equipped to manufacture the most advanced 3nm process nodes can cost from $6–7 billion to as much as $20 billion and become obsolete within five to six years (Lewis, 2019). In 2021, Samsung was considering US locations for a $17 billion fab construction project (Patterson, 2021). To put these costs in perspective, capital expenditures for US semiconductor companies amounted to roughly 30% of sales in 2020, compared to 4% of sales for the manufacturing sector as a whole (SIA, 2021).

Older fabs can sometimes be sold “down-market” to mixed-signal or analog companies that are not at the bleeding edge of the technology curve, but these sales are frequently at pennies on the dollar (EETimes, 2003). In Figure 4-14, we can see two fabs – one at SUNY College of Nanoscale Science and Engineering (left) and another at the London Centre for Nanotechnology (right).

Two photographs of two workers who wear personal protective equipment in their respective workplaces. The photograph on the left exhibits two workers displaying a wafer.

Back-End Manufacturing

Assembly and Test

After a wafer has been tested, hardworking fab technicians are ready to enclose the die into its IC Packaging and begin back-end assembly and testing. Most assembly and test work is done by third parties called Outsourced Assembly, Test, and Packaging Suppliers (OSAT’s), which are largely based in East Asia and enjoy significant labor cost advantages (Schafer & Buchalter, 2017).

The following steps detail the assembly and test process. There are many different variations of the packaging process, so it is difficult to give a comprehensive list of steps, but this is a good summary. Note that not all steps are performed in every case.

0. Wafer Bumping: This step is not always performed, but in cases where the bare die is connected directly to other components, this initial step places small solder balls (or bumps) directly onto the wafer.

1. Wafer Dicing: The next step is die cutting, where individual die are cut from a wafer using a diamond saw and sent to a back-end facility for final packaging and assembly.

2. Die Bonding: After arriving at the assembly and test facility, the freshly cut die are attached to either a packaging substrate, directly to a PCB in a process called die attach (MRSI, n.d.), or simply packaged as bare die (flip-chip). For our purposes, we will assume the die is attached to a packaging substrate. Epoxy die attach is the most common bonding process and uses specialized resins as a connecting adhesive, kind of like a gorilla glue for semiconductors (MRSI, n.d.). Flip-chip bonding functions as a die attach method as well as a method for forming system interconnects between the die and the rest of the system (Ahmed, n.d.).

3. External Interconnect Formation – Flip Chip or Wire Bond: Next, the attached die are connected to the rest of the system through little wires from the die that lead out to the periphery of the package, forming interconnects (I/0) with the rest of the system. This process is called wire bonding and results in fewer I/O connections than more advanced Flip-Chip technology (Ammann, 2003). In Flip-Chip packaging, die are flipped over and soldered to a ball grid array or directly to the PCB, forming interconnects throughout the chip’s area and increasing the overall speed of the system (Ammann, 2003). Don’t worry if this is a little overwhelming now – we will cover IC Packaging in greater detail in the next chapter.

4. Encapsulation and Sealing: In encapsulation, Surface Mount Technology (SMT) is used to mount the die onto the IC Package enclosure (Gilleo & Pham-Van-Diep, 2004). Next a transfer molding machine heats encapsulant compounds or molded underfills before injecting them into the packaging mold, sealing in the die-package assembly (Gilleo & Pham-Van-Diep, 2004). We can see a fully “assembled” die-package assembly in figure 4-15.

A diagram exhibits the components of a die. The silicon die or integrated circuit chip is covered by a plastic, metal, or ceramic lid with a package of similar material, while copper interconnects are assembled below.

5. Final Testing: The resulting die-package devices are tested one final time before shipping to the end customer or integrated into an intermediate system or product. It should be noted that in some well-established technologies with very high yield (>90%), this Final Testing may be the only testing of the individual die. When wafer testing is too expensive, it can be more economical to package every single die and test afterward, simply discarding the die that fail at final testing.

The five steps of the back-end manufacturing process are summarized in Figure 4-16. To re-cap, individual die are cut apart from one another during wafer dicing. Each die is then soldered to either a ball grid array (BGA) or directly to a PCB. Once soldered, external interconnects are formed to bond the die to the rest of the system and ensure effective connectivity and quick data transfer. The die-package assembly is then encapsulated and sealed to protect the die from any outside damage and ensure the system’s integrity. Finally, the die-package assemblies are tested one last time before shipping to an end customer or device manufacturer for incorporation into a larger product.

A diagram exhibits the steps of the back-end manufacturing process, namely, wafer dicing, die bonding, die attach, external interconnect formation, encapsulation and sealing, and final testing.

Semiconductor Equipment

As we have seen, semiconductor production is an incredibly complex process involving dozens of different types of sophisticated equipment. These devices are as complicated as they are expensive – a single EUV machine can cost upwards of $150 million. We can see the extent of these costs by looking at a breakdown of the $64 Billion semiconductor equipment market in Figure 4-17, which depicts 2019 sales data drawn from the 2021 BCG and SIA report on strengthening the global semiconductor supply chain. Figure 4-17 parses out eleven types of semiconductor equipment, with front-end manufacturing equipment responsible for the vast majority (86%) of overall equipment sales. As chips continue to shrink, the level of difficulty in making them grows, pushing costs for such equipment higher and higher. This is particularly true for core front-end technologies responsible for delivering these increasingly smaller patterns like deposition, lithography, and removal. You may have never heard of these machines before, but you can thank them for your iPhone!

A half-pie chart exhibits 8 semiconductor equipment, such as deposition, that make up 55 billion dollars or 86% of back-end manufacturing, while testing equipment and assembly equipment make up 9 billion dollars or 14% of back-end manufacturing.

Summary

From there, we reviewed the differences between pre-metal front-end-of-the-line (FEOL) processes used to etch a transistor array onto the wafer surface and post-metal back-end-of-the-line (BEOL) processes used to build local and global interconnects that tie the system together. Once wafer fabrication is complete, finished wafers are tested and probed for defects. We next learned the importance of yield and failure analysis to process improvement and cost cutting. Finally, we broke down the back-end assembly process where OSATs place the finished die into protective IC packaging. We can see the semiconductor manufacturing flow summarized in Figure 4-18.

A flow diagram exhibits the connected steps of wafer creation, wafer processing, and wafer dicing, assembly, and testing. Each has a bulleted list of its own steps.

Building functional machines at the atomic scale, much less protecting them from the outside world, requires a plethora of increasingly expensive and ultraprecise equipment and process technology. Tying these technologies together, modern semiconductor fabs are incredible feats of human ingenuity responsible for the proliferation of computing devices across the world.