Index
A
Actuators
Air purification/construction requirements
Analog-to-digital (ADC)
SeeDigital-to-analog (DAC) technology
Application-specific integrated circuits (ASICs)
advantages
cost analysis
disadvantages
time-to-market constraints
Application-specific standard parts (ASSPs)
Application-specific standard products (ASSPs)
Arithmetic logic unit (ALU)
Atomic layer deposition (ALD)
B
Back-end manufacturing
assembly/testing
die bonding/cutting
die-package assembly
encapsulation/sealing
external interconnect formation
flip-chip bonding functions
testing
transfer molding
wafer bumping
wire bonding
Back-end-of-the line (BEOL)
Backup/auxiliary memories
Ball grade array (BGA)
Ball grid array (BGA)
Bipolar junction transistors (BJT)
Bipolar semiconductor manufacturing
BrainScaleS System
Bus interfaces
block diagram
chipset architecture
CPU/microprocessor
interface circuit design
Northbridge
parallel vs. serial interfaces
primary functions
serial interface buses
Southbridge
system bus
C
Central processing units (CPUs)
Chemical-mechanical planarization (CMP)
Chinese competition
manufacturing capacity
smartphones/infotainment systems
United States
Chip-scale packaging (CSP)
Circuits
discrete components
SeeDiscrete components
Code division multiple access (CDMA)
Complementary metal-oxide semiconductor (CMOS) technology
Complex instruction set computing (CISC)/RISC
architectures
assembly languages
clock cycle
compilers
ecosystems
hertz
MIPS/ARM Holdings
proprietary vs. licensed vs. open source
Conductivity
conductors
definitions
electrical wiring
insulators
Ohms (Ω)
COVID-19/semiconductor supply chain
advantages
economic consequences
factors
geographic clustering
geopolitical conflict
mutual interdependence
natural variability
regional stratification
total cost of ownership (TCO)
Cycling pre/post-metal process
dielectric materials
FEOL pre-metal/BEOL post-metal processes
global interconnects–intel processor
metal deposition and interconnect formation
SRAM memory chip
types
D
Deep learning
Designing costs
communication architectures
EDA tools
overview
quantum tunneling and current leakage
semiconductor IP companies
software tools
systems companies
Die stacking technologies (HBM vs. HMC)
advantage/disadvantages
2.5D and 3D packaging
memory market
through silicon via (TSV)
Digital signal processors (DSPs)
Digital-to-analog (DAC) technology
artificial intelligence/machine learning
ASICs/FPGAs
binary computer language
central processing units (CPUs)
components
control systems
digital/analog components
electromagnetic energy
emulators
frequency
frequency/amplitude
graphics processing units (GPUs)
hardware accelerators
Hertz (Hz)
logic market
matrices
memory chips
MEMS devices
microprocessor (MPU)
mixed-signal devices
mobile device sensors
multi-chip-module (MCM)
multi-core architecture
optoelectronics
parallel/serial processing
potential applications
sensors/actuators
SIA framework
special purpose logic devices
synchronous
system on chips (SoCs)
wavelength
wave signals
wireless technologies
Discrete components
building blocks
CMOS technology
components
diodes
direct current (DC)
electronic system
functional components
functional scaling
geometric scaling
integrated circuits
logic gates
MEMS
non-integrated components
resistor/capacitor/inductor
substrate
technology/process node
transistor
SeeTransistors
transistors function
Double Data Rate RAM (DDR)
Dynamic random-access memory (DRAM)
E
Electrically erasable programmable read-only memory (EEPROM)
Electricity/conductivity
amperes
batteries
battery powered light bulb circuit
cathode/anode
charge/current
chemical energy
circuit
conductivity
conductors
current
differences
electromotive force (EMF/E)
electron flow vs. current flow
electron movement/charges
flammable structures
Joule’s Law
kinetic energy
neutral neutrons
potential charge
protons/electrons
strong/electromagnetic forces
units of electricity
watts (W)
Electrochemical deposition (ECD)
Electromagnetic force
Electromagnetic interference (EMI)
Electromotive force (EMF/E)
Electronic design automation (EDA)
Electronic system
components
die-level integration
different levels
functional components
integrated circuit
interconnects
module
PCB components
system architect
Erasable programmable read-only memory (EPROM)
F
Fabs vs. fabless design
Failure analysis engineers
Federal Communications Commission (FCC)
Field effect transistors (FET)
Field programmable gate array (FPGA)
FinFET vs. MOSFET transistors
Front-end manufacturing
ALD, MBE, and ECD machines
deposition
e-beam lithography
EUV systems
fabrication process
ingots/silica
ion implantation/ion introduction
oxidation
pattern-etching process
patterning and lithography
patterning and photolithography
photolithographic process
photolithography process
photoresist
physical property alteration
processed wafer vs. stamp sheet
PVD process
sputtering gas
stepper and photomask
substrate
thin films
wafer dicing
wafer fabrication
wet etching/dry etching
Front-end-of-the-line (FEOL)
Front-side bus (FSB)
Functional scaling
G
Gallium arsenide (GaAs)
Gallium nitride (GaN)
Gate-All-Around (GAA)
Geometric scaling
Geometric vs. functional scaling
Germanium/gallium arsenide (GaAs)
Global System for Mobile Communication (GSM)
Graphics processing units (GPUs)
H
Hard disk drives (HDD)
Hardware description languages (HDL)
Harvard vs. Von Neumann architecture
Heterogeneous vs. monolithic integration
device architecture and integration
functional scaling
geometric scaling
heterogeneous integration
integrated systems
monolithic/homogenous integration
power management/frequency
process nodes
High-bandwidth memory (HBM)
High performance computing (HPC)
Huang’s Law
Human Brain Project (HBP)
Hybrid Memory Cube (HMC)
I
Inking
Instruction set architectures (ISA)/microarchitecture
ARM architecture
cooking and clock cycles
instructions
pipelining
processing throughput
processor performance/instruction pipelining
synchronous task
transistors
universal architecture stack
Integrated circuits (ICs)
electronic system
packaging type
architectures
components/configurations
copper hybrid bonding
flip-chip attachment process
heterogeneous integration
MCM/SiP integrate
monolithic integration
solder balls
stacking technology
through silicon vias (TSVs)
2D/3D monolithic integration
2.5/3D packaging architectures
underfill/flip-chip bonding
wafer bumping
wafer-level packaging
wire bonded connections
Integrated device manufacturers (IDMs)
Internet protocol (IP)
Intersymbol Interference (ISI)
I/O Controller Hub (ICH)
J, K
Joule’s Law
L
Light emitting diodes (LEDs)
Lithographic equipment
Lithographic technologies (EUV)
Lithography lab
Logical link control (LLC)
Logic gates
M
M&A agreement announcements
Manufacturing costs
equipment
lithography equipment
packaging architectures/heterogeneous integration
semiconductor business models
Manufacturing process
back-end assembly/testing
consecutive cycles
cycling pre/post metal
DAO devices
die area/batch yield
end-to-end flow
front-end manufacturing
semiconductor equipment
technology/process nodes
utilization
wafer fabrication/dicing
wafer fabs
wafer probing/yield/failure analysis
Media access control (MAC)
Memory stack
booting instructions
cache
cache memories
hierarchy
memory hierarchy library analogy
microarchitectures
non-volatile ROM memories
permanent storage non-volatile
RAM/ROM memories
temporary storage volatile
Metal-oxide field effect devices (MOSFETs)
Metal oxide semiconductor field effect transistor (MOSFET)
Microarchitecture
Micro-electro-mechanical systems (MEMS)
actuators
discrete components
fabrication techniques
interface drivers/power devices
manufacturing technology
optoelectronics
power integrity issues
power management ICs (PMIC)
sensor applications
technological innovation
Microprocessor (MPU)
Micro-vs. Macro-architectural decisions
heterogeneous vs. monolithic integration
ISA/microarchitecture
RISC and CISC
system architecture/microarchitecture
Von Neumann vs. Harvard architecture
Molecular beam epitaxy (MBE)
Moore’s law
fascinating technologies
computing applications
cryogenic technology
data storage
geometric/functional scaling
neuromorphic technology
prolonging technologies
quantum computing
quantum entanglement/supremacy
scaling technologies
superposition
transistors
tunneling/entanglement
sustaining technologies
carbon nanotubes
custom silicon/specialized accelerators
data transfer rate
electron mobility
FinFETs
functional scaling
GAA transistors
Gate-All-Around (GAA)
graphene carbon nanotubes
optical chips/interconnects
optical interconnects
planar transistors
POEM project
power density
quantum tunneling
through silicon via (TSV)
transistors
tunneling interference
2.5 and 3D Die stacking
traditional silicon engineering
Multi-chip-modules (MCMs)
N
Nanosheet transistors
National Nuclear Security Administration (NNSA)
Neuromorphic computing technologies
Non-integrated discrete components
Non-volatile memories
burning process
EEPROM/EPROM
HDD vs. SSD
NAND flash memory
primary memories
secondary memories
n-type semiconductor (NMOS transistor)
O
Open systems interconnection (OSI) model
application layer
data link layer protocols
embedded software/firmware
hardware abstraction/platform layers
inter-system communication
macro-system stack
middleware layer
middleware/platform layer
network interface controller
network packets
PHY layer
presentation
reference model
session/transport
system designers
system layers
system stack
Optoelectronics
Outsourced Assembly, Test, and Packaging Suppliers (OSAT’s)
P, Q
Parametric testing
Performance, power, area, and cost (PPAC)
battery-powered laptops
clock frequency (Hz)/watts/nanometers (nm)
constraints
key design metrics
metrics
requirements/drivers
trade-offs
Peripheral component interface (PCI)
Photonically optimized embedded microprocessors (POEM)
Photonic integrated circuits (PICs)
Physical layer (PHY)
Physical vapor deposition (PVD)
Power distribution network (PDN)
Power management ICs (PMICs)
Power management units (PMUs)
Printed circuit board (PCB)
Programmable read-only memory (PROM)
Property, plant, and equipment (PPE)
p-type semiconductors (PMOS transistor)
R
Radio frequency (RF)/wireless technologies
bandwidth
base station
big picture
broadcasting/frequency regulation
conversation chunks
coverage cell
digital signal processing (DSP)
electrical energy/wave energy
electromagnetic spectrum
1G/5G(generation) technology
frequency and application
frequency bands
long-distance phone call
multiple access standard technology
OSI reference model
radiation
signals
TDMA/CDMA
transmitters/receivers
active/passive components
amplifier
antennas
block diagrams
filters
frequency/amplitude
functions
interference/noise
modulator/demodulator
power source/oscillator
signal integrity
Random-access memories (RAM)
Read-only memories (ROMs)
Reduced instruction set computing (RISC)
SeeComplex instruction set computing (CISC)/RISC
S
Scribe line
Semiconductor industry
capital expenditures
capital requirements
Chinese competition
consolidation
acquisition announcement
capital-intensive industry
companies
contextualize
cost of goods sold (COGS)
dual pressures
industry dynamics
intellectual property (IP)
M&A agreements
COVID-19
cyclical revenues/high volatility
fabless design companies
fabs vs. fabless design
front-end design
fully integrated semiconductor companies
high R&D/capital investment
historical evolution
IDMs/fabless design
Lite-Fab model
long-term profitability
manufacturing and assembly
positive productivity growth/high compensation
pros and cons
pure-play foundry
rising design/manufacturing costs
shuttle run
silicon cycles
tighter integration
United States/international market
Semiconductor Industry Association (SIA)
analog components
categories
components
distribution
end-use applications
framework
logic encompasses
memory
micro components
optoelectronics
PPAC requirements and drivers
Semiconductors
chip design
components
design/manufacturing technology
electricity/conductivity
SeeElectricity/conductivity
elements
flywire connections
integrated circuit
manufacturing
SeeManufacturing process
package-die assemblies
photolithography
PPAC constraints
SIA framework
silicon
substrate
system integration
transistors
types
value chain
Signal integrity
digital signals
noise, crosstalk, distortion, and loss
transmission lines/voltage
transmission process
Silicon
Silicon germanium (SiGe)
Solid state drives (SSD)
Spiking neural networks (SNN)
SpiNNaker (SNN) System
Standard linear integrated circuits (SLICs)
Static random-access memory (SRAM)
Strained silicon germanium (SiGe)
Strong force
Super extreme ultraviolet lithography (SEUV)
Surface mount technology (SMT)
System
bus interfaces
input/output (I/O)
interconnects
I/O interconnects
latency
packaging type
power flow
battery-powered system
power converter
power integrity
voltage regulators
voltage regulators/power converters
water utility analogy
signal integrity
subsystems/modules
System-in-packages (SiPs)
System-on-chips (SoCs)
T
Through silicon vias (TSVs)
Time-division multiple access (TDMA)
Transistors
base/emitter/collector
bipolar transistor
capacitors/resistors
channel process
components
digital electronics
dopants/impurities
doping
electronic system
ENIAC vs. ENIAC-on-a-chip
FinFET vs. MOSFET
function
metal oxide
n-type (negative) semiconductors
p-type (positive) semiconductors
signals
structure
vs. vacuum tubes
water flow analogy
working process
Transmission control protocol (TCP)
U
Ultraviolet light processing (UVP)
United States/international market
demand perspective
design companies
detailed analysis
EDA tools
memory and discrete component
OSAT
semiconductor value chain activities/consumption
silicon supply chain
smartphone
V
Volatile memories
Voltage (V)
Von Neumann vs. Harvard architecture
W, X
Wafer probing
Wireless networking systems
SeeRadio frequency (RF)/wireless technologies
Wireless technologies
analog technology
cloud computing
data centers
evolution
1G/5G(generation) technology
leveraging technologies
LTE
modulation
World Semiconductor Trade Statistics (WSTS)
Y, Z
Yield optimization
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