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Appendix I: Schematics Basics

Schematics are the primary document to design, build and troubleshoot the hardware.

Mostly, the architecture or functional blocks are split in to schematics pages and connected together. There might be separate sections for each subsystems, power delivery and Interconnects. Every electrical subsystem is covered in the schematics. The pages are sequenced in such a way the designer or the test engineers later navigate easily block by block. There are BKMs available for schematics to make it more presentable aesthetically, readable and easily understandable later during the design review and testing phase.

The components or symbols within the page or across the pages are connected through wires called nets . The point to point nets are connected with unique signal names. Signal names are based on the electrical interface type. There are global nets like power nodes, which might be connecting many devices run throughout the schematics pages.

Different components use different reference designators to identify in schematics.

Understanding how to read and follow schematics is an important skill for any electronics engineer.

Some of the standard basic schematics symbols of various components are given below

Resistor

Capacitor

Inductor

Diode

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Three Pin Header/Connector

../images/462209_1_En_BookBackmatter_Fige_HTML.gif

IC (20 Pin Buffer)

../images/462209_1_En_BookBackmatter_Figf_HTML.gif

TACT Switch with mounting holes (M1..M4)

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Power Source

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Ground

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Transistor

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Similar to these symbols, there are unique way of representing Logic Gates, Op AMPs, Oscillators and Crystals, Transformers, Fuses, Relays etc. Schematics is simple and the easy way to understand the components, connections and operation of the circuit.

Each part will be provided with unique reference designators to identify from the schematics and layout. Resistors, capacitors, inductors and other discrete are identified with values and other details. While integrated circuits are identified with part numbers along with the version numbers.

Reading Schematics

First step in reading the schematics is understanding the components. And how those components are connected each other through nets and nodes. Each net name will be provided with unique labels .

Below is the Board to Board connector with net connections provided with unique NetNames.

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Usually schematics should be split into different functional blocks and distributed through multiple pages. Most schematics drawn sequentially from the power input towards system boot flow. There is not standard practice to draw a schematics. The best practice to present is to keep the inputs at the left side and outputs at the right side of each block for easy understanding.

Layout Basics

PCB layout design has been around for decades, but its relevance not faded yet. There are lot of customization and miniaturization done over the time to get smaller PCBs for wearable devices. In the age of where everyday devices with embedded systems are becoming Internet-connected devices, PCB design is still meeting that need, while growing more advanced, and more in demand.

Despite so much advancements in the PCB technology and the design tools, the layout CAD design still same. Skilled CAD design engineers have to do manually place and route the connections in a PCB.

Its absolute necessary for an engineer working on systems designs to learn about printed circuit boards .

First step is setting up the layers as per the plan in the Layout tool. Fix the board outline along with the layer details. Import the netlist from the schematics design. All the schematics symbols shown above will be imported in the layout with equivalent layout symbols along with the reference designators and properties.

Once component are imported along with the connection details, finish the component placement as per the floor plan. Freeze the placement as per the system requirements.

Start the signal routing as per the guidelines. Do the power routing at the end.

Designers can view the board file on the Layout viewer, navigate layer by layer and make sure everything done as per electrical guidelines. Do not violate laws of physics anywhere in the design .

Electronic System Design Communication interfaces

Interfacing the electronic system allows the electronic circuit or system to communicate internally and externally. The communications interface allows the transmission of either analogue signals or digital data.

Each electronic system communicates with other systems by transmitting data via a transmitter (Tx) subsystem and receives data via a receiver (Rx) subsystem. The medium between the two systems is the communications channel. However, when analogue signals or digital data are transmitted through the communications channel, noise might be added to the signal, potentially corrupting the data. A great deal of care must be taken to ensure that the electronic systems do not use corrupted information.

Although information can be sent or received as analogue signals or digital data, digital data transmission is increasingly common and occurs as either parallel or serial data transmission:

Parallel data transmission. Multiple bits of data are transferred simultaneously, allowing high-speed data transfer.

Serial data transmission. One bit of data is transferred at a time (a serial bitstream). Serial data transmission takes longer, but when the data is transmitted on electrical wires (typically copper wires), fewer wires are required than with the parallel data transmission. Serial data transmission also lends itself to data transmission via optical fibers and wireless methods.

Many systems allow several parallel and serial communications standards.

For the synchronous data transfer, a separate clock is shown for the transmitter and receiver. In practice, there might only be one common clock for the transmitter and receiver.

During data transmission, errors can occur when noise is added to the signal and when the noise is large enough to corrupt the data being transmitted. The transmitter circuit can include the ability to add information to the data before they are transmitted, and the receiver circuit can include the ability to identify whether the data it has received appears to be OK or has been corrupted. A simple method for error checking is to use parity checking, in which a bit is added and transmitted with the data. Considering a byte of data (8 bits) as an example, parity checking is of two types:

Odd parity coding will set the parity bit to a logic 1 if the number of logic 1s in the byte is even, so that the total number of logic 1s is an odd number. If the receiver receives an odd number of logic 1s, then it will identify that the byte was transmitted correctly.

Even parity coding will set the parity bit to a logic 1 if the number of logic 1s in the byte is odd, so that the total number of logic 1s is an even number. If the receiver receives an even number of logic 1s, then it will identify that the byte was transmitted correctly.

Parity checking is a rudimentary method, and most communications systems include more sophisticated capabilities.

The characteristics of the channel must also be considered, the data may need to be modulated before transmission. Modulation takes either of two forms:

Baseband signals in digital are the 1s and 0s being generated. On a PCB and communicating between ICs on the PCB, baseband signals are used. These signals cover a frequency range from DC to an upper frequency value.

Modulated signals are baseband signals that have been modulated by a carrier signal so that the entire signal is now at some higher frequency. Modulation allows the baseband signals to be transmitted through a particular communications channel. When modulated signals are transmitted and received, the electronic system must include a modulator and a demodulator.

The transmission of the signal through the communications channel can be either one-way or two-way, so the designer must decide whether the communication is to be simplex, half-duplex, or full-duplex:

Simplex , in which data transmission is one-way on a single channel.

Half-duplex , in which data transmission is two-way on a single channel. This means that the direction of data transmission alternates, so that the system would be able to receive or transmit, but not both at the same time.

Full-duplex , in which data transmission is two-way on two channels. This means that an electronic system would be able to receive or transmit at the same time.

Finally, the signal will be transmitted through the communications channel via electrical wires, optical fibers, or using wireless methods.

Wired, in which metal wires, typically copper, are used to transmit the electrical signal.

Optical fiber, in which an electrical signal is converted to an optical (light) signal and transmitted along the optical fiber . This allows high transmission rates and low loss, so that signals can be transmitted over long distances, and a low bit error rate. The electrical signal is generated either by a light-emitting diode (LED) creating noncoherent light or by a laser creating coherent light. At the receiver end, the signal is converted back to an electrical signal using a photodiode or phototransistor.

Wireless , in which an electrical signal is modulated and applied to an antenna. The more popular modulation methods are AM (amplitude modulation), FM (frequency modulation), and PM (phase modulation). The signal is transmitted through free space, and at the receiver, another antenna picks up the transmitted signal, demodulates it, and restores it. It must then be amplified before it can be used.

High Speed Interfaces

High-speed serial interfaces are successful in chips due to demand for high bandwidth and performance of electronic devices. Various standards are developed around different high speed interfaces in a single monolithic IC. However, different standards also have different requirements and from a silicon design perspective. Creating a high speed interface cell that meets the requirements of different standards becomes a smart design proposition.

Only by understanding the differences among emerging high-speed interface standards and the tradeoffs involved in a common implementation will the system designer will better be able to choose the right device for his application.

Basically, a given high speed link can be modeled with three elements : the transmitter, a channel that propagates the signal, and a receiver:

The channel may be as simple as a pc board trace used to interconnect two chips or it may be much more complicated - for example, for a WAN backplane application the "channel" may have multiple lengths of pc board trace joined by connectors. For long-reach standards the channel may also have optics since long reach is required.

In an ideal system , the edges of a digital signal will always occur at integer multiples of the signal period. In a real system , the edges of a digital signal will occur in a distribution around the center point, which is the average period of the digital signal.

Jitter is defined as the variation in the edge placement of a digital signal. Three jitter components are usually specified: jitter generation, jitter tolerance, and jitter transfer. Jitter generation is the amount of jitter created by a device assuming the device’s reference clock to be jitter-free. Jitter tolerance is the maximum amount of jitter a device can withstand and still reliably receive data. Jitter transfer is a measure of the amount of jitter transferred from the receive side of a device to the transmit side of a device.

Jitter requirements for high-speed interface standards vary widely. Deterministic jitter is jitter generated by either insufficient channel bandwidth, leading to inter-symbol-interference, or by duty-cycle distortion, which leads to timing errors in data clocking. Random jitter is usually assumed to have a Gaussian distribution and is generated by physical noise such as thermal noise. Sinusoidal jitter is used to test the jitter tolerance of a receiver across a range of jitter frequencies and is not a jitter type that would be encountered in a deployed system.

Multiple approaches to meet the jitter requirements can be taken. Since many of these high-bandwidth interfaces use source-synchronous clocks, the jitter in the generated clock is of concern. Such systems benefit from using a high-quality crystal and PLL to generate the board clock used to clock most of the system logic, since clocks recovered from the received data usually have high jitter relative to a quality crystal oscillator.

Pre-emphasis may be applied to the output signals to ensure the received signal has a well-defined shape after the frequency-dependent deleterious effects of the channel are taken into consideration. PLLs required by the clock-and-data-recovery circuits in the receivers must be able to accurately track the input data. The receivers may also use equalization to reshape the received pulse and "open the eye" of the received signal.

Pulse-shaping

The pre-emphasis and equalization techniques described above are methods of pulse-shaping where the shape of the waveform is modified to "open-up" the eye diagram. Pre-emphasis is done by emphasizing the high frequency content of the output waveform and is done by the transmitter. Equalization is done by emphasizing the high frequency content of the input waveform and is done by the receiver. The emphasis on the high-frequency content is required since the channel frequency response is a low-pass response.

One simpler common pre-emphasis technique is to temporarily increase the rail voltage of the transmitter for 0-1 or 1-0 transitions. With this technique the rise and fall times for the circuit are accelerated, since after the transition the output is allowed to "settle" to a voltage closer to the common-mode voltage for a continuous run of common symbols. This technique has the advantage of requiring minimal circuit area to implement, since it can be done using digital logic — complex analog filters are not required.

An example differential interface architecture used by many CMOS differential circuits, The transmitter may be AC- or DC-coupled to the receiver. For DC-coupling, the transmitter output lines are directly connected to the receiver input lines - so any DC voltage on the transmitter output line is presented to the receiver input line. The common-mode voltage of a DC-coupled receiver will therefore vary as the common-mode voltage of the transmitter varies.

For an AC-coupled link, the transmitter output lines are connected to the receiver input lines through series capacitors, which serve as DC-blockers. An AC-coupled receiver can control its common-mode voltage, since the AC-coupling capacitor serves as a DC block - the transmitter cannot vary the common-mode voltage of the receiver. AC-coupling is possible because the maximum run-length (number of consecutive 1s or 0s) of the subject protocol is limited (the pattern must be DC-balanced). When the maximum run-length of a protocol is too large, AC-coupling is not possible.

The differential transmitter is paired with a differential receiver - however, while the differential transmitter architecture is relatively standardized there are many different differential receiver architectures in use. A DC-coupled example receiver architecture coupled to the differential transmitter .

One of the advantages of an AC-coupled high-speed link is the control the receiver designer has over the common-mode voltage - the designer can optimize the receive circuit for a specific common mode voltage, because the input signals will not have any DC component. As a result, the jitter requirements of a particular specification can potentially be met with more margin with an AC-coupled receiver than with a DC-coupled receiver.

The result is that the design of a DC-coupled transmitter may be easier than an AC-coupled transmitter for the same set of specifications. Also, the design of an AC-coupled receiver will be easier than the design of a DC-coupled receiver for the same set of specifications.

Reliability/durability

The primary concern for reliability is ESD protection. Since the I/Os for multi-gigabit standards are by definition high data rate, the I/O must have low capacitance. The requirement for low capacitance leads to novel ESD structures to ensure the I/Os are fully protected without introducing the deleterious effects on rise time which result from high capacitance. Such effects include a decrease in supported bandwidth and increases in jitter and power consumption .

Low Speed Communication Interfaces

The most common low speed communications interfaces are I2C, SPI and UART.

The main difference between synchronous interfaces (like the SPI or I2C) and the asynchronous ones (like the UART) is in the way the timing information is passed from transmitter to receiver. Synchronous communication peripherals need a physical line (a wire) to be dedicated to the clock signal , providing synchronization between the two devices.

Epilogue

We set out with a goal of providing good overview and introduction to electrical system design. Reader is taken through fascinating and challenging world of system design, starting from design flow till certification considerations. Drone system example is considered as it encompasses multiple aspects like industrial design, mechanical design, electrical hardware design and real time software designs. Hopefully we succeeded, to a large extent, in providing firm footing, so that reader can explore further on his own.

To develop further expertize and appreciation for the subject matter, reader is encouraged to take up study of few additional embedded system examples like set top box, WiFi routers, IoT systems for home automation, surveillance etc. Studying standard teardown reports is good way to start with. Even more effective approach would be to do a hands on high level design of a small system that addresses a specific need in the real world, however small it may be.

Index

A

Active cooling solutions

Active power management

Advanced configuration and power interface (ACPI)

Agile model

AHr (ampere hour)/WHr (watt hour)

Altitude simulation testing

Assembly process

design specifications of

inspection and functional test

manual soldering

post process

pre-gerber files

surface mount

hole connectors

inspection and quality control

inspection method

manual checks

pick and place

reflow soldering

soldering process

solder paste

wave soldering

X-ray check

B

Baseband signals

Batteries/solar/fuels

architecture

lead acid

lithium

NiCd

NiMH

power consumption

rechargeable batteries

specifications

Battery estimation

capacity

cells/voltage

cell voltage and packs

chemistry

constraints

initial and lifetime costs

watt hours and energy density

Bill of materials (BOM)

component

generation

material readiness

report-type document

symbol attributes

time-consuming process

tool-generated BOM

Black box testing

Board-level testing (BLT)

BIOS

flash programming

functionality check

OS and application installation

Board-to-board (BTB) connectors

Bringing-up system

drivers/modules

libraries/middle layer and application

loading and unloading process

OS (RTLinux)

SoC block diagram

system firmware

C

Cache memory

Cameras

categories

color sensors

crop monitoring drone

drone imaging solution

features of

hyperspectral imaging sensor

integration of

monochrome sensors

power source and host interface

spectral imaging

Clock-and-data-recovery circuits

Color sensors

Communication module

electronic system

features of

intentional and unintentional radiation

IR/RF wireless

key considerations

mobile network

module interfaces

solution

WiFi+BT

wireless protocols

CompactFlash storage

Computer-aided design (CAD) tool

Connected standby power management

Cooling technologies

Costing testing

Cathode ray oscilloscope (CRO)

Crop Squad specification

D

Data acquisition (DAQ) equipment

Design constraints

Design rules checking (DRC)

Design validation testing

electrical validation

integration testing

optional circuits

signal integrity testing

power validation

design margins

efficiency measurement

power and performance

power integrity

power supplies

system power targets

test specification

thermal device

validation processes

Drone system

accessories

assembly

factory tooling

standard/customized parts

system pilot build

system validation

classification

commercial field

ground-based controllers and accessories

hardware

industrial option

logical view

mechanical system

military applications

software

Drop, shock, and vibration testing

E

Electrical fast transient (EFT) test

Electronic system design

baseband signals

error checking

full-duplex

half-duplex

implex

modulated signals

modulation methods

optical fiber

parallel data transmission

parity checking

parity coding

serial data transmission

Tx and Rx

wireless

embedded multimedia controller (eMMC)

Electromagnetic compatibly (EMC)

End-to-end testing

Environmental testing certification

altitude testing

drop, shock, and vibration testing

humidity

product designers

reliability

temperature

Electrostatic discharge (ESD)

Ethernet

External displays

F

Fabrication process manufacturing process

Field programmable gate array (FPGA)

Flash storage device

advantages of

compactflash

Micro SD card

MMC/SD card

multimedia card

NOR vs. NAND flash

secure digital

solid state drives

USB flash drive

Flight controllers

FPC/FFC connection

Functional testing

G

Global system power states and transitions

Gray box testing

H

Hardware design

ball grid array

electrical ingredients selection

BOM and components

electrical BOM (EBOM)

feature

production status

features of

floor plan

PCBA design

dimensions

hybrid PCB

layer stack-up

parameters

types

power architecture

batteries

comparison of

complexity

cost and size

devices

efficiency

estimation

function

linear regulators

map

platform requirements

ripple and noise

sequencing data

SOC voltage and current requirements

states

switching regulators

process of

requirements

SOC

subsystems/electrical subsystems

communication devices

input

output

storage

Hardware development

High-speed serial interfaces

AC-coupled

DC-coupled

elements

ideal system

jitter components

jitter requirements

pre-emphasis technique

pulse-shaping technique

real system

reliability/durability

transmitter

Hyperspectral imaging. See Spectral imaging

I

Industrial design (ID)

Idle power management

Immunity testing

Incremental, iterative, and agile models

Ingredients

batteries

camera

communication module

display

external

internal

key considerations

flight controllers

interconnect ( see Interconnects)

mechanicals

memory system

storage solution

system on a chip

thermal solution

Integration testing

Interconnects

board-to-board (BTB) connectors

definition of

electrical connections

Ethernet cables

FPC/FFC connectors

key considerations

mini and micro USB

requirements

RF connector

selection of

wire-to-board connectors

Internal displays

J

Jitter

K

Keep Out Zones (KOZ)

L

Layout design

auto route

board outline

CAD PCB layout

electrical components

electrical constraints

capacitance

cross talk

dielectric absorption

impedance mismatch

mutual inductance

power integrity

proximity of

signal attenuation

signal integrity

skin effect

layer stack-up

mechanical constraints

component locations

coordinate system

design capabilities

design constraints

dimension

Keep Out Zones (KOZ)

orientation

physical constraints

requirements

Netlist

Gerber release

mechanical check

placement

routing

trade-off

Lead acid

Light-emitting diode (LED)

Linear regulator operates

Linux

ACPI methods

callback function

models/protocols/specifications

module loading process

operating context/state

platform/system design

predefined methods

running/active state

standby state

Lithium-Ion (Li-ion) batteries

Load testing

Logistics and operations management

Low speed communications interfaces

M

Magnetic storage devices

Mechanical design

Crop Squad

definition

dependencies

monitor crops

purpose

requirements

air gap

camera module

daughterboard

dimensions of

enclosures

flexible PCB

heat spreader

motherboard

Mylar

processing unit

propeller motor

shielding

stack-up

X-frame

variants

Mechanical items

categories

key considerations

multicopter designs

quadcopter

solutions

Memory systems

block diagram

cache memory

DDR-SDRAM

fifth generation

first generation

fourth generation

key considerations

layer of

load and prolonged operation

mobile DRAM

parameters

requirements

second generation

third generation

Microcontroller/microprocessor

Mobile network

Modulated signals

Monochrome sensors

Multimedia card (MMC)

N

Netlist generation

Nickel Cadmium (NiCd)

Nickel Metal Hydride (NiMH)

Non-functional testing

O

Optical storage devices

P, Q

Parallel data transmission

Passive cooling techniques

Performance testing

Physical constraints

Pilot systems

Pilot testing

Power integrity (PI)

Power management system

Power-on

firmware/software

generation of

input power requirement

inspection

preliminary and sanity checks

sequencing and reset check

short-circuit checks

variation of

Pre-emphasis technique

Product requirement document (PRD)

Printed circuit board assembly (PCBA)

Printed circuit board (PCB)

assembly process

fabrication process

layout design

library development

footprint creation

footprint verification

logical symbol creation

symbol creation

symbol verification

time-consuming task

visual representation

PCBA

Product certification/qualification

accessories cost

device costing

environmental certification ( see Environmental testing certification)

product certification centers

product ecology

California Proposition 65

EU REACH

ISO

prohibited substances

ROHS

WEEE

production cost

registration

regulations

regulatory certification

battery

chemical safety certification

conducted emissions

conducted voltage

EFT immunity test

electrical safety testing

electronic devices

emission testing

electrostatic discharge (ESD)

functional safety

immunity testing

mechanical check

products and characteristics

radiation testing

safety

service and support

Pulse-shaping technique

R

Radiation testing

Radio-frequency (RF)

Real-time operating system (RTOS)

Regression testing

Restriction of Hazardous Substances Directive (ROHS)

RTLinux system architecture

S

Schematics design

best practice

capture

definition

design rules

Netlist generation

nets

reading

reference circuit

reference designator

representation of

symbols

Secure Digital (SD)

Security testing

Serial data transmission

Smoke and sanity testing

Software architecture

application components

categories

firmware components

OS and drivers

sensing, navigation and control

Software development life cycle (SDLC)

incremental, iterative, and agile

software development models

stages/steps

V-shaped model

waterfall model

Software development process

ACPI states

active power management

connected standby power management

considerations

device states

global and system states

idle power management

key attributes

Linux power management

low power

HW considerations

power consumption

power optimization

SW considerations

power state

processor power states

real-time system

requirements

SDLC ( see Software development life cycle (SDLC))

software stack

system bring-up

verification, validation, and maintenance

mechanism

methodology

testing level

Software stack

application layer

architecture

components

firmware and device

hardware

operating system

RTLinux design

RTLinux operating system

SDK and libraries

Solid State Drives (SSD)

Spectral imaging

System requirement document (SRD)

Static random-access memory (SRAM)

Storage device

eMMC and uSSD

features of

flash storage

key parameters

magnetic storage

nonvolatile memory

optical storage

SDXC format

storage solution

Storage temperature

Stress testing

Switching regulators operate

Synchronous vs. asynchronous interfaces

Synchronous dynamic random-access memory (SDRAM)

System design flow

architecture

hardware block diagram

mechanical concept

software

aspects

implementation

logistics and operations management

mechanical design ( see Mechanical design)

requirement specification

software architecture

specifications of

System-on-a-chip (SOC)

categories

component

key considerations

solutions

System pilot build

System power map

System testing

System validation testing

T

Theoretical calculations

Thermal solution

active cooling solutions

architectural design

categories

key features

passive cooling techniques

solution

U

Unit testing

Universal Serial Bus (USB) connection

Unmanned aerial vehicle (UAV)

USB memory stick

User acceptance testing (UAT)

V

V-shaped model

W, X, Y, Z

Waterfall model

White box testing

WiFi+BT

Wire-to-board connection

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Table of Contents for Back Matter

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Index

A

B

C

D

E

F

G

H

I

J

K

L

M

N

O

P, Q

R

S

T

U

V

W, X, Y, Z

Table of Contents for
Back Matter