• It is also known as CCITT V24 standard.

• The standard is divided in four parts:

• RS232 divides the types of transmitter/receivers into either

RS232 Connector Details

The connector system defined in the standard is the 25-way D-type connector, although there is also a 9-pin version which takes advantage of the fact that usually not all 25 pins are used. In fact, most RS232 applications use only nine of the pins and, if necessary, you can get away with using just three.

The pinouts are shown in Figure 5.1 and the pin function is described in Table 5.1.

The asterisks show the signals which must be present for bidirectional data transfer. I have seen unidirectional data transfer systems which conform to a cut-down variant of RS232 with only 2 wires – TD or RD and SG.

Signal Details

Interface Cable Varieties

In the conventional computer to modem link (DTE–DCE) the connection is just made point to point:

However, if the user wants to cut down on the number of lines, then each piece of equipment must be fooled into thinking that the other is in place and ready to go. (The obvious problem is that if for some reason one of the pair is not in place. Not to worry, this can be handled with software handshaking – more later.) When the DTE issues a Request to Send, it expects to get a Clear to Send signal. So, the obvious way to do this is to loop back the RTS into the CTS pin. Figure 5.3 shows the loopback present on both RTS/CTS and DTR/DSR.

Quite often, a designer may wish to use the RS232 protocol to interconnect two DTE equipments, such as two computers or microprocessors. In this case, null modem or crossover connections must be used, as shown in Figure 5.4.

Electrical Signal Characteristics

The RS232 standard uses negative logic and bipolar power supplies, i.e. a logic ‘0’ lies between +3 and +25 volts, while a logic ‘1’ lies between −3 and −25 volts. Figure 5.5 shows the voltage levels as the letter ‘Q’ is transmitted. ‘Q’ has the ASCII value of 51_H and RS232 specifies that bits are transmitted Least Significant Bit first. So,

51_H = 01010001B – transmitted as 10001010

Figure 5.5 shows clearly the rest state of the line as a ‘mark’ or ‘1’. The transmitted byte is framed with a Start and a Stop bit; Start being a logic ‘0’ and Stop being logic ‘1’. (Actually the Stop bit can be of length 1, 1.5 or 2 bit lengths long – as long as the sender and receiver agree beforehand which protocol is to be used, then all is well.)

The next pitfall for RS232 users is that the standard allows for data to be transmitted as 5, 6, 7 or 8 bits, with or without odd or even parity and at a variety of baud rates. This is explained as follows.

Parity is a very simple method of error detection. If parity is enabled, it is declared to be ODD or EVEN and consists of an extra bit between the data bits and the stop bit. If the transmitter and receiver agree to use ODD parity, then the total number of data plus parity bits must add up to an odd number. If EVEN parity is decided upon, then the total number of data plus parity bits must add up to an EVEN number. If NO PARITY is opted for, then the parity bit is omitted, for example:

(‘J’ = 49H = 1001001 in 7-bit binary transmitted LSB first. ‘K’ = 4AH = 1001010 in 7-bit binary transmitted LSB first.)

The baud rate is simply the number of bits per second. Typically, these could be 75, 150, 300, 600, 1200, 2400, 4800, 9600, 19200 etc. This is not the rate at which data is transmitted, however. A 300 baud 8-bit system still requires the start and stop bits, so for each byte of data, 10 bits have to be transmitted. Hence the data rate would be 30 (300/(1 + 8 + 1)) bytes per second.

The rate should also be agreed before transmission commences. However, some equipment is auto-sensing in that it will try to sort out from the first characters transmitted the rate, parity and data size. It helps (or in some cases is essential) if the receiver knows what character to expect first. The space (20_H) is commonly used for this purpose.

All these variables – connection, DTE/DCE, rate, parity, word size – give lots of factors which can stop one device from transmitting to or receiving from another. Despite this, RS232 is still probably the most commonly used serial protocol in the world.

Even the simplest of the 8031 family has an inbuilt capability to handle Serial RS232 data. Example code for the family was shown on page 47 in Chapter 2.

Voltage Level Conversion

One of the difficulties of RS232 from a hardware designer’s point of view used to be the awkward voltages used to characterize a ‘0’ and ‘1’. Fortunately, this is eased by families of ICs which operate from a single +5 V power supply and yet convert the 0/+5 logic signal to and from an RS232 voltage level. Internally these devices have two power supply sections:

One of the first companies to exploit this technology was MAXIM, and Figure 5.6 shows two typical applications using RS232 voltage converters.

Both 8051 and PIC microprocessor families have members which will output RS232 directly, but there are occasions when it is necessary to use the pins of a parallel input/output port. Before deciding to embark on this route, it is as well to consider what tradeoffs you are going to have to live with. In the first place, it is perfectly possible to design a pin output full duplex RS232 interface on a non-interrupt low capability microcontroller. However, it does take up a lot of memory space. Assuming that the IC is going to do something else useful as well as RS232, then it is as well to set some limits.

Electrical Signals

The devices connect to the bus with open collector (or drain) transistors in the output stage of the integrated circuit and so each of the two wires of the bus must have a pull up resistor in the range of 1−10 kΩ, 4.7 kΩ being typical. Schematically, the bus looks like that shown in Figure 5.11.

Master/Slave Relationships

In Figure 5.11 SDA is the Serial Data line and SCL is the Serial Clock line. SCL is always generated by the masters when they try to initiate a data transfer. The data travels along the bidirectional line SDA. If Master 1 and Master 2 try to move data along SDA at the same time, the first one to output a ‘0’ when the other outputs a ‘1’ loses its access rights and has to wait until the other has finished.

At rest (no signal), both SDA and SCL are at logic ‘1’ (+5 V). Normally, SDA can only change when SCL is low – except that

Data is transferred in 8-bit bytes, MSB first. This will take 8 clock pulses, and an acknowledge is sent on the ninth clock pulse. Figure 5.12 shows a simple transfer of the binary word 11001001. The acknowledge is obligatory and indicates to the sending device that the receiving device recognizes and accepts the byte. The acknowledging device pulls the SDA line low to acknowledge.

The first byte sent by the master is an address byte. As mentioned, each device has a minimum of a 7-bit address. For each device type, the first four bits are usually fixed, while the lower three are hardwired on the IC to provide a user programmable address. The eighth bit of the transfer is a read/write control. If bit 8 is ‘0’ then the master is WRITING. If bit 8 is ‘1’ then the master is requesting or READING data. Figure 5.13 shows some of the possible combination of transfers.

MCS51 Control Signals

Many of the 8051 family members can transmit and receive I²C signals. It is of course perfectly possible to program a standard member of the family to output bit by bit signals to other I²C devices. This does seem to be the last resort in a microprocessor so well endowed with interface options. Sometimes cost is the main factor and this may be the spur to go down this road. Intel issues an application note (AP476 – available from many of the bulletin boards and web sites) which gives all the code necessary.

Transmission Protocols

The I²C standard defines operation as masters and slaves and the I²C serial I/O can operate in one of four modes:

However, in most applications, the MCS51 tends to be used as a bus master controlling the slave peripherals and to simplify the explanation of how to use it, I will only present the data for Modes 1 and 2.

As mentioned, a slave must generate an acknowledge after the reception of each byte and a master must generate an acknowledge after the reception of each byte.

If a receiving device cannot receive the data byte immediately, it can force the transmitter into a wait state by holding SCL Low. If the acknowledge is not received, the master should abort the transfer after an appropriate ‘timeout’. There are three I²C Special Function Registers (Table 5.2).

The Serial Control Register S1CON is used as shown in Table 5.3.

The serial status register S1STA only uses the upper 5 bits. These carry a status code which act (if enabled) as an interrupt vector to a service routine. The vectors lie half way between the normal interrupt service vectors, so there is just room in the vector address to fit a jmp location instruction to handle the interrupt. The lower 3 bits are set as 000.

S1DAT contains the data to be written out or the data which has been received.

S1ADR can be loaded with the 7-bit slave address to which the controller will respond if programmed as a slave receiver/transmitter. Bit 0 when set determines whether the general call address is to be recognized.

Modes of Operation

The first step must be to set interrupts with instructions such as

Thereafter, issuing setb sta would cause the START sequence to be commenced. Once the I²C master has determined that the bus is free for use and issued the start sequence, the SI flag will be set and the CPU should vector to location 08 as shown in Table 5.7. The code pointed to at this address should load the slave address into the S1DAT register and set the LSB according to whether the data is to be written or read. Lastly, the Interrupt Service Routine should reset SI ready for the next part of the transfer. Once acknowledge has been received from the slave, the SI flag will once again be set and the CPU will vector to either 18, 20 or 38 depending on whether the address was received, not received or lost. These vector addresses must hold code to deal with each situation appropriately (see Table 5.8).

Although this seems complicated, most of the difficulty in programming is in coping with error situations. As always, software gets a bad reputation when code fails to work because the programmer did not cater for every possible outcome.

There are two other tables of data relating to the use of the ‘552 as a slave. The 8x552 data sheet from Intel or one of the second source suppliers would provide all the register data. If your own assembler is not specifically for the 8x552, then the additional SFR locations and bit names will have to be declared in an equate list.

Capture and Compare Logic

Timer 2 is connected to four 16-bit capture and three 16-bit compare registers. Capture registers save the contents of Timer T2 when a transition (0−1 or 1−0) occurs on its corresponding input pin. These are the alternate functions of Port 4 on a ‘552 and port 1 on a ‘751. To continue the analysis on the ‘751, since individual models differ in detail, essentially there are many common elements between them. If the capture facility is not needed, the four input pins can be used to generate four additional external interrupts. The capture control registers are

A repeated external event such as t1, t2, t3 or t4 in Figure 5.14 can easily be measured. A capture register can be used to store the contents of T2 when the ‘start’ event occurs, and then this number can be subtracted from the updated value of T2 when the ‘stop’ event occurs.

A related function can be achieved with the three 16-bit compare registers. Every time that timer T2 is incremented, the new value is compared with the contents of CM0, CM1 and CM2. If a match is found then the appropriate interrupt flag in TM2IR is set.

1. hundreds of a second

2. seconds

3. minutes

4. hours

5. year/date

6. weekdays/months.

• write to the PCF8593 to initialize or set registers or set alarms

• read from the PCF8593 to determine time or date information in the following communication sequences: