12
SYNTHESIS OF DC AND LOW-FREQUENCY SINUSOIDAL AC VOLTAGES FOR MOTOR DRIVES, UPS, AND POWER SYSTEMS APPLICATIONS

12.1 INTRODUCTION

The importance of power electronics applications for motor drives (AC and DC), UPS, and in power systems was described in Chapter 11. In many of these applications, the voltage-link structure of Figure 12.1 is used, where our emphasis will be to discuss how the load-side converter, with the DC voltage as input, synthesizes DC or low-frequency sinusoidal voltage outputs. Functionally, this converter operates as a linear amplifier, amplifying a control signal, DC in case of DC motor drives, and AC in case of AC motor drives, UPS, and other utility-related applications. The power flow through this converter should be reversible.

FIGURE 12.1 Voltage-link system.

These converters consist of bidirectional switching power-poles, discussed in Chapter 3, two in the case of DC motor drives and single-phase AC applications, and three in the case of AC motor drives and three-phase applications. These are shown for DC and AC motor drives in Figures 12.2a and 12.2b, respectively.

FIGURE 12.2 Converters for DC and AC motor drives.

12.2 BIDIRECTIONAL SWITCHING POWER-POLE AS THE BUILDING BLOCK

In buck and boost DC-DC converters, discussed in Chapter 3, implementation of the switching power-pole by one transistor and one diode dictates the instantaneous current flow to be unidirectional. However, as shown in Figure 12.3a, combining the switching power-pole implementations of buck and boost converters, where the two transistors are switched by complementary signals, allows a continuous bidirectional power and current capability. In such a bidirectional switching power-pole, the positive inductor current i Subscript upper L as shown in Figure 12.3b, represents a buck-mode of operation, where only the transistor and the diode associated with the buck converter take part. The transistor conducts during q equals 1, and the diode conducts during q equals 0. Similarly, as shown in Figure 12.3c, the negative inductor current represents a boost-mode of operation, where only the transistor and the diode associated with the boost converter take part. The transistor conducts during q equals 0 (q Superscript minus Baseline equals 1), and the diode conducts during q equals 1 (q Superscript minus Baseline equals 0).

FIGURE 12.3 Bidirectional power flow through a switching power-pole.

Figures 12.3b and 12.3c show that the combination of devices in Figure 12.3a renders it to be a switching power-pole that can carry i Subscript upper L in either direction. This is shown as an equivalent switch in Figure 12.4a that is effectively in the “up” position when q equals 1, as shown in Figure 12.4b, and in the “down” position when q equals 0, as shown in Figure 12.4c, regardless of the direction of i Subscript upper L.

FIGURE 12.4 Bidirectional switching power-pole.

The bidirectional switching power-pole of Figure 12.4a is repeated in Figure 12.5a for pole-a, with its switching signal identified as q Subscript a. In response to the switching signal, it behaves similarly to the switching power-pole in Chapter 3: “up” when q Subscript a Baseline equals 1 and otherwise “down.” Therefore, its switching-cycle-averaged representation is also an ideal transformer, shown in Figure 12.5b, with a turns ratio 1 colon d Subscript a Baseline left-parenthesis t right-parenthesis.

FIGURE 12.5 Switching-cycle-averaged representation of the bidirectional power pole.

The switching-cycle-averaged values of the variables at the voltage port and the current port in Figure 12.5b are related by d Subscript a Baseline left-parenthesis t right-parenthesis as follows:

v overbar Subscript a upper N Baseline equals d Subscript a Baseline upper V Subscript d(12.1)
i overbar Subscript d a Baseline equals d Subscript a Baseline i overbar Subscript a Baseline period(12.2)

We should note that, ideally, unlike switching power-poles with a single transistor, discussed in Chapter 3, no discontinuous-conduction mode exists in a bidirectional switching pole of Figure 12.5a.

12.2.1 Pulse-Width Modulation (PWM) of the Bidirectional Switching Power-Pole

The voltage of a switching power-pole at the current port is always of positive polarity. However, the output voltages of converters in Figure 12.2 for motor drives and other AC applications must be reversible in polarity. This is achieved by introducing a common-mode voltage in each power pole as discussed below and taking the differential output between the power poles.

To obtain the desired switching-cycle-averaged voltage v overbar Subscript a upper N in Figure 12.5, which includes the common-mode voltage, requires the following power-pole duty ratio from Equation 12.1:

d Subscript a Baseline equals StartFraction v overbar Subscript a upper N Baseline Over upper V Subscript d Baseline EndFraction comma(12.3)

where upper V Subscript d is the DC-bus voltage. To obtain the switching signal q Subscript a to deliver this duty ratio, a control voltage v Subscript c n t r l comma a is compared with a triangular-shaped carrier waveform of the switching frequency f Subscript s and amplitude ModifyingAbove upper V With ˆ Subscript t r i, as shown in Figure 12.6. Because of symmetry, only upper T Subscript s Baseline slash 2, one-half of the switching time period, needs to be considered. The switching-signal q Subscript a Baseline equals 1 if v Subscript c n t r l comma a Baseline greater-than v Subscript t r i and is otherwise 0. Therefore in Figure 12.6,

v Subscript c n t r l comma a Baseline equals d Subscript a Baseline ModifyingAbove upper V With ˆ Subscript t r i Baseline period(12.4)

FIGURE 12.6 Waveforms for PWM in a switching power-pole.

The switching-cycle-averaged representation of the switching power-pole in Figure 12.7a is shown by a controllable turn-ratio ideal transformer in Figure 12.7b, where the switching-cycle-averaged representation of the duty-ratio control is in accordance with Equation 12.4.

FIGURE 12.7 Switching power-pole and its duty-ratio control.

The reason for selecting a triangular carrier-signal waveform, as opposed to a ramp signal in DC-DC converters of Chapter 3, is that it minimizes the harmonic content in the output voltage waveform for a given frequency with which the converter devices are switched. The Fourier spectrum of the switching waveform v Subscript a upper N is shown in Figure 12.8, which depends on the nature of the control signal. If the control voltage is DC, the output voltage has harmonics at the multiples of the switching frequency, that is at f Subscript s, 2 f Subscript s, and so on, as shown in Figure 12.8a. If the control voltage varies at a low frequency f 1, as in AC motor drives and UPS, then the harmonics of significant magnitudes appear in the side bands of the switching frequency and its multiples, as shown in Figure 12.8b, where

FIGURE 12.8 Harmonics in the output of a switching power-pole.

f Subscript h Baseline equals k 1 f Subscript s Baseline plus ModifyingBelow k 2 f 1 With presentation form for vertical right-brace Underscript s i d e b a n d s Endscripts comma(12.5)

in which k 1 and k 2 are constants that can take on values 1, 2, 3, and so on. Some of these harmonics associated with each power pole are canceled from the converter output voltages, where two or three of such power poles are used.

In the power pole shown in Figure 12.7, the output voltage v Subscript a upper N and its switching-cycle-averaged v overbar Subscript a upper N are limited between 0 and upper V Subscript d. To obtain an output voltage v overbar Subscript a n (where “n” may be a fictitious node) that can become both positive and negative, a common-mode offset v overbar Subscript c o m is introduced in each power pole so that the pole output voltage is

v overbar Subscript a upper N Baseline equals v overbar Subscript c o m Baseline plus v overbar Subscript a n Baseline comma(12.6)

where v overbar Subscript c o m allows v overbar Subscript a n to become both positive and negative around the common-mode voltage v overbar Subscript c o m. In the differential output, when two or three power poles are used, the common-mode voltage gets eliminated.

12.3 CONVERTERS FOR DC MOTOR DRIVES (minus upper V Subscript d Baseline less-than v overbar Subscript o Baseline less-than upper V Subscript d)

Converters for DC motor drives consist of two power poles, as shown in Figure 12.9a, where

FIGURE 12.9 Converter for DC motor drive.

v overbar Subscript o Baseline equals v overbar Subscript a upper N Baseline minus v overbar Subscript b upper N Baseline comma(12.7)

and v overbar Subscript o can assume both positive and negative values. Since the output voltage is desired to be in a full range, from minus upper V Subscript d to plus upper V Subscript d, pole-a is assigned to produce v overbar Subscript o Baseline slash 2, and pole-b is assigned to produce minus v overbar Subscript o slash 2 toward the output:

StartLayout 1st Row 1st Column v overbar Subscript a n Baseline equals StartFraction v overbar Subscript o Baseline Over 2 EndFraction and 2nd Column v overbar Subscript b n Baseline equals minus StartFraction v overbar Subscript o Baseline Over 2 EndFraction EndLayout comma(12.8)

where “n” is a fictitious node, as shown in Figure 12.9a, chosen to define the contribution of each pole toward v overbar Subscript o.

To achieve equal excursions in positive and negative values of the switching-cycle-averaged output voltage, the switching-cycle-averaged common-mode voltage in each pole is chosen to be one-half the DC-bus voltage,

v overbar Subscript c o m Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction period(12.9)

Therefore, from Equation 12.6,

StartLayout 1st Row 1st Column v overbar Subscript a upper N Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction plus StartFraction v overbar Subscript o Baseline Over 2 EndFraction 2nd Column and v overbar Subscript b upper N Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction minus StartFraction v overbar Subscript o Baseline Over 2 EndFraction EndLayout period(12.10)

The switching-cycle-averaged output voltages of the power poles and the converter are shown in Figure 12.9b. From Equations 12.3 and 12.10,

StartLayout 1st Row 1st Column d Subscript a Baseline equals one-half plus one-half StartFraction v overbar Subscript o Baseline Over upper V Subscript d Baseline EndFraction 2nd Column and d Subscript b Baseline equals one-half minus one-half StartFraction v overbar Subscript o Baseline Over upper V Subscript d Baseline EndFraction EndLayout comma(12.11)

and from Equation 12.11,

v overbar Subscript o Baseline equals left-parenthesis d Subscript a Baseline minus d Subscript b Baseline right-parenthesis upper V Subscript d Baseline period(12.12)

Example 12.1

In a DC motor drive, the DC-bus voltage is upper V Subscript d Baseline equals 350 normal upper V. Determine the following: v overbar Subscript c o m, v overbar Subscript a upper N, and d Subscript a for pole-a and similarly for pole-b, if the output voltage required is (a) v overbar Subscript 0 Baseline equals 300 upper V and (b) v overbar Subscript 0 Baseline equals 300 upper V.

Solution From Equation 12.9, v overbar Subscript c o m Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction equals 175 upper V.

a. For v overbar Subscript 0 Baseline equals 300 upper V, from Equation 12.8, v overbar Subscript b n Baseline equals minus v overbar Subscript o Baseline slash 2 equals negative 150 upper V and v overbar Subscript b upper N Baseline equals 25 upper V. From Equation 12.10, v overbar Subscript a upper N Baseline equals 325 upper V and v overbar Subscript b upper N Baseline equals 25 upper V. From Equation 12.11, d Subscript a Baseline asymptotically-equals 0.93 and d Subscript b Baseline asymptotically-equals 0.07.

b. For v overbar Subscript 0 Baseline equals negative 300 upper V, v overbar Subscript a n Baseline equals v overbar Subscript o Baseline slash 2 equals negative 150 upper V and v overbar Subscript b n Baseline equals minus v overbar Subscript o Baseline slash 2 equals 150 upper V. Therefore from Equation 12.10, v overbar Subscript a upper N Baseline equals 25 upper V and v overbar Subscript b upper N Baseline equals 325 upper V. From Equation 12.11, d Subscript a Baseline asymptotically-equals 0.07 and d Subscript b Baseline asymptotically-equals 0.93.

The switching-cycle-averaged representation of the two power poles, along with the pulse-width modulator, in a block diagram form is shown in Figure 12.10.

FIGURE 12.10 Switching-cycle-averaged representation of the converter for DC drives.

In each power pole of Figure 12.10, the switching-cycle-averaged DC-side current is related to its output current by the pole duty ratio,

StartLayout 1st Row 1st Column i overbar Subscript d a Baseline equals d Subscript a Baseline i overbar Subscript a Baseline 2nd Column and i overbar Subscript d b Baseline equals d Subscript b Baseline i overbar Subscript b Baseline EndLayout period(12.13)

By Kirchhoff’s current law, the total switching-cycle-averaged DC-side current is

i overbar Subscript d Baseline equals i overbar Subscript d a Baseline plus i overbar Subscript d b Baseline equals d Subscript a Baseline i overbar Subscript a Baseline plus d Subscript b Baseline i overbar Subscript b Baseline period(12.14)

Recognizing the directions with which the currents i Subscript a and i Subscript b are defined,

ModifyingAbove i With bar Subscript a Baseline left-parenthesis t right-parenthesis equals minus ModifyingAbove i With bar Subscript b Baseline left-parenthesis t right-parenthesis equals ModifyingAbove i With bar Subscript o Baseline left-parenthesis t right-parenthesis period(12.15)

Thus, substituting currents from Equation 12.14 into Equation 12.15,

i overbar Subscript d Baseline equals left-parenthesis d Subscript a Baseline minus d Subscript b Baseline right-parenthesis i overbar Subscript o Baseline period(12.16)

Example 12.2

In the DC motor drive of Example 12.1, the output current into the motor is i overbar Subscript o Baseline equals 15 normal upper A. Calculate the power delivered from the DC-bus and show that it is equal to the power delivered to the motor (assuming the converter to be lossless), if v overbar Subscript 0 Baseline equals 300 normal upper V.

Solution Using the values for d Subscript a and d Subscript b from part (a) of Example 12.1, and i overbar Subscript o Baseline equals 15 normal upper Afrom Equation 12.16, ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals 12.9 normal upper A and therefore the power delivered by the DC-bus is upper P Subscript d Baseline equals 4.515 kW. Power delivered by the converter to the motor is upper P Subscript o Baseline equals v overbar Subscript o Baseline i overbar Subscript o Baseline equals 4.5 kW, which is equal to the input power (neglecting the round-off errors).

Using Equations 12.4 and 12.11, the control voltages for the two poles are as follows:

StartLayout 1st Row 1st Column v Subscript c n t r l comma a Baseline equals StartFraction ModifyingAbove upper V With ˆ Subscript t r i Baseline Over 2 EndFraction plus StartFraction ModifyingAbove upper V With ˆ Subscript t r i Baseline Over 2 EndFraction left-parenthesis StartFraction v overbar Subscript o Baseline Over upper V Subscript d Baseline EndFraction right-parenthesis 2nd Column and v Subscript c n t r l comma b Baseline equals StartFraction ModifyingAbove upper V With ˆ Subscript t r i Baseline Over 2 EndFraction minus StartFraction ModifyingAbove upper V With ˆ Subscript t r i Baseline Over 2 EndFraction left-parenthesis StartFraction v overbar Subscript o Baseline Over upper V Subscript d Baseline EndFraction right-parenthesis EndLayout period(12.17)

In Equation 12.17, defining the second term in the two control voltages above as one-half the control voltage, that is,

StartFraction v Subscript c n t r l Baseline Over 2 EndFraction equals StartFraction ModifyingAbove upper V With ˆ Subscript t r i Baseline Over 2 EndFraction left-parenthesis StartFraction v overbar Subscript o Baseline Over upper V Subscript d Baseline EndFraction right-parenthesis period(12.18)

Equation 12.18 simplifies as follows:

v overbar Subscript o Baseline equals left-parenthesis StartFraction upper V Subscript d Baseline Over ModifyingBelow ModifyingAbove upper V With caret Subscript t r i Baseline With presentation form for vertical right-brace Underscript k Subscript upper P upper W upper M Baseline Endscripts EndFraction right-parenthesis v Subscript c n t r l Baseline comma(12.19)

where left-parenthesis upper V Subscript d Baseline slash ModifyingAbove upper V With ˆ Subscript t r i Baseline right-parenthesis is the converter gain k Subscript upper P upper W upper M, from the feedback control signal to the switching-cycle-averaged voltage output, as shown in Figure 12.11 in a block diagram form.

FIGURE 12.11 Gain of the converter for DC drives.

12.3.1 Switching Waveforms in a Converter for DC Motor Drives

We will look further into the switching details of the converter in Figure 12.9a. To produce a positive output voltage, the control voltages are shown in Figure 12.12. Only one-half of the time period, upper T Subscript s Baseline slash 2, needs to be considered due to symmetry.

FIGURE 12.12 Switching voltage waveforms in a converter for DC drive.

The pole output voltages v Subscript a upper N and v Subscript b upper N have the same waveform as the switching signals except for their amplitude. The output voltage v Subscript o waveform shows that the effective switching frequency at the output is twice the original. That is, within the time period of the switching frequency f Subscript s with which the converter devices are switching, there are two complete cycles of repetition. Therefore, the harmonics in the output are at left-parenthesis 2 f Subscript s Baseline right-parenthesis and at its multiples. If the switching frequency is selected sufficiently large, the motor inductance may be enough to keep the ripple in the output current within an acceptable range without the need for an external inductor in series.

Next, we will look at the currents associated with this converter, repeated in Figure 12.13. The pole currents i Subscript a Baseline equals i Subscript o and i Subscript b Baseline equals minus i Subscript o. The DC-side current i Subscript d Baseline equals i Subscript d a Baseline plus i Subscript d b. The waveforms for these currents are shown by means of Example 12.3.

FIGURE 12.13 Currents defined in the converter for DC motor drives.

Example 12.3

In the DC motor drive of Figure 12.13, assume the operating conditions are as follows: upper V Subscript d Baseline equals 350 normal upper V, e Subscript a Baseline equals 236 normal upper V left-parenthesis d c right-parenthesis, and i overbar Subscript o Baseline equals 4 normal upper A. The switching frequency f Subscript s is 20 kHz. Assume that the series resistance upper R Subscript a associated with the motor is 0.5 normal upper Omega. Calculate the series inductance upper L Subscript a necessary to keep the peak-peak ripple in the output current to be 1.0 normal upper A at this operating condition. Assume that ModifyingAbove upper V With caret Subscript t r i Baseline equals 1 normal upper V. Plot v Subscript o, v overbar Subscript o, i Subscript o, and i Subscript d.

Solution As seen from Figure 12.12, the output voltage v Subscript o is a pulsating waveform that consists of a DC switching-cycle-averaged v overbar Subscript o plus a ripple component v Subscript o comma r i p p l e, which contains sub-components that are at very high frequencies (the multiples of 2 f Subscript s):

v Subscript o Baseline equals v overbar Subscript o Baseline plus v Subscript o comma r i p p l e Baseline period(12.20)

Therefore, the resulting current i Subscript o consists of a switching-cycle-averaged DC component i overbar Subscript o and a ripple component i Subscript o comma r i p p l e:

i Subscript o Baseline equals i overbar Subscript o Baseline plus i Subscript o comma r i p p l e Baseline period(12.21)

For a given v Subscript o, we can calculate the output current by means of superposition by considering the circuit at DC and the ripple frequency (the multiples of 2 f Subscript s), as shown in Figures 12.14a and 12.14b, respectively. In the DC circuit, the series inductance has no effect and hence is omitted from Figure 12.14a. In the ripple-frequency circuit of Figure 12.14b, the back-emf e Subscript a, that is DC, is suppressed along with the series resistance upper R Subscript a, which generally is negligible compared to the inductive reactance of upper L Subscript a at very frequencies associated with the ripple.

FIGURE 12.14 Superposition of DC and ripple-frequency variables.

From the circuit of Figure 12.14a,

v overbar Subscript o Baseline equals e Subscript a Baseline plus upper R Subscript a Baseline i overbar Subscript o Baseline equals 238 normal upper V period(12.22)

The switching waveforms are shown in Figure 12.15, which is based on Figure 12.12, where the details are shown for the first half-cycle. The output voltage v Subscript o pulsates between 0 and upper V Subscript d Baseline equals 350 normal upper V, where from Equation 12.11, d Subscript a Baseline equals 0.84, and d Subscript b Baseline equals 0.16. At f Subscript s Baseline equals 20 kHz, upper T Subscript s Baseline equals 50 mu normal s. Using Equations 12.20 and 12.22, the ripple voltage waveform is also shown in Figure 12.15, where during StartFraction d Subscript a Baseline minus d Subscript b Baseline Over 2 EndFraction upper T Subscript s Baseline left-parenthesis equals 17.0 mu normal s right-parenthesis, the ripple voltage in the circuit of Figure 12.14b is 112 normal upper V. Therefore, during this time interval, the peak-to-peak ripple upper Delta upper I Subscript p minus p in the inductor current can be related to the ripple voltage as follows:

upper L Subscript a Baseline StartFraction upper Delta upper I Subscript p minus p Baseline Over left-parenthesis d Subscript a Baseline minus d Subscript b Baseline right-parenthesis upper T Subscript s Baseline slash 2 EndFraction equals 112 normal upper V period(12.23)

FIGURE 12.15 Switching current waveforms in Example 12.3.

Substituting the values in the equation above with upper Delta upper I Subscript p minus p Baseline equals 1 normal upper A, upper L Subscript a Baseline equals 1.9 mH. As shown in Figure 12.15, the output current increases linearly during left-parenthesis d Subscript a Baseline minus d Subscript b Baseline right-parenthesis upper T Subscript s slash 2, and its waveform is symmetric around the switching-cycle-averaged value; that is, it crosses the switching-cycle-averaged value at the midpoint of this interval. The ripple waveform in other intervals can be found by symmetry. The DC-side current i Subscript d flows only during left-parenthesis d Subscript a Baseline minus d Subscript b Baseline right-parenthesis upper T Subscript s slash 2 interval; otherwise, it is zero, as shown in Figure 12.15. Averaging over upper T Subscript s Baseline slash 2, the switching-cycle-averaged DC-side current i overbar Subscript d Baseline equals 2.72 normal upper A.

12.4 SYNTHESIS OF LOW-FREQUENCY AC

The principle of synthesizing a DC voltage for DC motor drives can be extended for synthesizing low-frequency AC voltages, so long as the frequency f 1 of the AC being synthesized is two or three orders of magnitude smaller than the switching frequency f Subscript s. This is the case in most AC motor drives and UPS applications where f 1 is at 60 Hz (or is of the order of 60 Hz) and the switching frequency is a few tens of a kilohertz. The control voltage, which is compared with a triangular waveform voltage to generate switching signals, varies slowly at the frequency f 1 of the AC voltage being synthesized.

Therefore, with f 1 less-than less-than f Subscript s, during a switching-frequency time period upper T Subscript s Baseline left-parenthesis equals 1 slash f Subscript s Baseline right-parenthesis, the control voltage can be considered pseudo-DC, and the analysis and synthesis for the converter for DC drives applies. Figure 12.16 shows how the switching power-pole output voltage can be synthesized so, on switching-cycle-averaged, it varies as shown at the low frequency f 1, where at any instant “under the microscope” shows the switching signal waveform with the duty ratio that depends on the switching-cycle-averaged voltage being synthesized. The limit on switching-cycle-averaged power-pole voltage is between 0 and upper V Subscript d, as in the case of converters for DC drives.

FIGURE 12.16 Waveforms of a switching power-pole to synthesize low-frequency AC.

The switching-cycle-averaged representation of the switching power-pole in Figure 12.5a is, as shown earlier in Figure 12.5b, represented by an ideal transformer with a controllable turns ratio. The harmonics in the output of the power pole in a general form were shown earlier by Figure 12.8b. In the following sections, two switching power-poles are used to synthesize single-phase AC voltage for single-phase UPS and for interfacing with a single-phase supply voltage, and three switching power-poles are used to synthesize three-phase AC for motor drives, UPS, and utility-related applications.

12.5 SINGLE-PHASE INVERTERS

The load-side converter of 1-phase UPS, or for interfacing with the single-phase utility grid, is similar in power topology to that in DC motor drives, as shown in Figure 12.17a. The switching-cycle-averaged representation is shown in Figure 12.17b. It consists of two switching power-poles where, as shown, the inductance of the low-pass filter establishes the current ports of the two power poles.

FIGURE 12.17 Single-phase uninterruptible power supply.

The switching-cycle-averaged voltages being synthesized are shown in Figure 12.18, which in this application are sinusoidal at the line frequency f 1,

v overbar Subscript o Baseline equals ModifyingAbove upper V With ˆ Subscript o Baseline sine omega 1 t period(12.24)

FIGURE 12.18 Switching-cycle-averaged voltages in a single-phase UPS.

Similar to DC motor drives, the common-mode voltage is

v overbar Subscript c o m Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction comma(12.25)

and the pole output voltages with respect to a hypothetical neutral “n” are

StartLayout 1st Row 1st Column v overbar Subscript a n Baseline equals StartFraction v overbar Subscript o Baseline Over 2 EndFraction 2nd Column and v overbar Subscript b n Baseline equals minus StartFraction v overbar Subscript o Baseline Over 2 EndFraction EndLayout period(12.26)

Therefore, as shown in Figure 12.18, the switching-cycle-averaged voltages are as follows:

StartLayout 1st Row 1st Column v overbar Subscript a upper N Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction plus StartFraction v overbar Subscript o Baseline Over 2 EndFraction 2nd Column and v overbar Subscript b upper N Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction minus StartFraction v overbar Subscript o Baseline Over 2 EndFraction EndLayout period(12.27)

On the DC-side, in order to calculate the switching-cycle-averaged current drawn from the DC source, we will assume that the switching-cycle-averaged AC-side current is sinusoidal and lagging behind the output AC voltage ModifyingAbove v With bar Subscript o Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper V With ˆ Subscript o Baseline sine omega 1 t by an angle phi 1, as shown in Figure 12.19:

ModifyingAbove i With bar Subscript o Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper I With ˆ Subscript o Baseline sine left-parenthesis omega 1 t minus phi 1 right-parenthesis(12.28)

FIGURE 12.19 Output voltage and current.

Assuming the ripple in the output current to be negligible, the average output power equals the product of the switching-cycle-averaged output voltage v overbar Subscript o and the switching-cycle-averaged output current i overbar Subscript o,

upper P Subscript o Baseline equals v overbar Subscript o Baseline i overbar Subscript o Baseline period(12.29)

Assuming the converter to be lossless, the switching-cycle-averaged input current can be calculated by equating the input power to the average power:

StartLayout 1st Row i overbar Subscript d Baseline equals StartFraction v overbar Subscript o Baseline i overbar Subscript o Baseline Over upper V Subscript d Baseline EndFraction equals StartFraction ModifyingAbove upper V With caret Subscript 0 Baseline ModifyingAbove upper I With caret Subscript o Baseline Over upper V Subscript d Baseline EndFraction s i n omega 1 t times s i n left-parenthesis omega 1 t minus phi 1 right-parenthesis 2nd Row equals ModifyingBelow 0.5 StartFraction ModifyingAbove upper V With caret Subscript o Baseline Over upper V Subscript d Baseline EndFraction ModifyingAbove upper I With caret Subscript o Baseline c o s phi 1 With presentation form for vertical right-brace Underscript upper I Subscript d Baseline Endscripts minus ModifyingBelow 0.5 StartFraction ModifyingAbove upper V With caret Subscript o Baseline Over upper V Subscript d Baseline EndFraction ModifyingAbove upper I With caret Subscript o Baseline c o s left-parenthesis 2 omega 1 t minus phi 1 right-parenthesis With presentation form for vertical right-brace Underscript i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis Endscripts EndLayout comma(12.30)

which shows that the switching-cycle-averaged current drawn from the DC-bus has a DC component upper I Subscript d that is responsible for the average power transfer to the AC side of the converter, and a second harmonic component i Subscript d Baseline 2 (at twice the frequency of the AC output), which is undesirable. The DC-link storage in a 1-phase inverter must be sized to accommodate the flow of this large AC current at twice the output frequency, similar to that in PFCs, discussed in Chapter 6. Of course, we should not forget that the above discussion is in terms of switching-cycle-averaged representation of the switching power-poles. Therefore, the DC-link capacitor must also accommodate the flow of switching-frequency ripple in i Subscript d, discussed below. The pulsating current ripple in i Subscript d Baseline left-parenthesis t right-parenthesis can be bypassed from being supplied by the batteries by placing a high-quality capacitor with a very low equivalent series inductance in close physical proximity to the converter switches.

12.5.1 Switching Waveforms Associated with a Single-Phase Inverter

The switching waveforms in a single-phase converter are shown by means of an example below.

Example 12.4

In a single-phase UPS, shown in Figure 12.17a, the parameters and the operating conditions are as follows: upper V Subscript d Baseline equals 200 normal upper V, f 1 equals 60 Hz, v overbar Subscript o Baseline equals 160 sine omega 1 t volts, and the switching frequency f Subscript s Baseline equals 40 kHz. At the positive peak of the voltage waveform to be synthesized, calculate and plot the switching waveforms for one cycle of the switching frequency.

At the positive peak, the switching-cycle-averaged voltage to be synthesized is v overbar Subscript o Baseline equals 160 normal upper V. Therefore, using the equations for the DC drive converters, from Equation 12.11, d Subscript a Baseline equals 0.9 and d Subscript b Baseline equals 0.1, where upper T Subscript s Baseline equals 25 mu normal s. Assuming ModifyingAbove upper V With ˆ Subscript t r i Baseline equals 1 normal upper V, from Equation 12.4, upper V Subscript c n t r l comma a Baseline equals 0.9 normal upper V, and upper V Subscript c n t r l comma b Baseline equals 0.1 normal upper V. The resulting voltage waveforms are shown in Figure 12.20.

FIGURE 12.20 Waveforms in the UPS of Example 12.4.

As shown in Figure 12.20, the output voltage waveform pulsates at the switching frequency, and a low-pass filter is necessary to remove the output voltage harmonics, which were discussed earlier in a generic manner for each switching power-pole and expressed by Equation 12.5.

12.5.2 Simulation and Hardware Prototyping

The simulation of a single-phase inverter is demonstrated by means of an example:

Example 12.5

A single-phase inverter is connected to an upper R upper L load, upper R equals 8 upper Omega, and upper L equals 1 m normal upper H. The DC voltage upper V Subscript d c Baseline equals 200 normal upper V. The desired output voltage is 120 normal upper V RMS at 60 Hz. Simulate this converter using LTspice.

Solution

The simulation file used in this example is available on the accompanying website. The LTspice model is shown in Figure 12.21, and the steady-state waveforms from the simulation of this converter are shown in Figure 12.22.

FIGURE 12.21 LTspice model.

FIGURE 12.22 LTspice simulation results.

The same control algorithm used in Example 12.5 is implemented in Workbench, as shown in Figure 12.23, to generate a sinusoidal voltage from DC using the Sciamble lab kit.

FIGURE 12.23 Workbench model.

In the hardware, the available DC-bus voltage is upper V Subscript d c Baseline equals 15 normal upper V,and this is used to generate a 10.6 normal upper V RMS, 60 Hz output voltage, as shown in Figure 12.24. The switching frequency is chosen to be f Subscript s Baseline equals 20 k upper H z. The step-by-step procedure for re-creating the above hardware implementation is presented in [1].

FIGURE 12.24 Workbench hardware results: (1) Output current, and (3) Output voltage.

12.6 THREE-PHASE INVERTERS

Converters for three-phase outputs consist of three power poles, as shown in Figure 12.25a. The application may be motor drives, three-phase UPS, or a three-phase utility system. The switching-cycle-averaged representation is shown in Figure 12.25b.

FIGURE 12.25 Three-phase converter.

In Figure 12.25, v overbar Subscript a n, v overbar Subscript b n and v overbar Subscript c n are the desired balanced three-phase switching-cycle-averaged voltages to be synthesized: v overbar Subscript a n Baseline equals ModifyingAbove upper V With ˆ Subscript p h Baseline sine left-parenthesis omega 1 t right-parenthesis, v overbar Subscript a n Baseline equals ModifyingAbove upper V With ˆ Subscript p h Baseline sine left-parenthesis omega 1 t right-parenthesis and v overbar Subscript c n Baseline equals ModifyingAbove upper V With ˆ Subscript p h Baseline sine left-parenthesis omega 1 t minus 240 degree right-parenthesis. In series with these, common-mode voltages are added such that,

v overbar Subscript a upper N Baseline equals v overbar Subscript c o m Baseline plus v overbar Subscript a n Baseline v overbar Subscript b upper N Baseline equals v overbar Subscript c o m Baseline plus v overbar Subscript b n Baseline v overbar Subscript c upper N Baseline equals v overbar Subscript c o m Baseline plus v overbar Subscript c n Baseline period(12.31)

These voltages are shown in Figure 12.26a. The common-mode voltages do not appear across the load; only v overbar Subscript a n, v overbar Subscript b n, and v overbar Subscript c n appear across the load with respect to the load neutral. This can be illustrated by applying the principle of superposition to the circuit in Figure 12.26a.

FIGURE 12.26 Switching-cycle-averaged output voltages in a three-phase converter.

By “suppressing” v overbar Subscript a n, v overbar Subscript b n, and v overbar Subscript c n, only equal common-mode voltages are present in each phase, as shown in Figure 12.26b. If the current in one phase is i, then it will be the same in the other two phases. By Kirchhoff’s current law at the load neutral, 3 i equals 0 and hence i equals 0, and therefore, the common-mode voltages do not appear across the load phases.

To obtain the switching-cycle-averaged currents drawn from the voltage port of each switching power-pole, we will assume the currents drawn by the motor load in Figure 12.25b to be sinusoidal but lagging with respect to the switching-cycle-averaged voltages in each phase by an angle phi 1, where ModifyingAbove v With bar Subscript a n Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper V With ˆ Subscript p h Baseline sine omega 1 t and so on:

StartLayout 1st Row ModifyingAbove i With bar Subscript a Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper I With ˆ sine left-parenthesis omega 1 t minus phi 1 right-parenthesis comma ModifyingAbove i With bar Subscript b Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper I With ˆ sine left-parenthesis omega 1 t minus phi 1 minus 120 degree right-parenthesis comma 2nd Row ModifyingAbove i With bar Subscript c Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper I With ˆ sine left-parenthesis omega 1 t minus phi 1 minus 240 degree right-parenthesis EndLayout period(12.32)

Assuming that the ripple in the output currents is negligibly small, the average power output of the converter can be written as

upper P Subscript o Baseline equals v overbar Subscript a upper N Baseline i overbar Subscript a Baseline plus v overbar Subscript b upper N Baseline i overbar Subscript b Baseline plus v overbar Subscript c upper N Baseline i overbar Subscript c Baseline period(12.33)

Equating the average output power to the power input from the DC-bus and assuming the converter to be lossless,

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis upper V Subscript d Baseline equals v overbar Subscript a upper N Baseline i overbar Subscript a Baseline plus v overbar Subscript b upper N Baseline i overbar Subscript b Baseline plus v overbar Subscript c upper N Baseline i overbar Subscript c Baseline period(12.34)

Making use of Equation 12.31 into Equation 12.34,

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis upper V Subscript d Baseline equals v overbar Subscript c o m Baseline left-parenthesis i overbar Subscript a Baseline plus i overbar Subscript b Baseline plus i overbar Subscript c Baseline right-parenthesis plus v overbar Subscript a n Baseline i overbar Subscript a Baseline plus v overbar Subscript b n Baseline i overbar Subscript b Baseline plus v overbar Subscript c n Baseline i overbar Subscript c Baseline period(12.35)

By Kirchhoff’s current law at the load neutral, the sum of all three-phase currents within brackets in Equation 12.35 is zero,

i overbar Subscript a Baseline plus i overbar Subscript b Baseline plus i overbar Subscript c Baseline equals 0 period(12.36)

Therefore, from Equation 12.35,

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals StartFraction 1 Over upper V Subscript d Baseline EndFraction left-parenthesis v overbar Subscript a n Baseline i overbar Subscript a Baseline plus v overbar Subscript b n Baseline i overbar Subscript b Baseline plus v overbar Subscript c n Baseline i overbar Subscript c Baseline right-parenthesis period(12.37)

In Equation 12.37, the sum of the products of phase voltages and currents is the three-phase power being supplied to the motor. Substituting for phase voltages and currents in Equation 12.37,

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals StartFraction ModifyingAbove upper V With ˆ Subscript p h Baseline ModifyingAbove upper I With ˆ Over upper V Subscript d Baseline EndFraction StartBinomialOrMatrix sine left-parenthesis omega 1 t right-parenthesis sine left-parenthesis omega 1 t minus phi 1 right-parenthesis plus sine left-parenthesis omega 1 t minus 120 degree right-parenthesis sine left-parenthesis omega 1 t minus phi 1 minus 120 degree right-parenthesis Choose plus sine left-parenthesis omega 1 t minus 240 degree right-parenthesis sine left-parenthesis omega 1 t minus phi 1 minus 240 degree right-parenthesis EndBinomialOrMatrix comma(12.38)

which simplifies to a DC current, as it should, in a three-phase circuit:

ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis equals upper I Subscript d Baseline equals three-halves StartFraction ModifyingAbove upper V With ˆ Subscript p h Baseline ModifyingAbove upper I With ˆ Over upper V Subscript d Baseline EndFraction cosine phi 1 period(12.39)

In three-phase converters, there are two methods of synthesizing sinusoidal output voltages, both of which we will investigate:

  1. Sine-PWM
  2. SV-PWM (Space Vector PWM)

12.6.1 Sine-PWM

In Sine-PWM (similar to converters for DC motor drives and 1-phase UPS), the switching-cycle-averaged output of power poles, v overbar Subscript a upper N, v overbar Subscript b upper N, and v overbar Subscript c upper N, has a constant DC common-mode voltage v overbar Subscript c o m Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction, similar to that in DC motor drives and single-phase UPS v overbar Subscript a n, v overbar Subscript b n, and v overbar Subscript c n can vary sinusoidally as shown in Figure 12.27:

v overbar Subscript a upper N Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction plus v overbar Subscript a n Baseline v overbar Subscript b upper N Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction plus v overbar Subscript b n Baseline v overbar Subscript c upper N Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction plus v overbar Subscript c n Baseline period(12.40)

FIGURE 12.27 Switching-cycle-averaged voltages due to sine-PWM.

In Figure 12.27, using Equation 12.3, the plots of v overbar Subscript a upper N, v overbar Subscript b upper N, and v overbar Subscript c upper N, each divided by upper V Subscript d, are also the plots of d Subscript a, d Subscript b, and d Subscript c within the limits of 0 and 1:

d Subscript a Baseline equals one-half plus StartFraction v overbar Subscript a n Baseline Over upper V Subscript d Baseline EndFraction d Subscript b Baseline equals one-half plus StartFraction v overbar Subscript b n Baseline Over upper V Subscript d Baseline EndFraction d Subscript c Baseline equals one-half plus StartFraction v overbar Subscript c n Baseline Over upper V Subscript d Baseline EndFraction period(12.41)

These power-pole duty ratios define the turns ratio in the ideal transformer representation of Figure 12.25b. As can be seen from Figure 12.27, at the limit, v overbar Subscript a n can become a maximum of StartFraction upper V Subscript d Baseline Over 2 EndFraction and hence the maximum allowable value of the phase-voltage peak is

left-parenthesis ModifyingAbove upper V With ˆ Subscript p h Baseline right-parenthesis Subscript max Baseline equals StartFraction upper V Subscript d Baseline Over 2 EndFraction period(12.42)

Therefore, using the properties of three-phase circuits where the line-line voltage magnitude is StartRoot 3 EndRoot times the phase-voltage magnitude, the maximum amplitude of the line-line voltage in sine-PWM is limited to

left-parenthesis ModifyingAbove upper V With ˆ Subscript upper L upper L Baseline right-parenthesis Subscript max Baseline equals StartRoot 3 EndRoot left-parenthesis ModifyingAbove upper V With ˆ Subscript p h Baseline right-parenthesis Subscript max Baseline equals StartFraction StartRoot 3 EndRoot Over 2 EndFraction upper V Subscript d Baseline asymptotically-equals 0.867 upper V Subscript d Baseline period(12.43)

12.6.1.1 Switching Waveforms in a Three-Phase Inverter with Sine-PWM

In sine-PWM, three sinusoidal control voltages equal the duty ratios, given in Equation 12.41, multiplied by ModifyingAbove upper V With ˆ Subscript t r i. These are compared with a triangular waveform signal to generate the switching signals. These switching waveforms for sine-PWM are shown by an example below.

Example 12.6

In a three-phase converter of Figure 12.25a, a sine-PWM is used. The parameters and the operating conditions are as follows: upper V Subscript d Baseline equals 350 normal upper V, f 1 equals 60 Hz, v overbar Subscript a n Baseline equals 160 cosine omega 1 t volts, and similarly for “b” and “c” phases, and the switching frequency f Subscript s Baseline equals 25 kHz. ModifyingAbove upper V With ˆ Subscript t r i Baseline equals 1 normal upper V. At omega 1 t equals 15 degree, calculate and plot the switching waveforms for one cycle of the switching frequency.

Solution At omega 1 t equals 15 degree, v overbar Subscript a n Baseline equals 154.55 normal upper V, v overbar Subscript b n Baseline equals negative 41.41 normal upper V, and v overbar Subscript c n Baseline equals negative 113.14 normal upper V. Therefore, from Equation 12.40, v overbar Subscript a upper N Baseline equals 329.55 normal upper V, v overbar Subscript b upper N Baseline equals 133.59 normal upper V, and v overbar Subscript c upper N Baseline equals 61.86 normal upper V. From Equation 12.41, the corresponding power-pole duty ratios are d Subscript a Baseline equals 0.942, d Subscript b Baseline equals 0.382, and d Subscript c Baseline equals 0.177. For ModifyingAbove upper V With ˆ Subscript t r i Baseline equals 1 normal upper V, these duty ratios also equal the control voltages in volts. The switching time period upper T Subscript s Baseline equals 50 mu normal s. Based on this, the switching waveforms are shown in Figure 12.28.

FIGURE 12.28 Switching waveforms in Example 12.6.

12.6.1.2 Simulation and Hardware Prototyping

The simulation of a three-phase inverter modulated using sine-PWM is demonstrated by means of an example:

Example 12.7

A three-phase inverter is connected to a balanced three-phase upper R upper L load, upper R equals 8 upper Omega, and upper L equals 1 m normal upper H. The DC voltage upper V Subscript d c Baseline equals 350 normal upper V. The desired output voltage is 208 normal upper V line-line RMS at 60 Hz. Simulate this converter using LTspice.

Solution The simulation file used in this example is available on the accompanying website. The LTspice model is shown in Figure 12.29, and the steady-state waveforms from the simulation of this converter are shown in Figure 12.30.

FIGURE 12.29 LTspice model.

FIGURE 12.30 LTspice simulation results.

The same control algorithm used in Example 12.7 is implemented in Workbench, as shown in Figure 12.31, to generate a balanced three-phase sinusoidal voltage from DC using the Sciamble lab kit.

FIGURE 12.31 Workbench model.

In the hardware, the available DC-bus voltage is upper V Subscript d c Baseline equals 24 normal upper V, and this is used to generate a 14.7 normal upper V RMS, 60 Hz output voltage, as shown in Figure 12.32. The switching frequency is chosen to be f Subscript s Baseline equals 20 k upper H z. The step-by-step procedure for re-creating the above hardware implementation is presented in [2].

FIGURE 12.32 Workbench hardware results: (1)upper I Subscript upper A, (2) upper I Subscript upper B, (3) upper V Subscript upper A upper B, AND (4) upper V Subscript upper B upper C.

12.6.2 Space Vector PWM (SV-PWM)

The use of space vectors has been introduced on a physical basis such that it can be used in teaching the first course dealing with 3-phase AC machines [3]. This approach has numerous benefits compared to conventional methods of understanding AC machines.

The voltage space vector is a compact way to represent all the three-phase voltages desired at any instant by a single variable. This switching-cycle averaged space vector is synthesized using space-vector PWM (SV-PWM), which fully utilizes the available DC-bus voltage and results in the AC output, which can be approximately 15% higher than that possible by using the sine-PWM approach, both in a linear range, where no lower-order harmonics appear.

Sine-PWM is limited to left-parenthesis ModifyingAbove upper V With ˆ Subscript upper L upper L Baseline right-parenthesis Subscript max Baseline asymptotically-equals 0.867 upper V Subscript d Baseline, as given by Equation 12.43, because it synthesizes output voltages on a per-pole basis, which does not take advantage of the three-phase properties. Physically, by considering line-line voltages, it is possible to get left-parenthesis ModifyingAbove upper V With ˆ Subscript upper L upper L Baseline right-parenthesis Subscript max Baseline equals upper V Subscript d in SV-PWM.

12.6.2.1 Definition of Space Vectors

Space vectors can be easily understood by considering a balanced three-phase load, for example, an AC machine, as shown in Figure 12.25, where the a-axis is taken as the reference axis, and the phase axes for the other two phases are 2 pi slash 3 and 4 pi slash 3 radians away in the counterclockwise direction.

The stator space voltage vector at any instant is defined as follows, by multiplying the stator phase voltages at that instant by their respective axes’ orientation and summing them:

ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis t right-parenthesis equals v Subscript a Baseline left-parenthesis t right-parenthesis e Superscript j Baseline 0 Baseline plus v Subscript b Baseline left-parenthesis t right-parenthesis e Superscript j Baseline 2 pi slash 3 Baseline plus v Subscript c Baseline left-parenthesis t right-parenthesis e Superscript j Baseline 4 pi slash 3 Baseline period(12.44)

In terms of the inverter output voltages with respect to the negative DC bus “N” in Figure 12.33, and hypothetically assuming the stator neutral as a reference ground,

v Subscript a Baseline equals v Subscript a upper N Baseline plus v Subscript upper N Baseline semicolon v Subscript b Baseline equals v Subscript b upper N Baseline plus v Subscript upper N Baseline semicolon v Subscript c Baseline equals v Subscript c upper N Baseline plus v Subscript upper N Baseline period(12.45)

FIGURE 12.33 Inverter with a three-phase output.

Substituting Equations 12.45 into Equation 12.44 and recognizing that

e Superscript j Baseline 0 Baseline plus e Superscript j Baseline 2 pi slash 3 Baseline plus e Superscript j Baseline 4 pi slash 3 Baseline equals 0(12.46)

the instantaneous stator voltage space vector can be written in terms of the inverter output voltages as

ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis t right-parenthesis equals v Subscript a upper N Baseline e Superscript j Baseline 0 Baseline plus v Subscript b upper N Baseline e Superscript j Baseline 2 pi slash 3 Baseline plus v Subscript c upper N Baseline e Superscript j Baseline 4 pi slash 3 Baseline period(12.47)

A switch in an inverter pole of Figure 12.33 is in the “up” position if the pole-switching function q equals 1 and in the “down” position if q equals 0. In terms of the switching functions, the instantaneous voltage space vector can be written as

ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis t right-parenthesis equals upper V Subscript d Baseline left-parenthesis q Subscript a Baseline e Superscript j Baseline 0 Baseline plus q Subscript b Baseline e Superscript j Baseline 2 pi slash 3 Baseline plus q Subscript c Baseline e Superscript j Baseline 4 pi slash 3 Baseline right-parenthesis period(12.48)

With three poles, eight switch-status combinations are possible. In Equation 12.48, the instantaneous stator voltage vector ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis t right-parenthesis can take on one of the following seven distinct instantaneous values where in a digital representation, phase “a” represents the least significant digit and phase “c” the most significant digit (for example, the resulting voltage vector due to the switch-status combination ModifyingBelow 011 With presentation form for vertical right-brace Underscript left-parenthesis equals 3 right-parenthesis Endscripts is represented as ModifyingAbove v With right-arrow Subscript 3):

StartLayout 1st Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 000 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 0 Baseline equals 0 EndLayout 2nd Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 001 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 1 Baseline equals upper V Subscript d Baseline e Superscript j Baseline 0 Baseline EndLayout 3rd Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 010 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 2 Baseline equals upper V Subscript d Baseline e Superscript j Baseline 2 pi slash 3 Baseline EndLayout 4th Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 011 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 3 Baseline equals upper V Subscript d Baseline e Superscript j pi slash 3 Baseline EndLayout 5th Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 100 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 4 Baseline equals upper V Subscript d Baseline e Superscript j Baseline 4 pi slash 3 Baseline EndLayout 6th Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 101 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 5 Baseline equals upper V Subscript d Baseline e Superscript j Baseline 5 pi slash 3 Baseline EndLayout 7th Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 110 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 6 Baseline equals upper V Subscript d Baseline e Superscript j pi Baseline EndLayout 8th Row StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis 111 right-parenthesis equals ModifyingAbove v With right-arrow Subscript 7 Baseline equals 0 EndLayout period EndLayout(12.49)

In Equation 12.49, ModifyingAbove v With right-arrow Subscript 0 and ModifyingAbove v With right-arrow Subscript 7 are the zero vectors because of their zero value. The resulting instantaneous stator voltage vectors, which we will call the “basic vectors,” are plotted in Figure 12.34. The basic vectors form six sectors, as shown in Figure 12.34.

FIGURE 12.34 Basic voltage vectors (ModifyingAbove v With right-arrow Subscript 0 and ModifyingAbove v With right-arrow Subscript 7 are not shown).

It should be noted that the basic voltage vectors are the only true instantaneous voltages. However, the machine phase voltages that we are aiming to synthesize, for example, in Equation 12.44, are the switching-cycle-averaged voltages, and therefore, to be rigorous, they should be written as ModifyingAbove v With bar Subscript a Baseline left-parenthesis t right-parenthesis, and so on . Therefore, the switching-cycle-averaged space vector in Equation 12.44 will have to be written as ModifyingAbove Above ModifyingAbove v With bar With right-arrow Subscript s Baseline left-parenthesis t right-parenthesis. This is not done in the analysis presented here simply to avoid complicating the symbols, but the intent should be clearly understood. Reiterating, as shown in Figure 12.34, the basic vectors are the truly instantaneous space vectors, which by time-weighted averaging called SV-PWM and, as discussed in the next section, allow us to synthesize the space vector ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis t right-parenthesis of Figure 12.34, which is switching-cycle-averaged.

12.6.2.2 SV-PWM

The objective of the PWM control of the inverter switches is to synthesize the desired reference stator voltage space vector in an optimum manner with the following objectives:

  • A constant switching frequency f Subscript s;
  • Smallest instantaneous deviation from its reference value;
  • Maximum utilization of the available DC-bus voltages;
  • Lowest ripple in the motor current;
  • Minimum switching loss in the inverter.

The above conditions are generally met if the average voltage vector is synthesized by means of the two instantaneous basic nonzero voltage vectors that form the sector (in which the average voltage vector to be synthesized lies) and both the zero-voltage vectors, such that each transition causes the change of only one switch status to minimize the inverter switching loss.

In the following analysis, we will focus on the average voltage vector in sector 1 with the aim of generalizing the discussion to all sectors. To synthesize an average voltage vector ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis equals ModifyingAbove upper V With ˆ Subscript s Baseline e Superscript j theta Super Subscript s Superscript Baseline right-parenthesis over a time period upper T Subscript s, as shown in Figure 12.35, the adjoining basic vectors ModifyingAbove v With right-arrow Subscript 1 and ModifyingAbove v With right-arrow Subscript 3 are applied for intervals x upper T Subscript s and y upper T Subscript s, respectively, and the zero vectors ModifyingAbove v With right-arrow Subscript 0 and ModifyingAbove v With right-arrow Subscript 7 are applied for a total duration of z upper T Subscript s.

FIGURE 12.35 Voltage vector in sector 1.

In terms of the basic voltage vectors, the average voltage vector can be expressed as

ModifyingAbove v With right-arrow Subscript s Baseline equals StartFraction 1 Over upper T Subscript s Baseline EndFraction left-bracket x upper T Subscript s Baseline ModifyingAbove v With right-arrow Subscript 1 Baseline plus y upper T Subscript s Baseline ModifyingAbove v With right-arrow Subscript 3 Baseline plus z upper T Subscript s Baseline dot 0 right-bracket comma(12.50)

or

ModifyingAbove v With right-arrow Subscript s Baseline equals x ModifyingAbove v With right-arrow Subscript 1 Baseline plus y ModifyingAbove v With right-arrow Subscript 3 Baseline comma(12.51)

where

x plus y plus z equals 1 period(12.52)

In Equation 12.51, expressing voltage vectors in terms of their amplitude and phase angles results in

ModifyingAbove upper V With ˆ Subscript s Baseline e Superscript j theta Super Subscript s Superscript Baseline equals x upper V Subscript d Baseline e Superscript j Baseline 0 Baseline plus y upper V Subscript d Baseline e Superscript j pi slash 3 Baseline period(12.53)

By equating real and imaginary terms on both sides of Equation 12.53, we can solve for x and y (in terms of the given values of ModifyingAbove upper V With ˆ Subscript s, theta Subscript s, and upper V Subscript d) to synthesize the desired average space vector in sector 1.

Having determined the durations for the adjoining basic vectors and the two zero vectors, the next task is to relate the above discussion to the actual poles (a, b, and c). Note in Figure 12.34 that in any sector, the adjoining basic vectors differ in one position. For example, in sector 1 with the basic vectors ModifyingAbove v With right-arrow Subscript 1 Baseline left-parenthesis 001 right-parenthesis and ModifyingAbove v With right-arrow Subscript 3 Baseline left-parenthesis 011 right-parenthesis, only the pole b differs in the switch position. For sector 1, the switching pattern in Figure 12.36 shows that pole a is in “up” position during the sum of x upper T Subscript s, y upper T Subscript s, and z 7 upper T Subscript s intervals and hence for the longest interval of the three poles. Next in the length of duration in the “up” position is pole b for the sum of y upper T Subscript s and z 7 upper T Subscript s intervals. The smallest in the length of duration is pole c for only the z 7 upper T Subscript s interval. Each transition requires a change in switch state in only one of the poles, as shown in Figure 12.36. Similar switching patterns for the three poles can be generated for any other sector.

FIGURE 12.36 Waveforms in sector 1 (z equals z 0 plus z 7).

12.6.2.3 Limit on the Amplitude ModifyingAbove upper V With caret Subscript s of the Stator Voltage Space Vector ModifyingAbove v With right-arrow Subscript s

First, we will establish the absolute limit on the amplitude ModifyingAbove upper V With ˆ Subscript s of the average stator voltage space vector at various angles. The limit on the amplitude equals upper V Subscript d (the DC-bus voltage) if the average voltage vector lies along a nonzero basic voltage vector. In between the basic vectors, the limit on the average voltage vector amplitude is that its tip can lie on the straight lines shown in Figure 12.37, forming a hexagon.

FIGURE 12.37 Limit on amplitude ModifyingAbove upper V With ˆ Subscript s.

However, the maximum amplitude of the output voltage ModifyingAbove v With right-arrow Subscript s should be limited to the circle within the hexagon in Figure 12.37 to prevent distortion in the resulting currents. This can be easily concluded from the fact that in a balanced sinusoidal steady state, the voltage vector ModifyingAbove v With right-arrow Subscript s rotates at the synchronous speed omega Subscript s y n Baseline left-parenthesis equals 2 pi f right-parenthesis, with its constant amplitude, where f is the frequency of the phase voltages. At its maximum amplitude,

ModifyingAbove v With right-arrow Subscript s comma max Baseline left-parenthesis t right-parenthesis equals ModifyingAbove upper V With ˆ Subscript s comma max Baseline e Superscript j omega Super Subscript s y n Superscript t Baseline period(12.54)

Therefore, the maximum value that ModifyingAbove upper V With ˆ Subscript s can attain is

ModifyingAbove upper V With ˆ Subscript s comma max Baseline equals upper V Subscript d Baseline cosine left-parenthesis StartFraction 60 degree Over 2 EndFraction right-parenthesis equals StartFraction StartRoot 3 EndRoot Over 2 EndFraction upper V Subscript d Baseline period(12.55)

In a balanced steady state, the peak of the phase voltages is 2 slash 3 times the amplitude of the space vector. Therefore, from Equation 12.55, the corresponding limits on the phase voltage and the line-line voltages are as follows:

ModifyingAbove upper V With ˆ Subscript p h a s e comma max Baseline equals two-thirds ModifyingAbove upper V With ˆ Subscript s comma max Baseline equals StartFraction upper V Subscript d Baseline Over StartRoot 3 EndRoot EndFraction comma(12.56)

and

upper V Subscript upper L upper L comma max Baseline left-parenthesis rms right-parenthesis equals StartRoot 3 EndRoot StartFraction ModifyingAbove upper V With ˆ Subscript p h a s e comma max Baseline Over StartRoot 2 EndRoot EndFraction equals StartFraction upper V Subscript d Baseline Over StartRoot 2 EndRoot EndFraction equals 0.707 upper V Subscript d Baseline left-parenthesis SV hyphen PWM right-parenthesis period(12.57)

The sine-PWM in the linear range, as discussed before, results in a maximum voltage

StartLayout 1st Row 1st Column upper V Subscript upper L upper L comma max Baseline left-parenthesis rms right-parenthesis equals StartFraction StartRoot 3 EndRoot Over 2 StartRoot 2 EndRoot EndFraction upper V Subscript d Baseline equals 0.612 upper V Subscript d Baseline 2nd Column left-parenthesis Sine hyphen PWM right-parenthesis EndLayout period(12.58)

A comparison of Equations 12.57 and 12.58 shows that the SV-PWM discussed in this chapter better utilizes the DC-bus voltage and results in a higher limit on the available output voltage by a factor of left-parenthesis 2 slash StartRoot 3 EndRoot right-parenthesis, or by approximately 15% higher, compared to the sine-PWM.

Example 12.8

Similar to that in Example 12.6, consider the three-phase converter of Figure 12.21a, where upper V Subscript d Baseline equals 350 normal upper V and v overbar Subscript a n Baseline equals 160 cosine omega 1 t volts, and so forth. Obtain the duty ratios d Subscript a, using SV-PWM at omega 1 t equals 15 degree.

Solution The voltage space vector at omega 1 t equals 15 degree is obtained using Equation 12.47 :StartLayout 1st Row ModifyingAbove v With right-arrow Subscript s Baseline left-parenthesis t right-parenthesis equals 160 cosine left-parenthesis 15 degree right-parenthesis e Superscript j Baseline 0 Baseline plus 160 cosine left-parenthesis 15 degree negative 120 degree right-parenthesis e Superscript j Baseline 2 pi slash 3 Baseline plus 160 cosine left-parenthesis 15 degree negative 240 degree right-parenthesis e Superscript j Baseline 4 pi slash 3 Baseline 2nd Row equals 240 angle 15 degree EndLayout

This is in sector 1 of the voltage vectors shown in Figure 12.34. In sector 1, The two nonzero vectors are ModifyingAbove v With right-arrow Subscript 1 Baseline left-parenthesis 001 right-parenthesis and ModifyingAbove v With right-arrow Subscript 2 Baseline left-parenthesis 011 right-parenthesis. The ratio of the switching time period each of these vectors is applied is determined using Equation 12.53:

StartLayout 1st Row 240 e Superscript j Baseline 15 pi slash 180 Baseline equals 350 left-parenthesis x e Superscript j Baseline 0 Baseline plus y e Superscript j pi slash 3 Baseline right-parenthesis 2nd Row right double arrow 0.6857 left-parenthesis 0.9659 plus j Baseline 0.2588 right-parenthesis equals left-parenthesis x plus 0.5 y right-parenthesis plus j Baseline 0.866 y period EndLayout

Solving the above equation gives x equals 0.5599 and y equals 0.2049. The two zero vectors ModifyingAbove v With right-arrow Subscript 0 Baseline left-parenthesis 000 right-parenthesis and ModifyingAbove v With right-arrow Subscript 7 Baseline left-parenthesis 111 right-parenthesis are shared equally in the remaining period:

z 0 equals z 1 equals left-parenthesis 1 minus x minus y right-parenthesis slash 2 equals 0.1176

Now the duty cycle of each phase can be obtained by summing up the duty cycles of each vector whose phase’s switch is in the “up” position during that phase: d Subscript a Baseline equals x plus y plus z 7 equals 0.8824, d Subscript b Baseline equals y plus z 7 equals 0.3225, and d Subscript c Baseline equals z 7 equals 0.1176.

12.6.2.4 Simulation and Hardware Prototyping

The simulation of a three-phase inverter modulated using SV-PWM is demonstrated by means of an example:

Example 12.9

A three-phase inverter is connected to a balanced three-phase upper R upper L load, where upper R equals 8 upper Omega and upper L equals 1 m normal upper H. The DC voltage upper V Subscript d c Baseline equals 350 normal upper V. The desired output voltage is 208 normal upper V line-line RMS at 60 Hz. Simulate this converter using LTspice.

Solution The simulation file used in this example is available on the accompanying website. The LTspice model is shown in Figure 12.38, and the steady-state waveforms from the simulation of this converter are shown in Figure 12.39.

FIGURE 12.38 LTspice model.

FIGURE 12.39 LTspice simulation results.

The same control algorithm used in Example 12.9 is implemented in Workbench, as shown in Figure 12.40, to generate a balanced three-phase sinusoidal voltage from DC using the Sciamble lab kit.

FIGURE 12.40 Workbench model.

In the hardware, the available DC-bus voltage is upper V Subscript d c Baseline equals 40 normal upper V, and this is used to generate a 17 normal upper V RMS, 60 Hz output voltage, as shown in Figure 12.41. The switching frequency is chosen to be f Subscript s Baseline equals 20 k upper H z. The step-by-step procedure for re-creating the above hardware implementation is presented in [4].

FIGURE 12.41 Workbench hardware results: (1)upper I Subscript upper A, (2) upper I Subscript upper B, (3) upper V Subscript upper A upper B, AND (4) upper V Subscript upper B upper C.

12.6.3 Over-Modulation and Square-Wave (Six-step) Mode of Operation [5]

So far, in using sine-PWM and SV-PWM, it is assumed that the control voltage peak is kept equal to or less than the triangular waveform peak ModifyingAbove upper V With ˆ Subscript t r i. This results in a linear range where the output phase voltages, ignoring the common-mode offset voltages that do not appear across the load, are linearly related to the control voltages. Therefore, in terms of functionality, a PWM converter is similar to a linear amplifier in the linear modulation. In addition to this linearity, the harmonics in the switched output waveform are, as shown in Figure 12.8b, at around the multiples of the switching frequency. That is, the low-order harmonics that are multiples of the low-frequency f 1 (the fundamental frequency) do not appear in the output.

However, in applications such as motor drives at higher than rated speed, it may be advantageous to get as high a voltage as possible at the fundamental frequency f 1, even if the output contains harmonics that are low-order multiples of f 1. This requires the control voltages to exceed the triangular-waveform peak by over-modulation. The output voltage-switching waveform, as a consequence, contains low-order harmonics that can be obtained by Fourier analysis. At the limit, in each switching power-pole, the switch is in “up” position for one-half the time period and “down” for the other half, as shown in Figure 12.42.

FIGURE 12.42 Square-wave (six-step) waveforms.

The output waveforms of the three poles are displaced by 2 pi slash 3 radians with respect to each other. The resulting output waveforms are square waves, and such an operation is called square-wave or six-step mode of operation. For a given DC-bus voltage upper V Subscript d, this mode of operation yields the highest possible output voltages at frequency f 1, where by Fourier analysis, at the fundamental frequency,

StartLayout 1st Row 1st Column ModifyingAbove upper V With ˆ Subscript p h 1 Baseline equals StartFraction 4 Over pi EndFraction left-parenthesis StartFraction upper V Subscript d Baseline Over 2 EndFraction right-parenthesis equals 0.637 upper V Subscript d Baseline 2nd Column and ModifyingAbove upper V With ˆ Subscript upper L upper L 1 Baseline equals StartRoot 3 EndRoot ModifyingAbove upper V With ˆ Subscript p h 1 Baseline equals StartFraction 2 StartRoot 3 EndRoot Over pi EndFraction upper V Subscript d Baseline asymptotically-equals 1.1 upper V Subscript d Baseline EndLayout comma(12.59)

which shows that it is possible to get the fundamental-frequency line-line voltage peak greater than upper V Subscript d, although at the expense of the low-order harmonic voltages,

StartLayout 1st Row 1st Column ModifyingAbove upper V With ˆ Subscript upper L upper L Sub Subscript h Baseline equals StartFraction ModifyingAbove upper V With ˆ Subscript upper L upper L 1 Baseline Over h EndFraction equals StartFraction 1.1 Over h EndFraction upper V Subscript d Baseline 2nd Column where h equals 6 n plus-or-minus 1 semicolon n equals 1 comma 2 comma 3 comma ellipsis period EndLayout(12.60)

12.7 MULTILEVEL INVERTERS

In high-power and high-voltage applications, it is desirable to operate with high values of voltages in order to keep the associated currents to manageable levels. This requires the DC-bus voltage upper V Subscript d to be large so that it exceeds the voltage ratings of the transistors (of course, a safety margin has to be used), as shown in Figure 12.3a of a switching power-pole. One option in such a case is to use multiple transistors in series in order to yield, effectively, each transistor in Figure 12.3a. This is done in practice; however, great care must be taken to ensure that all the transistors in series switch in unison so that they share voltages equally.

Another option that has been used sometimes is to have a three-level arrangement, as shown in Figure 12.43, where a midpoint “o” is established by two series-connected equal capacitors as shown with equal DC voltages upper V Subscript d Baseline slash 2 [4].

FIGURE 12.43 Three-level inverters.

We will consider the switching power-pole for phase a. By turning switches upper S Subscript a Baseline 2 Superscript plus and upper S Subscript a Baseline 2 Superscript minus on, with respect to the midpoint, the switching-pole output voltage v Subscript a o Baseline equals 0 regardless of the current direction. Turning upper S Subscript a Baseline 1 Superscript plus and upper S Subscript a Baseline 2 Superscript plus on results in v Subscript a o Baseline equals upper V Subscript d Baseline slash 2. Similarly, turning upper S Subscript a Baseline 1 Superscript minus and upper S Subscript a Baseline 2 Superscript minus on results in v Subscript a o Baseline equals minus upper V Subscript d Baseline slash 2. There are two major advantages of the three-level inverter: (1) transistors in Figure 12.43 need to block only one-half the DC-bus voltage, that is, upper V Subscript d Baseline slash 2, without the need to connect two transistors in series and without the associated problem of ensuring equal voltage sharing mentioned earlier, and (2) three levels (upper V Subscript d Baseline slash 2, 0,minus upper V Subscript d slash 2) result in less switching-frequency ripple in the output for the same switching frequency, as compared to two-level inverters discussed earlier. One of the drawbacks of these inverters is the need to ensure that the midpoint remains at half the DC bus voltage.

Multilevel inverters with more than three levels have been reported in the literature with various advantages and challenges [6, 7]. A detailed discussion of this topic is presented in [8].

12.8 CONVERTERS FOR BIDIRECTIONAL POWER FLOW

In many applications, the power flow through the voltage-link structure of Figure 12.1 is bidirectional. For example, in motor drives, normally, power flows from the utility to the motor, and while slowing down, the energy stored in the inertia of machine-load combination can be recovered by operating the machine as a generator and feeding power back into the utility grid. This can be accomplished by using three-phase converters, discussed in section 12.6, at both ends, as shown in Figure 12.44a, recognizing that the power flow through these converters is bidirectional.

FIGURE 12.44 Voltage-link structure for bidirectional power flow.

In the normal mode, the converter at the utility-end operates as a rectifier and the converter at the machine-end as an inverter. The roles of these two are opposite when the power flows in the reverse direction during energy recovery. A similar arrangement can be used in connecting two AC systems by means of a HVDC transmission line.

The switching-cycle-averaged representation of these converters by means of ideal transformers is shown in Figure 12.44b. In this simplified representation, where losses are ignored, one side is represented by a source v Subscript s a, and so forth, in series with the internal system inductance upper L Subscript s. The other side, for example, an AC machine, is represented by its steady-state equivalent circuit, the equivalent machine inductance upper L Subscript e q in series with the back-emf e Subscript upper A, and so on. Under balanced three-phase operation at both ends, the role of each converter can be analyzed by means of the per-phase equivalent circuits shown in Figure 12.44c. In these per-phase equivalent circuits, the fundamental-frequency voltages produced at the AC side by the two converters are v Subscript a Baseline 1 and v Subscript upper A n Baseline 1, and the AC-side currents at the two sides can be expressed in the phasor form as

upper I overbar Subscript a Baseline 1 Baseline equals StartFraction upper V overbar Subscript s a Baseline minus upper V overbar Subscript a Baseline 1 Baseline Over j omega Subscript s Baseline upper L Subscript s Baseline EndFraction(12.61)
upper I overbar Subscript upper A Baseline 1 Baseline equals StartFraction upper V overbar Subscript upper A n Baseline 1 Baseline minus upper E overbar Subscript upper A Baseline Over j omega 1 upper L Subscript e q Baseline EndFraction comma(12.62)

where the phasors in Equation 12.61 represent voltages and current at the frequency omega Subscript s of side 1 and the phasors in Equation 12.62 at the fundamental-frequency omega 1 synthesized at side 2.

In Figure 12.44a, for a given utility voltage, it is possible to control the current drawn from side 1 by controlling the voltage synthesized by the side 1 converter in magnitude and phase. In these circuits, if the losses are ignored, the switching-cycle-averaged power drawn from side 1 equals the power supplied to side 2. However, the reactive power at the side 1 converter can be controlled independently of the reactive power at the side 2 converter.

12.9 MATRIX CONVERTERS (DIRECT LINK SYSTEM)

To review once again, power electronics systems are categorized as voltage-link systems described so far, where a capacitor is used in parallel with two converters as an energy storage element, and current-link systems, described in Chapters 13 and 14, used in very high-power applications, where an inductor is used in series with the two converters for energy storage. There is another structure called the matrix converters, which provides a direct link between the input and the output without any intermediate energy storage element. There is a great deal of research interest at present in these converters because they avoid the intermediate energy storage element.

Such a system for a three-phase to three-phase conversion is shown in Figure 12.45, where there is a bidirectional switch from each input port to each output port. Such a bidirectional switch must be capable of blocking voltages of either polarity and conduct current in either direction. Such a bidirectional switch can be realized, for example, by two IGBTs and two diodes, as connected in Figure 12.45. When the two transistors are gated on, the current can flow in either direction, effectively representing the closed position of the bidirectional switch. When both transistors are gated off, current cannot flow in either direction, effectively representing the closed position of the bidirectional switch. A detailed discussion of this topic is presented in [8].

FIGURE 12.45 Matrix converter.

REFERENCES

  1. 1. “Single-Phase Inverter Lab Manual.” https://sciamble.com/resources/pe-drives-lab/basic-pe/single-phase-inverter.
  2. 2. “Sine PWM Lab Manual.” https://sciamble.com/resources/pe-drives-lab/basic-pe/sine-pwm.
  3. 3. N. Mohan and S. Raju, Analysis and Control of Electric Drives: Simulations and Laboratory Implementation (New York: John Wiley & Sons, 2020).
  4. 4. “Space Vector PWM Lab Manual.” https://sciamble.com/resources/pe-drives-lab/basic-pe/svpwm.
  5. 5. N. Mohan, T.M. Undeland, and W.P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Edition (New York: John Wiley & Sons, 2003).
  6. 6. J. Rodríguez, et al., “Multilevel Inverters: A Survey of Topologies, Controls, and Applications,” IEEE Transactions on Industrial Electronics 49, no. 4 (August 2002): 724–738.
  7. 7. V.T. Somasekhar, K. Gopakumar, M.R. Baiju, K.K. Mohapatra, and L. Umanand, “A Multilevel Inverter System for an Induction Motor with Open-End Windings,” IEEE Transactions on Industrial Electronics 52, no. 3 (June 2005), 824–836.
  8. 8. N. Mohan, W. Robins, T. Undeland, and S. Raju, Power Electronics for Grid-Integration of Renewables: Analysis, Simulations and Hardware Lab (New York: John Wiley & Sons, 2023).

PROBLEMS

Switching Power-Pole

  • 12.1 In a switch-mode converter pole a, upper V Subscript d Baseline equals 175 normal upper V, ModifyingAbove upper V With ˆ Subscript t r i Baseline equals 5 normal upper V, and f Subscript s Baseline equals 20 kHz. Calculate the values of the control signal v Subscript c n t r l comma a and the pole duty ratio d Subscript a during which the switch is in its top position, for the following values of the average output voltage: v overbar Subscript a upper N Baseline equals 125 normal upper V and v overbar Subscript a upper N Baseline equals 50 normal upper V.
  • 12.2 In a converter pole, including the ripple in the i Subscript a Baseline left-parenthesis t right-parenthesis waveform, show that the relationship between the currents on both sides of the switching-cycle-averaged power pole is similar to that in an ideal transformer.

DC-MOTOR DRIVES

  • 12.3 A switch-mode DC-DC converter uses a PWM-controller IC that has a triangular waveform signal at 25 kHz with ModifyingAbove upper V With ˆ Subscript t r i = 1.5 V. If the input DC source voltage upper V Subscript d Baseline equals 150 normal upper V, calculate the gain k Subscript upper P upper W upper M in Equation 12.19 of this switch-mode amplifier.
  • 12.4 In a switch-mode DC-DC converter, v Subscript c n t r l Baseline slash ModifyingAbove upper V With ˆ Subscript t r i Baseline equals 0.75 with a switching frequency f Subscript s Baseline equals 20 kHz and upper V Subscript d Baseline equals 150 normal upper V. Calculate and plot the ripple in the output voltage v Subscript o Baseline left-parenthesis t right-parenthesis.
  • 12.5 A switch-mode DC-DC converter is operating at a switching frequency of 20 kHz, and upper V Subscript d = 150 V. The average current being drawn by the DC motor is 8.0 A. In the equivalent circuit of the DC motor, upper E Subscript a Baseline equals 100 normal upper V, upper R Subscript a Baseline equals 0.25 upper Omega, and upper L Subscript a Baseline equals 4 mH. (a) Plot the output current and calculate the peak-to-peak ripple, and (b) plot the current on the DC side of the converter.
  • 12.6 In Problem 12.5, the motor goes into regenerative braking mode. The average current being supplied by the motor to the converter during braking is 7.0 A. Plot the voltage and current waveforms on both sides of this converter at that instant. Calculate the average power flow into the converter.
  • 12.7 In Problem 12.5, calculate i overbar Subscript d a, i overbar Subscript d b, and ModifyingAbove i With bar Subscript d Baseline left-parenthesis equals upper I Subscript d Baseline right-parenthesis.
  • 12.8 Repeat Problem 12.5 if the motor is rotating in the reverse direction, with the same current draw and the same induced emf upper E Subscript a value of the opposite polarity.
  • 12.9 Repeat Problem 12.8 if the motor is braking while it has been rotating in the reverse direction. It supplies the same current and produces the same induced emf upper E Subscript a value of the opposite polarity.
  • 12.10 Repeat Problem 12.5 if a bipolar voltage switching is used in the DC-DC converter. In such a switching scheme, the two bi-positional switches are operated in such a manner that when switch a is in the top position, switch b is in its bottom position, and vice versa. The switching signal for pole a is derived by comparing the control voltage (as in Problem 12.5) with the triangular waveform.

SINGLE-PHASE INVERTERS

  • 12.11 In a 1-phase UPS, upper V Subscript d Baseline equals 350 normal upper V, ModifyingAbove v With bar Subscript o Baseline left-parenthesis t right-parenthesis equals 170 sine left-parenthesis 2 pi times 60 t right-parenthesis normal upper V, and ModifyingAbove i With bar Subscript o Baseline left-parenthesis t right-parenthesis equals 10 sine left-parenthesis 2 pi times 60 t minus 30 degree right-parenthesis upper A. Calculate and plot d Subscript a Baseline left-parenthesis t right-parenthesis, d Subscript b Baseline left-parenthesis t right-parenthesis, ModifyingAbove v With bar Subscript a upper N Baseline left-parenthesis t right-parenthesis, ModifyingAbove v With bar Subscript b upper N Baseline left-parenthesis t right-parenthesis, upper I Subscript d, i Subscript d Baseline 2 Baseline left-parenthesis t right-parenthesis, and ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis. Switching frequency f Subscript s Baseline equals 20 kHz.
  • 12.12 In Problem 12.11, calculate q Subscript a Baseline left-parenthesis t right-parenthesis and q Subscript b Baseline left-parenthesis t right-parenthesis at omega t equals 90 degree.

THREE-PHASE INVERTERS

  • 12.13 Plot d Subscript a Baseline left-parenthesis t right-parenthesis if the output voltage of the converter pole a is ModifyingAbove v With bar Subscript a upper N Baseline left-parenthesis t right-parenthesis equals StartFraction upper V Subscript d Baseline Over 2 EndFraction plus 0.85 StartFraction upper V Subscript d Baseline Over 2 EndFraction sine left-parenthesis omega 1 t right-parenthesis, where omega 1 equals 2 pi times 60 rad slash normal s.
  • 12.14 In a three-phase DC-AC inverter, upper V Subscript d Baseline equals 350 normal upper V, ModifyingAbove upper V With ˆ Subscript t r i Baseline equals 1 normal upper V, the maximum value of the control voltage reaches 0.8 normal upper V, and f 1 equals 45 Hz. Calculate and plot (a) the duty ratios d Subscript a Baseline left-parenthesis t right-parenthesis, d Subscript b Baseline left-parenthesis t right-parenthesis, d Subscript c Baseline left-parenthesis t right-parenthesis, (b) the pole output voltages ModifyingAbove v With bar Subscript a upper N Baseline left-parenthesis t right-parenthesis, ModifyingAbove v With bar Subscript b upper N Baseline left-parenthesis t right-parenthesis, ModifyingAbove v With bar Subscript c upper N Baseline left-parenthesis t right-parenthesis, and (c) the phase voltages ModifyingAbove v With bar Subscript a n Baseline left-parenthesis t right-parenthesis, ModifyingAbove v With bar Subscript b n Baseline left-parenthesis t right-parenthesis, and ModifyingAbove v With bar Subscript c n Baseline left-parenthesis t right-parenthesis.
  • 12.15 In a balanced three-phase DC-AC converter, the phase a average output voltage is ModifyingAbove v With bar Subscript a n Baseline left-parenthesis t right-parenthesis equals 112.5 sine left-parenthesis omega 1 t right-parenthesis, where upper V Subscript d Baseline equals 300 normal upper V and omega 1 equals 2 pi times 45 rad slash normal s. The inductance upper L in each phase is 5 mH. The AC motor internal voltage in phase A can be represented as e Subscript a Baseline left-parenthesis t right-parenthesis equals 106.14 sine left-parenthesis omega 1 t minus 6.6 degree right-parenthesis normal upper V. (a) Calculate and plot d Subscript a Baseline left-parenthesis t right-parenthesis, d Subscript b Baseline left-parenthesis t right-parenthesis, and d Subscript c Baseline left-parenthesis t right-parenthesis, and (b) sketch ModifyingAbove i With bar Subscript a Baseline left-parenthesis t right-parenthesis and ModifyingAbove i With bar Subscript d a Baseline left-parenthesis t right-parenthesis.
  • 12.16 In Problem 12.15, calculate and plot ModifyingAbove i With bar Subscript d Baseline left-parenthesis t right-parenthesis, which is the average DC current drawn from the DC side.
  • 12.17 In a converter upper V Subscript d Baseline equals 700 normal upper V. To synthesize an average stator voltage vector ModifyingAbove v With right-arrow Subscript s Superscript a Baseline equals 563.38 e Superscript j Baseline 0.44 Baseline normal upper V, calculate x, y, and z.
  • 12.18 Given that ModifyingAbove v With right-arrow Subscript s Superscript a Baseline equals 563.38 e Superscript j Baseline 0.44 Baseline normal upper V, calculate the phase voltage components.

SIMULATION PROBLEMS

  • 12.19 Simulate a single-phase inverter where upper V Subscript d Baseline equals 300 normal upper V, the output voltage v 0 is 150 V (RMS) at the fundamental frequency, which is 45 Hz. The output current i 0 has an RMS value of 10 A at a lagging power factor of 0.866. The switching frequency is f Subscript s Baseline equals 1 kHz. The output load can be simulated by a back-emf in series with a resistance of 2.0 normal upper Omega and an inductance of 10.0 mH.
    • Obtain v 0 and i 0 waveforms.
    • By Fourier analysis, obtain v 01, and plot the v 01 and i 0 waveforms.
    • Obtain the i Subscript d waveform.
    • By Fourier analysis, obtain upper I Subscript d and i Subscript d Baseline 2, and plot them.
    • Obtain the RMS value of the high-frequency ripple current in i Subscript d.
  • 12.20 In the single-phase inverter of Problem 12.17, represent each of the two poles by their average model.
    • Obtain the v overbar Subscript 0 and i overbar Subscript 0 waveforms.
    • Obtain the i overbar Subscript d waveform.
    • Obtain upper I Subscript d and i Subscript d Baseline 2, and plot them.
  • 12.21 Simulate a three-phase inverter where upper V Subscript d Baseline equals 350 normal upper V, the output voltage upper V Subscript upper L upper L is 175 V(RMS) at the fundamental frequency, which is 45 Hz. The output current has an RMS value of 10 A at a lagging power factor of 0.866. The switching frequency is f Subscript s Baseline equals 1 kHz. The per-phase output load can be simulated by a back-emf in series with a resistance of 2.0 normal upper Omega and an inductance of 10.0 mH.
    • Obtain the waveforms for v Subscript a n (with respect to load-neutral), i Subscript a and i Subscript d.
    • Obtain v Subscript a n Baseline 1 by means of Fourier analysis of the v Subscript a n waveform.
    • Using the results of part (b), obtain the ripple component v Subscript r i p p l e waveform in the output voltage.
  • 12.22 In the three-phase inverter of Problem 12.19, represent each of the three poles by their average model.
    • Observe the waveforms for v overbar Subscript a n, i overbar Subscript a, and i overbar Subscript d.
    • Append the output current waveforms of the switching model of Problem 12.19.
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