8
SWITCH-MODE DC POWER SUPPLIES

8.1 APPLICATIONS OF SWITCH-MODE DC POWER SUPPLIES

Switch-mode DC power supplies represent an important power electronics application area with a worldwide market of several billion dollars per year. Many of these power supplies incorporate transformer isolation for reasons that are discussed below. Within these power supplies, transformer-isolated DC-DC converters are derived from non-isolated DC-DC converter topologies already discussed in Chapter 3. For short, we will refer to transformer-isolated switch-mode DC power supplies as SMPS (switched-mode power supply, sometimes called switcher), whose block diagram is shown in Figure 8.1. As shown in Figure 8.1, these supplies encompass the rectification of the utility supply, and the voltage upper V Subscript i n across a large filter capacitor is the input to the transformer-isolated DC-DC converter, which is the focus of discussion in this chapter. Internally, the transformer operates at very high frequencies, typically upwards of a few hundred kHz, thus resulting in small size and weight, as discussed in the next chapter.

FIGURE 8.1 Block diagram of switch-mode DC power supplies.

8.2 NEED FOR ELECTRICAL ISOLATION

Electrical isolation by means of transformers is needed in switch-mode DC power supplies for three reasons:

  1. Safety: It is necessary for the low-voltage DC output to be isolated from the utility supply to avoid the shock hazard.
  2. Different reference potentials: The DC supply may have to operate at a different potential, for example, the DC supply to the gate drive for the upper MOSFET in the power pole is referenced to its source.
  3. Voltage matching: If the DC-DC conversion is large, then to avoid requiring large voltage and current ratings of semiconductor devices, it may be economical and operationally more suitable to use an electrical transformer for conversion of voltage levels.

8.3 CLASSIFICATION OF TRANSFORMER-ISOLATED DC-DC CONVERTERS

In the block diagram of Figure 8.1, there are the following three categories of transformer-isolated DC-DC converters, all of which are discussed in detail in this chapter:

  1. Flyback converters derived from buck-boost DC-DC converters
  2. Forward converter derived from buck DC-DC converters
  3. Full-bridge and half-bridge converters derived from buck DC-DC converters

8.4 FLYBACK CONVERTERS

Flyback converters are very commonly used in applications at low power levels below 50 W. These are derived from the buck-boost converter redrawn in Figure 8.2a, where the inductor is drawn descriptively on a low permeability core.

FIGURE 8.2 Buck-boost and the flyback converters.

The flyback converter in Figure 8.2b consists of two mutually coupled coils, where the coil orientations are such that at the instant when the transistor is turned off, the current switches to the second coil to maintain the same flux in the core. Therefore, the dots on coils are as shown in Figure 8.2b, where the current into the dot of either coil produces core flux in the same direction. Commonly, the circuit of Figure 8.2b is redrawn as in Figure 8.2c.

We will consider the steady state in the incomplete demagnetization mode, where the energy is never completely depleted from the magnetic core. This corresponds to the continuous conduction mode (CCM) in buck-boost converters. We will assume ideal devices and components, the output voltage v Subscript o Baseline left-parenthesis t right-parenthesis equals upper V Subscript o , and the leakage inductances to be zero.

Turning on the transistor at t equals 0 in the circuit in Figure 8.2c applies the input voltage upper V Subscript i n across coil 1, and the core magnetizing flux phi Subscript m increases linearly from its initial value phi Subscript m Baseline left-parenthesis 0 right-parenthesis , as shown in the waveforms of Figure 8.3. During the transistor on interval upper D upper T Subscript s , the increase in flux can be calculated from Faraday’s law as:

upper Delta phi Subscript p minus p Baseline zero width space equals StartFraction upper V Subscript i n Baseline Over upper N 1 EndFraction upper D upper T Subscript s Baseline period (8.1)

FIGURE 8.3 Flyback converter waveforms.

Due to increasing phi Subscript m , the induced voltage left-parenthesis upper N 2 slash upper N 1 right-parenthesis upper V Subscript i n across coil 2 adds to the output voltage upper V Subscript o to reverse bias the diode, resulting in i Subscript o u t Baseline equals 0 . Corresponding to the core flux, the current i Subscript i n can be calculated using the relationship phi equals upper N i slash German upper R , where German upper R is the core reluctance in the flux path. Therefore, using Equation (8.1), the increase in the input current during the on interval from its initial value upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis can be calculated as

upper Delta phi Subscript p minus p Baseline zero width space equals StartFraction upper V Subscript i n Baseline Over upper N 1 EndFraction upper D upper T Subscript s Baseline (8.2)

During the on interval upper D upper T Subscript s , the output load is entirely supplied by the energy stored in the output capacitor, and the core magnetizing flux and the input current reach their peak values at the end of this interval:

ModifyingAbove phi With ˆ Subscript m Baseline equals phi Subscript m Baseline left-parenthesis 0 right-parenthesis plus zero width space StartFraction upper V Subscript i n Baseline Over upper N 1 EndFraction upper D upper T Subscript s Baseline (8.3)
ModifyingAbove upper I With ˆ Subscript i n Baseline equals upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis plus zero width space StartFraction German upper R Over upper N 1 squared EndFraction upper V Subscript i n Baseline upper D upper T Subscript s Baseline equals upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis plus zero width space StartFraction upper V Subscript i n Baseline left-parenthesis upper D upper T Subscript s Baseline right-parenthesis Over upper L Subscript m Baseline 1 Baseline EndFraction (8.4)

where upper L Subscript m Baseline 1 Baseline left-parenthesis equals upper N 1 squared slash German upper R right-parenthesis is the magnetizing inductance of the transformer seen from the primary side. After the on interval, turning off the transistor forces the input current in Figure 8.2c to zero. The magnetic energy stored in the magnetic core due to the flux phi Subscript m cannot change instantaneously, and hence the ampere-turns applied to the core must be the same at the instant immediately before and after turning the transistor off. Therefore, the current i Subscript o u t in coil 2 through the diode suddenly jumps to its peak value such that

upper N 2 ModifyingAbove upper I With ˆ Subscript o u t Baseline StartAbsoluteValue equals upper N 1 ModifyingAbove upper I With ˆ Subscript i n Baseline EndAbsoluteValue Subscript i Sub Subscript i n Subscript equals 0 Baseline Subscript i Sub Subscript o u t Subscript equals 0 (8.5)
therefore ModifyingAbove upper I With ˆ Subscript o u t Baseline equals StartFraction upper N 1 Over upper N 2 EndFraction ModifyingAbove upper I With ˆ Subscript i n Baseline period (8.6)

With the diode conducting, the output voltage upper V Subscript o appears across coil 2 with a negative polarity. Hence, during the off interval left-parenthesis 1 minus upper D right-parenthesis upper T Subscript s , the core flux declines linearly, as plotted in Figure 8.3, by upper Delta phi Subscript p minus p , where

upper Delta phi Subscript p minus p Baseline equals StartFraction upper V Subscript o Baseline Over upper N 2 EndFraction left-parenthesis 1 minus upper D right-parenthesis upper T Subscript s Baseline period (8.7)

Using Equations (8.1) and (8.7),

StartFraction upper V Subscript o Baseline Over upper V Subscript i n Baseline EndFraction equals left-parenthesis StartFraction upper N 2 Over upper N 1 EndFraction right-parenthesis StartFraction upper D Over 1 minus upper D EndFraction period (8.8)

The change in the current i Subscript o u t Baseline left-parenthesis t right-parenthesis can be calculated in a manner similar to Equation (8.2), and this current is plotted in Figure 8.3.

Equation (8.8) shows that in a flyback converter, the dependence of the voltage ratio on the duty ratio upper D is identical to that in the buck-boost converter, and it also depends on the coils’ turns ratio upper N 2 slash upper N 1 period Flyback converters require the minimum number of components by integrating the inductor (needed for a buck-boost operation) with the transformer that provides electrical isolation and matching of the voltage levels. These converters are very commonly used in low-power applications in the complete demagnetization mode (corresponding to the discontinuous conduction mode in buck-boost), which makes their control easier. A disadvantage of flyback converters is the need for snubbers to prevent voltage spikes across the transistor and diode due to leakage inductances associated with the two coils

Example 8.1

In a flyback converter, shown in Figure 8.2c, normal upper V Subscript i n Baseline equals 48 normal upper V , upper V Subscript o Baseline equals 5 normal upper V , upper N 1 slash upper N 2 equals 6 , and the magnetizing inductance upper L Subscript m Baseline 1 Baseline equals 150 mu upper H . This converter is operating in equivalent CCM with a switching frequency f Subscript s Baseline equals 200 kHz and supplying an output load upper P Subscript o Baseline equals 60 normal upper W . Assuming this converter to be lossless, calculate the waveforms associated with it.

Solution

From Equation (8.8), the duty ratio upper D equals 0.385 , where upper T Subscript s Baseline equals 5 mu s . The average currents are upper I Subscript i n Baseline equals 0.6 25 normal upper A and upper I Subscript o u t Baseline equals 6 normal upper A . In Figure 8.3, the rise in current during the on interval upper D upper T Subscript s can be calculated as

ModifyingAbove upper I With ˆ Subscript i n Baseline minus upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis equals StartFraction upper V Subscript i n Baseline left-parenthesis upper D upper T Subscript s Baseline right-parenthesis Over upper L Subscript m Baseline 1 Baseline EndFraction equals 0.616 normal upper A

From the waveforms of Figure 8.3, the average input current can be calculated as follows:

StartLayout 1st Row 1st Column upper I Subscript i n Baseline zero width space equals StartFraction ModifyingAbove upper I With caret Subscript i n Baseline plus upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis Over 2 EndFraction upper D equals 0.625 normal upper A semicolon 2nd Column ModifyingAbove upper I With caret Subscript i n Baseline plus upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis equals 3.247 normal upper A EndLayout period

From the equations above, in Figure 8.3, ModifyingAbove upper I With ˆ Subscript i n Baseline equals 1.93 normal upper A and upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis equals 1.315 normal upper A . The output current has a peak value ModifyingAbove upper I With ˆ Subscript o u t Baseline equals ModifyingAbove upper I With ˆ Subscript i n Baseline StartFraction upper N 1 Over upper N 2 EndFraction equals 11.58 normal upper A and upper I Subscript o u t Baseline left-parenthesis 0 right-parenthesis equals upper I Subscript i n Baseline left-parenthesis 0 right-parenthesis StartFraction upper N 1 Over upper N 2 EndFraction equals 7.89 normal upper A .

8.4.1 Simulation and Hardware Prototyping—CCM without Snubber

The simulation of a nonideal flyback converter is demonstrated by means of an example:

Example 8.2

In the flyback converter shown in Figure 8.2c, upper C equals 490 mu upper F , and upper R equals 10 upper Omega . It is operating in DC steady state under the following conditions: upper V Subscript i n Baseline equals 15 normal upper V , upper D equals 0.5 , and f Subscript s Baseline equals 100 kHz . The transformer’s primary-to-secondary turns ratio is 2:1. The primary side has a magnetizing inductance of upper L Subscript m Baseline equals 27.8 mu upper H and a leakage inductance of upper L Subscript l Baseline equals 0.26 mu upper H . For the switch and the diode, use the parameters given in the Appendix of Chapter 2. Simulate this converter using LTspice.

Solution The simulation file used in this example is available on the accompanying website. The LTspice model is as shown in Figure 8.4, and the steady-state waveforms from the simulation of this model are shown in Figure 8.5.

FIGURE 8.4 LTspice model.

FIGURE 8.5 LTspice simulation results.

The Workbench model for implementing the above example in hardware using the Sciamble lab kit is as shown in Figure 8.6.

FIGURE 8.6 Workbench model.

The steady-state waveforms from running the flyback converter using the Sciamble laboratory kit are shown in Figure 8.7. The step-by-step procedure for re-creating the above hardware implementation is presented in [1].

FIGURE 8.7 Workbench hardware results: (1) Input current, (2) Switch-node voltage, (3) Diode current and (4) Output voltage.

8.4.2 RCD Snubber

Unlike the case of an ideal flyback converter waveform shown in Figure 8.3, the switch-node voltage waveform of a practical flyback converter, shown in Figure 8.8, has significant ringing. The energy stored in the leakage inductance upper L Subscript l , unlike the energy stored in the magnetizing inductance upper L Subscript m , does not transfer over to the secondary side when the switch is turned off. This energy charges up the switch’s parasitic capacitance, leading to a high voltage across the switch, causing significant voltage stress, which can damage the switch, the transformer insulation, or both.

FIGURE 8.8 Practical flyback converter parasitic elements.

In a practical flyback converter, the magnitude of the voltage swing is clamped by the use of a snubber circuit [2]. This section presents the operation and design of one of the commonly used snubber circuit, RCD snubber, shown in Figure 8.9.

FIGURE 8.9 RCD snubber.

We will first analyze the steady-state operation of the snubber circuit before proceeding with how to determine the snubber parameters. The voltage across the snubber capacitor is assumed to be a constant upper V Subscript c s , which is justified given a sufficiently large upper C Subscript s .

8.4.2.1 Steady-State Operation of RCD Snubber

At time 0 less-than t less-than upper D upper T Subscript s , when the transistor is on, as shown in Figure 8.10a, the primary current increases linearly, as shown in Figure 8.10b. During this period, the voltage across the transistor is 0 as shown in Figure 8.10c, and there is no current flowing into the snubber circuit because the diode upper D Subscript s is reverse biased with a voltage of upper V Subscript i n Baseline plus upper V Subscript c s across it, as shown in Figure 8.10d. The snubber capacitor is slowly discharged by the snubber resistor, as shown by the negative current, minus StartFraction upper V Subscript c s Baseline Over upper R Subscript s Baseline EndFraction in Figure 8.10e.

FIGURE 8.10 RCD snubber waveforms

When the transistor is turned off, the parasitic capacitance upper C Subscript upper P is charged up to the sum of the input voltage and the reflected secondary voltage, upper V Subscript i n Baseline plus n upper V Subscript o where n equals StartFraction upper N 1 Over upper N 2 EndFraction . During this interval, upper D upper T Subscript s Baseline less-than t less-than upper T 1 , the energy stored in the magnetizing inductance contributes to a very rapid charging of the transistor’s parasitic capacitance upper C Subscript upper P as well as the discharging of the secondary side diode’s junction capacitance upper C Subscript upper D . The input current i Subscript i n remains relatively constant, given the negligible energy transfer from the magnetizing inductance to the parasitic capacitances.

Once the secondary side diode’s junction capacitance is fully discharged, and the diode begins conducting and simultaneously upper C Subscript upper P is charged to upper V Subscript i n Baseline plus n upper V Subscript o , the energy stored in the magnetizing inductance starts charging the output capacitor.

During the time interval upper T 1 less-than t less-than upper T 2 , the snubber diode is still reverse biased since n upper V Subscript o Baseline less-than upper V Subscript upper C s . The voltage across the transistor continues to rise until it reaches upper V Subscript i n Baseline plus upper V Subscript upper C s (plus the diode forward voltage drop, which is assumed to be negligible in this discussion), forward biasing the snubber diode. The primary current during this interval falls rapidly as only the energy stored in the primary side leakage inductance is available to charge upper C Subscript upper P .

In the absence of the snubber circuit, the energy in the leakage inductance continues to charge upper C Subscript upper P , which leads to high voltage ringing across the transistor, as seen in Figure 8.7. In addition to the issue of high voltage, the ringing frequency, given by Equation (8.9), is typically in the order of MHz and is a source of significant noise and EMI:

f Subscript p Baseline equals StartFraction 1 Over 2 pi StartRoot upper L Subscript l Baseline upper C Subscript p Baseline EndRoot EndFraction period (8.9)

In the presence of the snubber circuit, the primary current flows through the forward-biased snubber diode, charging the snubber capacitor. upper V Subscript upper C s remains relatively a constant by design, as explained in the next section. During this interval, upper T 2 less-than t less-than upper T 3 , the primary current continues to fall rapidly. The voltage across the transistor remains clamped at upper V Subscript i n Baseline plus upper V Subscript upper C s .

Once the leakage energy is fully transferred to the clamp capacitor at time t equals upper T 3 , the primary current goes to 0 , and the snubber diode gets reverse biased as the transistor voltage drops from upper V Subscript i n Baseline plus upper V Subscript upper C s to upper V Subscript i n Baseline plus n upper V Subscript o .

Example 8.3

In Example 8.1, calculate the frequency of the ringing of the voltage across the transistor when it turns off. The transistor’s parasitic capacitance upper C Subscript upper P Baseline equals 970 p upper F .

Solution From Equation (8.9), f Subscript p Baseline equals StartFraction 1 Over 2 pi StartRoot upper L Subscript l Baseline upper C Subscript p Baseline EndRoot EndFraction almost-equals 10 upper M upper H z .

8.4.2.2 Design of RCD Snubber

At steady state, since the voltage across the snubber capacitor is a constant, the current through the capacitor averaged over a switching cycle upper T Subscript s Baseline left-parenthesis equals StartFraction 1 Over f Subscript s Baseline EndFraction right-parenthesis is zero:

one-half upper I Subscript p k Baseline left-parenthesis upper T 3 minus upper T 2 right-parenthesis minus StartFraction upper V Subscript upper C s Baseline Over upper R Subscript s Baseline EndFraction upper T Subscript s Baseline equals 0 period (8.10)

During the time interval upper T 2 less-than t less-than upper T 3 , when the snubber diode is forward biased, the voltage across the inductor from Figure 8.8 is the sum of the voltage across the snubber capacitor and the voltage across the transformer primary winding:

upper V Subscript upper L l Baseline equals upper L Subscript l Baseline StartFraction upper Delta upper I Subscript l Baseline Over upper Delta t EndFraction equals upper V Subscript upper C s Baseline minus n upper V Subscript o Baseline period (8.11)

The current through the leakage inductor goes from approximately upper I Subscript p k to zero, as seen in Figure 8.10b. The duration of the interval when the snubber diode is conducting can be obtained from Equation (8.11):

upper L Subscript l Baseline StartFraction upper Delta upper I Subscript l Baseline Over upper Delta t EndFraction equals upper L Subscript l Baseline StartFraction upper I Subscript p k Baseline minus 0 Over upper T 3 minus upper T 2 EndFraction equals upper V Subscript upper C s Baseline minus n upper V Subscript o Baseline right double arrow upper T Subscript s n Baseline equals upper T 3 minus upper T 2 equals upper L Subscript l Baseline StartFraction upper I Subscript p k Baseline Over upper V Subscript upper C s Baseline minus n upper V Subscript o Baseline EndFraction period (8.12)

The expression for the snubber resistor can be obtained using Equations (8.10) and (8.12):

one-half upper I Subscript p k Superscript 2 Baseline upper L Subscript l Baseline StartFraction 1 Over upper V Subscript upper C s Baseline minus n upper V Subscript o Baseline EndFraction minus StartFraction upper V Subscript upper C s Baseline Over upper R Subscript s Baseline EndFraction upper T Subscript s Baseline equals 0
right double arrow upper R Subscript s Baseline equals StartFraction upper V Subscript upper C s Baseline left-parenthesis upper V Subscript upper C s Baseline minus n upper V Subscript o Baseline right-parenthesis Over one-half upper I Subscript p k Superscript 2 Baseline upper L Subscript l Baseline f Subscript s Baseline EndFraction period (8.13)

Given the converter operating condition and the desired maximum transistor voltage, the snubber resistor can be determined using the above expression. The lower the tolerable voltage across the transistor, the smaller the snubber resistor and thus higher losses in the snubber circuit. The power lost in the snubber circuit is:

upper P Subscript s Baseline equals StartFraction upper V Subscript upper C s Superscript 2 Baseline Over upper R Subscript s Baseline EndFraction equals one-half upper I Subscript p k Superscript 2 Baseline upper L Subscript l Baseline f Subscript s Baseline StartFraction upper V Subscript upper C s Baseline Over left-parenthesis upper V Subscript upper C s Baseline minus n upper V Subscript o Baseline right-parenthesis EndFraction equals alpha upper P Subscript upper L l Baseline comma (8.14)

where upper P Subscript upper L l Baseline equals one-half upper I Subscript p k Superscript 2 Baseline upper L Subscript l Baseline f is the leakage inductor power, the energy stored in the leakage inductor per switching cycle time period. alpha equals 1 slash left-parenthesis 1 minus StartFraction n upper V Subscript o Baseline Over upper V Subscript upper C s Baseline EndFraction right-parenthesis is the factor by which the losses in the circuit are scaled due to the presence of the snubber compared to the circuit without a snubber. Since upper V Subscript upper C s Baseline ampersand gt semicolon n upper V Subscript o , alpha is always greater than 1. The higher the snubber voltage, the lower the losses and vice versa.

The value of the snubber capacitor isn’t as crucial as that of the resistor. The only requirement is that the capacitance is large enough to maintain the snubber voltage a constant. An approximate expression can be obtained from the snubber capacitor current waveform in Figure 8.10e. Assuming that the current in the snubber resistor is negligible compared to the peak input current upper I Subscript p k , during the interval when the snubber diode is reverse biased:

i Subscript upper C s Baseline equals upper C Subscript s Baseline StartFraction upper Delta upper V Subscript upper C s Baseline Over upper Delta upper T EndFraction right double arrow StartFraction upper V Subscript upper C s Baseline Over upper R Subscript s Baseline EndFraction equals upper C Subscript s Baseline StartFraction upper Delta upper V Subscript upper C s Baseline Over upper T Subscript s Baseline minus upper T Subscript s n Baseline EndFraction
right double arrow upper C Subscript s Baseline equals StartFraction 1 Over upper R Subscript s Baseline EndFraction StartFraction upper V Subscript upper C s Baseline Over upper Delta upper V Subscript upper C s Baseline EndFraction left-parenthesis upper T Subscript s Baseline minus upper T Subscript s n Baseline right-parenthesis almost-equals StartFraction upper T Subscript s Baseline Over upper R Subscript s Baseline EndFraction StartFraction upper V Subscript upper C s Baseline Over upper Delta upper V Subscript upper C s Baseline EndFraction period (8.15)

In the above expression StartFraction upper Delta upper V Subscript upper C s Baseline Over upper V Subscript upper C s Baseline EndFraction is the ratio of the snubber capacitor peak-peak ripple voltage and the snubber capacitor average voltage over a switching cycle. This value is typically chosen between 0.01 and 0.1.

The diode must be a fast-acting diode such as the Schottky diode since the conduction period upper T Subscript s n typically lasts for a short interval.

Example 8.4

Design a snubber for the flyback converter in Example 8.1. Assume that the snubber diode is ideal and the peak input current is upper I Subscript p k Baseline equals 2 upper A . The voltage across the transistor should not exceed 35 upper V under the given operating conditions.

Solution Using Equation (8.8), under ideal conditions.

The snubber capacitor voltage must be chosen such that it is greater than the voltage across the transistor when it is off and less than the given maximum allowable voltage across the transistor, i.e.,

30 upper V less-than upper V Subscript i n Baseline plus upper V Subscript upper C p Baseline less-than 35 upper V right double arrow 15 upper V less-than upper V Subscript upper C p Baseline less-than 20 upper V comma

allowing for a snubber capacitor ripple of 10 percent-sign , which is 2 upper V at the worst case. To keep within the specified snubber voltage limit, accounting for the ripple, the voltage is chosen to be upper V Subscript upper C p Baseline equals 18 upper V .

The snubber resistance can be obtained using Equation (8.13):

upper R Subscript s Baseline equals StartFraction 18 left-parenthesis 18 minus 2 times 7.5 Subscript o Baseline right-parenthesis Over one-half 2 squared times 0.26 mu times 100 k EndFraction almost-equals 1 k upper Omega period

The power lost in the snubber circuit can be obtained using Equation (8.14):

upper P Subscript s Baseline equals StartFraction upper V Subscript upper C s Superscript 2 Baseline Over upper R Subscript s Baseline EndFraction equals StartFraction 18 squared Over 1000 EndFraction equals 0.324 upper W comma

which is about 6 times the leakage inductance power left-parenthesis upper P Subscript upper L l Baseline equals one-half upper I Subscript p k Superscript 2 Baseline upper L Subscript l Baseline f equals 0.052 upper W right-parenthesis , and is otherwise lost without the snubber circuit.

The snubber capacitance is obtained using Equation (8.15):

upper C Subscript s Baseline equals StartFraction upper T Subscript s Baseline Over upper R Subscript s Baseline EndFraction StartFraction upper V Subscript upper C s Baseline Over upper Delta upper V Subscript upper C s Baseline EndFraction equals StartFraction 1 Over 100 k times 1 k EndFraction StartFraction 18 Over 0.1 times 18 EndFraction equals 0.1 mu upper F period

8.4.3 Simulation and Hardware Prototyping—CCM with Snubber

The simulation of a nonideal flyback converter with a primary side snubber is demonstrated by means of an example:

Example 8.5

In the flyback converter shown in Figure 8.2c, upper C equals 490 mu upper F , and upper R equals 10 upper Omega . It is operating in DC steady state under the following conditions: upper V Subscript i n Baseline equals 15 normal upper V , upper D equals 0.5 , and f Subscript s Baseline equals 100 kHz . The transformer’s primary-to-secondary turns ratio is 2:1. The primary side has a magnetizing inductance of upper L Subscript m Baseline equals 27.8 mu upper H and a leakage inductance of upper L Subscript l Baseline equals 0.26 mu upper H . The snubber resistance upper R Subscript s Baseline equals 1 k upper Omega and the snubber capacitance upper C Subscript s Baseline equals 0.1 mu upper F . For the switch and the diode, use the parameters given in the Appendix of Chapter 2. Simulate this converter using LTspice.

Solution The simulation file used in this example is available on the accompanying website. The LTspice model is shown in Figure 8.11, and the steady-state waveforms from the simulation of this model are shown in Figure 8.12.

FIGURE 8.11 LTspice model.

FIGURE 8.12 LTspice simulation results.

The Workbench model for implementing the above example in hardware using the Sciamble lab kit is the same as the one shown in Figure 8.6. The steady-state waveforms from running the flyback converter with an RCD snubber using the Sciamble laboratory kit are shown in Figure 8.13. The step-by-step procedure for re-creating the above hardware implementation is presented in [3].

FIGURE 8.13 Workbench hardware results: (1) Input current, (2) Switch-node

As seen in Figure 8.13, the voltage across the switch is clamped to within the 35 upper V design requirement given in Example 8.4.

8.4.4 Simulation and Hardware Prototyping—DCM with Snubber

In the previous sections, the operation of the flyback converter was considered under continuous conduction mode. The operation of the flyback converter under discontinuous conduction mode is mostly similar to that of the buck-boost converter. The simulation of a nonideal flyback converter with a primary side snubber under discontinuous conduction mode is demonstrated by means of an example:

Example 8.6

The flyback converter in Example 8.5 is operating at a duty of upper D equals 0.15 and the load resistance upper R equals 8 upper Omega . Simulate this converter using LTspice.

Solution The simulation file used in this example is available on the accompanying website. The LTspice model is the same as the one shown in Figure 8.11, and the steady-state waveforms from the simulation of this model are shown in Figure 8.14.

FIGURE 8.14 LTspice simulation results.

The Workbench model for implementing the above example in hardware using the Sciamble lab kit is the same as the one shown in Figure 8.6. The steady-state waveforms from running the flyback converter with an RCD snubber using the Sciamble laboratory kit under DCM are shown in Figure 8.15.

FIGURE 8.15 Workbench hardware results: (1) Input current, (2) Switch-node voltage, (3) Diode current and (4) Secondary side voltage.

Under DCM, when the secondary side current goes to zero, and the diode is reverse biased, the voltage across the transistor transitions from upper V Subscript i n Baseline plus n upper V Subscript o to upper V Subscript i n . The frequency of this ringing is given by:

f Subscript d Baseline equals StartFraction 1 Over 2 pi StartRoot left-parenthesis upper L Subscript l Baseline plus upper L Subscript m Baseline right-parenthesis upper C Subscript p Baseline EndRoot EndFraction period (8.16)

Many commercially available flyback converter controller ICs, such as Texas Instruments’ UCC28704, typically operate under DCM to make use of the inherent ringing of the transistor voltage to turn on the transistor when the voltage across the switch is at the lowest point, thereby reducing the switching losses.

So far, we have only discussed the design of snubber for the primary side. As seen in Figure 8.15, there is significant ringing in the voltage across the secondary side due to the leakage inductance and the diode’s junction capacitance. The frequency of this typically tends to be much higher than that of the primary side ringing. This can be addressed by the use of a simple RC snubber across the diode, as presented in [2].

8.5 FORWARD CONVERTERS

The forward converter and its variations derived from a buck converter are commonly used in applications at low power levels up to 1 kW. A buck converter is shown in Figure 8.16a. In this circuit, a three-winding transformer is added, as shown in Figure 8.16b, to realize a forward converter. The third winding in series with a diode upper D 3 , and the diode upper D 1 are needed to demagnetize the core every switching cycle. The winding orientations in Figure 8.16b are such that the current into the dot of any of the windings will produce core flux in the same direction. We will consider steady-state converter operation in the continuous conduction mode where the output inductor current i Subscript upper L flows continuously. In the following analysis, we will assume ideal semiconductor devices, v Subscript o Baseline left-parenthesis t right-parenthesis equals upper V Subscript o , and the leakage inductances to be zero.

FIGURE 8.16 Buck and forward converters.

Initially, assuming an ideal transformer in the forward converter of Figure 8.16b, the third winding and the diode upper D 3 can be removed, and upper D 1 can be replaced by a short circuit. In such an ideal case, the forward converter operation is identical to that of the buck converter, as shown by the waveform in Figure 8.17, except for the presence of the transformer turns ratio upper N 2 slash upper N 1 . Therefore, in the continuous conduction mode,

upper V Subscript o Baseline zero width space equals zero width space left-parenthesis StartFraction upper N 2 Over upper N 1 EndFraction right-parenthesis upper D upper V Subscript i n Baseline period (8.17)

FIGURE 8.17 Forward converter operation.

In the case of a real transformer, the core must be completely demagnetized during the off interval of the transistor, hence the need for the third winding and the diodes upper D 1 and upper D 3 , as shown in Figure 8.4b. Turning on the transistor causes the magnetizing flux in the core to build up, as shown in Figure 8.18. During this on-interval upper D upper T Subscript s , upper D 3 gets reverse biased, thus preventing the current from flowing through the tertiary winding. The diode upper D 2 also gets reverse biased, and the output inductor current flows through upper D 1 .

FIGURE 8.18 Forward converter core flux.

When the transistor is turned off, the magnetic energy stored in the transformer core forces a current to flow into the dotted terminal of the tertiary winding since the current into the dotted terminal of the secondary winding cannot flow due to upper D 1 , which results in upper V Subscript i n being applied negatively across the tertiary winding, and the core flux to decline, as shown in Figure 8.6. (The output inductor current freewheels through upper D 2 .) After an interval upper T Subscript d e m a g , the core flux comes to zero and stays zero during the remaining interval until the next cycle begins.

To avoid the core from saturating, upper T Subscript d e m a g must be less than the off interval left-parenthesis 1 minus upper D right-parenthesis upper T Subscript s of the transistor. Typically, windings 1 and 3 are wound bifilar to provide a very tight mutual coupling between the two, and hence, upper N 3 equals upper N 1 . Therefore, a per-turn voltage of equal magnitude but opposite polarity is applied to the core during upper D upper T Subscript s and upper T Subscript d e m a g . With upper N 3 equals upper N 1 , upper T Subscript d e m a g Baseline equals upper D upper T Subscript s , and at the upper limit, upper D upper T Subscript s and upper T Subscript d e m a g are both equal to upper T Subscript s Baseline slash 2 . Therefore, with upper N 3 equals upper N 1 , the upper limit on the duty ratio is upper D Subscript max Baseline equals 0.5 .

Example 8.7

In a forward converter, shown in Figure 8.16b, upper V Subscript i n Baseline equals 48 normal upper V , upper V Subscript o Baseline equals 5 normal upper V , upper N 1 slash upper N 2 equals 3.5 , upper N 1 slash upper N 3 equals 1 , and the magnetizing inductance upper L Subscript m Baseline 1 Baseline equals 150 mu upper H . This converter is operating in equivalent CCM with a switching frequency f Subscript s Baseline equals 200 kHz and supplying an output load upper P Subscript o Baseline equals 60 normal upper W . Assume the filter inductor current i Subscript upper L to be ripple-free. Assuming this converter to be lossless, calculate the waveforms associated with it.

Solution From Equation (8.17), the duty ratio upper D equals 0.365 , where upper T Subscript s Baseline equals 5 mu s . The average currents are upper I Subscript i n Baseline equals 1.25 normal upper A and upper I Subscript i n Baseline equals 1.25 normal upper A . The voltage waveforms are shown in Figure 8.19, where the output current reflected to the primary side is left-parenthesis upper N 2 slash upper N 1 right-parenthesis upper I Subscript o u t Baseline equals 3.43 normal upper A . The peak of the magnetizing current during the on interval upper D upper T Subscript s can be calculated as

upper Delta upper I Subscript m Baseline equals StartFraction upper V Subscript i n Baseline left-parenthesis upper D upper T Subscript s Baseline right-parenthesis Over upper L Subscript m Baseline 1 Baseline EndFraction equals 0.5 normal upper A period

FIGURE 8.19 Waveforms in the forward converter of Example 8.7.

During the transistor off interval, this magnetizing current, flowing through the diode D3, decreases and comes to zero after upper T Subscript d e m a g Baseline equals upper D upper T Subscript s Baseline equals 1.825 mu s, as shown in Figure 8.19.

8.5.1 Simulation and Hardware Prototyping

The simulation of a nonideal forward converter is demonstrated by means of an example:

Example 8.8

In the forward converter shown in Figure 8.16c, upper C equals 490 mu upper F , upper L equals 68 mu upper H , upper R equals 10 upper Omega , upper N 1 slash upper N 2 equals 1 , and upper N 1 slash upper N 3 equals 1 . It is operating in DC steady state under the following conditions: upper V Subscript i n Baseline equals 15 normal upper V , upper D equals 0.3 , and f Subscript s Baseline equals 100 kHz . The primary side has a magnetizing inductance of upper L Subscript m Baseline equals 72.9 mu upper H and a leakage inductance of upper L Subscript l Baseline equals 0.12 mu upper H . For the switch and the diode, use the parameters given in the Appendix of Chapter 2. Simulate this converter using LTspice.

Solution The simulation file used in this example is available on the accompanying website. The LTspice model is, as shown in Figure 8.20, and the steady-state waveforms from the simulation of this model are shown in Figure 8.21.

FIGURE 8.20 LTspice model.

FIGURE 8.21 LTspice simulation results.

The Workbench model for implementing the above example in hardware using the Sciamble lab kit is as shown in Figure 8.22.

FIGURE 8.22 Workbench model.

The steady-state waveforms from running the forward converter using the Sciamble laboratory kit are shown in Figure 8.23. The step-by-step procedure for re-creating the above hardware implementation is presented in [4].

FIGURE 8.23 Workbench hardware results: (1) Input current, (2) Switch-node voltage, (3) Diode current and (4) Output voltage.

Unlike the voltage across the transistor of the flyback converter without a snubber, as seen in Figure 8.7, the voltage across the transistor of a forward converter without a snubber doesn’t ring as much as seen in Figure 8.23. This is due to two reasons: the forward converter transformer typically has lower leakage inductance due to tighter coupling between the primary and the demagnetization winding, and sustained voltage greater than 2 upper V Subscript i n across the transistor will lead to forward-biasing the demagnetization winding diode, thus effectively clamping the voltage at the sum of 2 upper V Subscript i n and the diode forward voltage drop.

In cases where the leakage inductance of the transformer is high or the trace parasitic inductance is high due to poor layout, an RCD snubber, explained in the earlier section, can be used to limit the transient voltage spikes.

8.5.2 Two-Switch Forward Converters

Single-switch forward converters are used in power ratings up to a few hundred watts. However, two-switch forward converters discussed below eliminate the need for a separate demagnetizing winding and are used in much higher power ratings of 1 kW and even higher.

Figure 8.24 shows the topology of the two-switch forward converter, where both transistors are gated on and off simultaneously with a duty ratio upper D less-than-or-equal-to 0.5 . During the on interval upper D upper T Subscript s , when both transistors are on, diodes upper D 1 and upper D 2 get reverse biased, and the output inductor current i Subscript upper L flows through upper D Subscript o , similar to that in a single-switch forward converter. During the off interval, when both transistors are turned off, the magnetizing current in the transformer core flows through the two primary-side diodes into upper V Subscript i n , thus applying upper V Subscript i n negatively to the core and causing it to demagnetize. Application of minus upper V Subscript i n to the primary winding causes upper D Subscript o to get reverse biased, and the output inductor current i Subscript upper L freewheels through upper D Subscript upper F .

FIGURE 8.24 Two-switch forward converter.

Based on the discussion regarding the demagnetization of the core in a single-switch forward converter, the switch duty ratio upper D is limited to 0.5 . The voltage conversion ratio remains the same as in Equation (8.17).

8.6 FULL-BRIDGE CONVERTERS

Full-bridge converters consist of four transistors and hence are economically feasible only at higher power levels in applications at a few hundred watts and higher. Like forward converters, full-bridge converters are also derived from buck converters. Unlike flyback and forward converters that operate in only one quadrant of the B-H loop, full-bridge converters use the magnetic core in two quadrants.

A full-bridge converter consists of two switching power-poles, as shown in Figure 8.25, with a center-tapped transformer secondary winding. In analyzing this converter, we will assume the transformer ideal, although the effects of magnetizing current can be easily accounted for. We will consider steady-state converter operation in the continuous conduction mode where the output inductor current i Subscript upper L flows continuously. As with previous converters, we will assume ideal devices and components and v Subscript o Baseline left-parenthesis t right-parenthesis equals upper V Subscript o .

FIGURE 8.25 Full-bridge converter.

In the full-bridge converter of Figure 8.9, the voltage v 1 applied to the primary winding alternates without a DC component. The waveform of this voltage is shown in Figure 8.26, where v 1 equals upper V Subscript i n when transistors upper T 1 and upper T 2 are on during upper D upper T Subscript s , and v 1 equals minus upper V Subscript i n when upper T 3 and upper T 4 are on for an interval of the same duration. This waveform applies equal positive and negative volt-seconds to the transformer primary. The switch duty ratio upper D left-parenthesis zero width space less-than zero width space 0.5 right-parenthesis is controlled to achieve the output voltage regulation by means of zero intervals between the positive and the negative applied voltages.

FIGURE 8.26 Full-bridge converter waveforms.

The way the voltage across the primary winding, and hence the secondary winding, is forced to be zero classifies full-bridge converters into the following two categories:

  1. Pulse-width modulated (PWM)
  2. Phase-shift modulated (PSM)

PWM Control. In PWM control, all four transistors are turned off, resulting in a zero voltage across the transformer windings, as discussed shortly. With all transistors off, the output inductor current freewheels through the two secondary windings, and there are no conduction losses on the primary side of the transformer. Therefore, the PWM control results in lower conduction losses, which is why it is the control method we focus on in this chapter.

PSM Control. In phase-shift modulated control, the two transistors of each power pole are operated at nearly 50% duty ratio, with upper D asymptotically-equals 0.5 . The output of each power pole pulsates between upper V Subscript i n and 0 with a duty ratio of nearly 50%. The length of the zero intervals is controlled by phase-shifting the two power-pole outputs with respect to each other, as the name of this control implies. During zero intervals, either both transistors at the top or both transistors at the bottom are on, creating a short circuit (through one of the anti-parallel diodes, depending on the direction of the current) across the primary winding, resulting in v 1 equals 0 . During this short-circuited condition, the output inductor current is reflected to the primary winding and circulates through the primary-side semiconductor devices, causing additional conduction losses. However, increased conduction losses can be offset by the reduction in switching losses by this means of control, as we will discuss in detail in Chapter 10 on soft-switching.

8.6.1 PWM Control

As shown by the block diagram of Figure 8.27a, the PWM IC for full-bridge converters provides gate signals to the transistor pairs (upper T 1 comma upper T 2 and upper T 3 comma upper T 4 ) during alternate cycles of the ramp voltage in Figure 8.27b.

FIGURE 8.27 PWM IC and control signals for transistors.

Corresponding to these PWM switching signals, the resulting sub-circuits are shown in Figure 8.28 for one-half switching cycle, where the other half-cycle is symmetric.

FIGURE 8.28 Full-bridge: sub-circuits.

Interval upper D upper T Subscript s with transistors upper T 1 comma upper T 2 in their on state. Turning on upper T 1 comma upper T 2 applies a positive voltage upper V Subscript i n to the primary winding, causing upper D 2 to become reverse biased and i Subscript upper L is carried through upper D 1 , as shown in Figure 8.28a. During this interval, v Subscript upper A Baseline equals left-parenthesis upper N 2 slash upper N 1 right-parenthesis upper V Subscript i n , as plotted in Figure 8.29.

FIGURE 8.29 Full-bridge converter waveforms.

Interval left-parenthesis 1 slash 2 minus upper D right-parenthesis upper T Subscript s with all transistors off. When all the transistors are turned off, there is no current in the primary winding, and the output inductor current divides equally (assuming an ideal transformer) between the two output diodes, as shown in the sub-circuit of Figure 8.28b. This ensures that the total ampere-turns acting on the transformer core equal zero because of i Subscript upper L Baseline slash 2 coming out of the dotted terminal and i Subscript upper L Baseline slash 2 going into the dotted terminal. Applying Kirchhoff’s voltage law in the loop consisting of the two secondaries in Figure 8.27b shows that v 2 plus v prime 2 equals 0 . Since v 2 equals v prime 2 , the two voltages must be individually zero, and hence also the primary voltage v 1 :

v 1 equals v 2 equals v prime 2 equals 0 (8.18)

During this interval, v Subscript upper A Baseline equals 0 as plotted in Figure 8.29.

The above discussion completes the discussion of one-half switching cycle. The other half-cycle with upper T 3 comma upper T 4 on applies a negative voltage (minus upper V Subscript i n ) across the primary winding for an interval upper D upper T Subscript s and results in upper D 2 conducting and upper D 1 reverse biased. During this interval, v Subscript upper A Baseline equals left-parenthesis upper N 2 slash upper N 1 right-parenthesis upper V Subscript i n as before when the positive voltage was applied to the primary winding. The waveforms during this half-cycle are as plotted in Figure 8.29.

From Figure 8.29, recognizing that upper V Subscript upper A Baseline equals upper V Subscript o in the DC steady state,

StartFraction upper V Subscript o Baseline Over upper V Subscript i n Baseline EndFraction equals 2 left-parenthesis StartFraction upper N 2 Over upper N 1 EndFraction right-parenthesis upper D period (8.19)

Example 8.9

In a full-bridge converter shown in Figure 8.25, upper V Subscript i n Baseline equals 48 normal upper V , upper V Subscript o Baseline equals 5 normal upper V , and upper N 1 slash upper N 2 equals 6 . This converter is operating in CCM with a switching frequency f Subscript s Baseline equals 200 kHz and supplying an output load upper P Subscript o Baseline equals 100 normal upper W . The filter inductor has an inductance of upper L equals 0.25 mu upper H . Assuming this converter to be lossless, calculate the waveforms associated with it.

Solution From Equation (8.19), the duty ratio upper D equals 0.3125 , where upper T Subscript s Baseline equals 5 mu s . The average currents are upper I Subscript i n Baseline equals 2.083 normal upper A and upper I Subscript o u t Baseline equals 20 normal upper A . The voltage waveforms are shown in Figure 8.14. The peak-peak ripple in the filter inductor current i Subscript upper L can be calculated from the voltage waveforms in Figure 8.30,

upper Delta upper I Subscript upper L comma zero width space p minus p Baseline equals StartFraction left-parenthesis v Subscript upper A Baseline minus upper V Subscript o Baseline right-parenthesis left-parenthesis upper D upper T Subscript s Baseline right-parenthesis Over upper L EndFraction equals 18.75 normal upper A

FIGURE 8.30 Waveforms of the full-bridge converter of Example 8.3.

Therefore, the i Subscript upper L waveform is as shown in Figure 8.30, with a minimum of IL, min = Iout upper I Subscript upper L comma min Baseline equals upper I Subscript o u t Baseline minus StartFraction upper Delta upper I Subscript upper L comma zero width space p minus p Baseline Over 2 EndFraction equals 10.625 normal upper A and a maximum of d Subscript i Baseline equals StartFraction 6 Over h Subscript i Baseline plus h Subscript i plus 1 Baseline EndFraction left-parenthesis StartFraction y Subscript i plus 1 Baseline minus y Subscript i Baseline Over h Subscript i plus 1 Baseline EndFraction minus StartFraction y Subscript i Baseline minus y Subscript i minus 1 Baseline Over h Subscript i Baseline EndFraction right-parenthesis equals 6 f left-parenthesis x Subscript i minus 1 Baseline comma x Subscript i Baseline comma x Subscript i plus 1 Baseline right-parenthesis .

Taking the transformer turns ratio into account, the primary current i 1 and the input current i Subscript i n ramp from 1.77 upper A to 4.896 upper A , and are zero when all the transistors are off.

8.6.2 Simulation and Hardware Prototyping

The simulation of a PWM full-bridge converter is demonstrated by means of an example:

Example 8.10

In the full-bridge converter shown in Figure 8.25, upper C equals 490 mu upper F , upper L equals 68 mu upper H , upper R equals 8 upper Omega , and upper N 1 slash upper N 2 equals 1 . It is operating in DC steady state under the following conditions: upper V Subscript i n Baseline equals 15 normal upper V , upper D equals 0.3 , and f Subscript s Baseline equals 100 kHz . The primary side has a magnetizing inductance of upper L Subscript m Baseline equals 72.9 mu upper H and a leakage inductance of upper L Subscript l Baseline equals 0.14 mu upper H . For the switch and the diode, use the parameters given in the Appendix of Chapter 2. Simulate this converter using LTspice.

Solution⋓The simulation file used in this example is available on the accompanying website. The LTspice model is shown in Figure 8.31, and the steady-state waveforms from the simulation of this model are shown in Figure 8.32.

FIGURE 8.31 LTspice model.

FIGURE 8.32 LTspice simulation results.

The Workbench model for implementing the above example in hardware using the Sciamble lab kit is shown in Figure 8.33

FIGURE 8.33 Workbench model.

The steady-state waveforms from running the full-bridge converter using the Sciamble laboratory kit are shown in Figure 8.34. The step-by-step procedure for re-creating the above hardware implementation is presented in [5].

FIGURE 8.34 Workbench hardware results: (1) Input current, (2) T1, T4 switchnode voltage, (3) Secondary-side inductor current, (4) T2, T3 switch-node voltage, and (M) Transformer primary-side voltage.

8.7 HALF-BRIDGE AND PUSH-PULL CONVERTERS

Variations of full-bridge converters are shown in Figure 8.35. The half-bridge converter in Figure 8.35a consists of only two transistors but requires two split capacitors to form a DC input midpoint. It is sometimes used at slightly lower power levels compared to the full-bridge converter.

FIGURE 8.35 Half-bridge and push-pull converters.

The push-pull converter in Figure 8.35b has the advantage of having both transistors’ gates referenced to the low side of the input voltage. The penalty is in the transformer, where during the power transfer interval, only one-half of the primary winding and one-half of the secondary winding are utilized.

8.8 PRACTICAL CONSIDERATIONS

To provide electrical isolation between the input and the output, the feedback control loop should also have electrical isolation. There are several ways of providing this isolation, as discussed in Reference [6].

REFERENCES

  1. 1. “Flyback Converter Lab Manual.” https://sciamble.com/resources/pe-drives-lab/basic-pe/flyback-converter.
  2. 2. “Flyback Converter Snubber Design,” Ray Ridley. http://www.ridleyengineering.com/images/phocadownload/12_%20flyback_snubber_design.pdf.
  3. 3. “Flyback Converter Snubber Design Lab Manual.” https://sciamble.com/resources/pe-drives-lab/basic-pe/flyback-snubber-converter.
  4. 4. “Forward Converter Lab Manual.” https://sciamble.com/resources/pe-drives-lab/basic-pe/forward-converter.
  5. 5. “Full-Bridge Converter Lab Manual.” https://sciamble.com/resources/pe-drives-lab/basic-pe/full-bridge-converter.
  6. 6. N. Mohan, T.M. Undeland, and W.P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Edition (New York: John Wiley & Sons, 2003).

PROBLEMS

Flyback Converters

In Problems 8.1 through 8.4, in a flyback converter, upper V Subscript i n Baseline equals 30 normal upper V , upper N 1 equals 30 turns, and upper N 2 equals 15 turns. The self-inductance of winding 1 is 50 mu upper H , and f Subscript s Baseline equals 200 kHz . The output voltage is regulated at upper V Subscript o Baseline equals 9 normal upper V .

  • 8.1 Calculate and draw the waveforms shown in Figure 8.3 along with the ripple current in the output capacitor if the load is 30 W.
  • 8.2 For the same duty ratio as in Problem 8.1, calculate the critical power, which makes this converter operate at the border of incomplete and complete demagnetization modes.
  • 8.3 Draw the waveforms, similar to those in Problem 8.1, in Problem 8.2.
  • 8.4 Consider that a flyback converter is operating in the complete demagnetizing mode. Under this mode of operation, derive the voltage transfer ratio upper V Subscript o Baseline slash upper V Subscript i n in terms of the transformer magnetizing inductance upper L Subscript m Baseline 1 seen from the input-side winding, switching frequency f Subscript s , the duty ratio upper D , and the load resistance upper R .

Forward Converter

In Problems 8.5 through 8.7, in a forward converter, upper V Subscript i n Baseline equals 30 normal upper V , upper N 1 equals 10 turns, upper N 2 equals 5 turns, and upper N 3 equals 10 turns. The self-inductance of winding 1 is 150 mu normal upper H , and the switching frequency f Subscript s Baseline equals 250 kHz . The output voltage is regulated such that upper V Subscript o Baseline equals 5 normal upper V . The output filter inductance is 50 mu upper H , and the output load is 30 W.

  • 8.5 Calculate and draw the waveforms for v Subscript upper A , i Subscript upper L , i Subscript i n , and i Subscript upper D 3 in Figure 8.16b, where i Subscript i n is the current drawn from the input, and i Subscript upper D 3 is the current through the diode upper D 3 .
  • 8.6 If the maximum duty ratio needs to be increased to 0.7 , calculate upper N 1 slash upper N 3 .
  • 8.7 Why is diode upper D 1 necessary in Figure 8.16b?
  • 8.8 Consider that a forward converter is operating in the discontinuous-conduction mode. Under this mode of operation, derive the voltage transfer ratio upper V Subscript o Baseline slash upper V Subscript i n in terms of the circuit parameters.

Two-Switch Forward Converter

In Problems 8.9 and 8.10, in a two-switch forward converter, upper V Subscript i n Baseline equals 30 normal upper V , upper N 1 slash upper N 2 equals 2 , and the switching frequency f Subscript s Baseline equals 300 k upper H z . The output voltage is regulated such that upper V Subscript o Baseline equals 5 normal upper V . The self-inductance of winding 1 is 50 mu upper H , and the output filter inductance is 50 mu upper H .

  • 8.9 Calculate and draw waveforms if the output load is 200 W.
  • 8.10 Why is the duty ratio in this converter limited to 0.5?

Full-Bridge Converter

  • 8.11 In a full-bridge converter, shown in Figure 8.25, upper V Subscript i n Baseline equals 30 normal upper V , f Subscript s Baseline equals 300 kHz , and upper N 1 slash upper N 2 equals 4 . The output voltage is regulated by PWM such that upper V Subscript o Baseline equals 5 normal upper V . The output power upper P Subscript o Baseline equals 250 normal upper W , and the peak-peak ripple in the output inductor current is 10% of its average value at full load. Calculate the value of the filter inductor upper L . Calculate and plot all the waveforms associated with this converter. Assume the transformer ideal and the flux waveform to be symmetric with the same positive and negative peak amplitudes.

Half-Bridge Converter

  • 8.12 A regulated DC power supply similar to Problem 8.11 is implemented using a half-bridge topology, shown in Figure 8.35a, where upper N 1 slash upper N 2 equals 2 . Calculate all the waveforms associated with this converter.

Comparison of MOSFETs in Full-Bridge and Half-Bridge Converters

  • 8.13 Compare the voltage and current ratings of MOSFETs in full-bridge and half-bridge converters of Problems 8.11 and 8.12 respectively.

Push-Pull Converter

  • 8.14 A regulated DC power supply similar to Problem 8.11 is implemented using a push-pull topology shown in Figure 8.35b, where upper N 1 slash upper N 2 equals 5 . Calculate all the waveforms associated with this converter.

Simulation Problems

  • 8.15 Simulate a flyback converter with the following parameters and operating conditions: upper V Subscript i n Baseline equals 20 normal upper V , upper V Subscript o Baseline equals 5 normal upper V , upper N 1 slash upper N 2 equals 2 , upper L Subscript m Baseline 1 Baseline equals 280 mu upper H , the output capacitance upper C equals 100 mu upper F and the switching frequency f Subscript s Baseline equals 100 kHz . upper R Subscript upper L o a d Baseline equals 6 upper Omega .
    • Obtain the waveforms for i Subscript i n , i Subscript o u t and v Subscript o . What is the relationship between i Subscript i n and i Subscript o u t at the time of transition from the switch to diode, and vice versa?
    • What is the value of upper R Subscript c r i t in this converter?
    • For upper R equals 100 upper Omega , obtain the waveforms for i Subscript i n , i Subscript o u t and v Subscript o .
  • 8.16 Simulate a forward converter with the following parameters and operating conditions: upper V Subscript i n Baseline equals 20 normal upper V , upper V Subscript o Baseline equals 7.5 normal upper V , upper N 1 zero width space colon zero width space upper N 2 zero width space colon zero width space upper N 3 equals 1 , upper L Subscript m Baseline 1 Baseline equals 144 mu normal upper H , the filter inductor upper L equals 100 mu normal upper H and the output capacitance upper C equals 100 mu normal upper F , and the switching frequency f Subscript s Baseline equals 100 k upper H z . upper R Subscript upper L o a d Baseline equals 0.5 upper Omega .
    • Obtain the waveforms for i 1 , i 3 , i Subscript upper D Baseline 1 , i Subscript upper L , and v Subscript o . What is the relationship between i 1 , i 3 , and i Subscript upper D Baseline 1 at the time of transitions when the switch turns on, turns off, and the core gets demagnetized?
    • What is the voltage across the switch?
    • What is the value of upper R Subscript c r i t in this converter?
    • For upper R equals 50 upper Omega , obtain the waveforms for i 1 , i 3 , i Subscript upper D Baseline 1 , i Subscript upper L , and v Subscript o .
  • 8.17 Simulate a full-bridge converter, with a midpoint rectifier, shown in Figure 8.25, with the following parameters and operating conditions: upper V Subscript i n Baseline equals 175 normal upper V , upper V Subscript o Baseline equals 4.5 normal upper V , upper N 1 slash upper N 2 equals 25 , upper L Subscript m Baseline 1 Baseline equals 10 m upper H , the filter inductor upper L equals 7.5 mu upper H and the output capacitance upper C equals 100 mu upper F , and the switching frequency f Subscript s Baseline equals 100 k upper H z . upper R Subscript upper L o a d Baseline equals 0.5 upper Omega .
    • Obtain the waveforms for v 1 , v 2 , v prime 2 , v Subscript upper A , and v Subscript o . What are their values when all switches are off?
    • Plot the waveforms of i 1 , i Subscript upper D Baseline 1 , i Subscript upper D Baseline 2 , and i Subscript upper L defined in Figure 8.28. What are their values when all switches are off?
    • Based on the converter parameters and the operating conditions, calculate the peak-peak ripple current in i Subscript upper L and verify your answer with the simulation results.
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