3
Derating Analysis

3.1. Derating

Derating is conducted according to rules that preserve a “safety margin” (robustness) in terms of the maximum values of components guaranteed by manufacturers, in the case of operational constraints (electric overloads, disruptions, overheating, etc.) or in the case of errors or accidents while in use.

From a theoretical viewpoint, derating is defined by the following equation:

[3.1]image

Let us illustrate this by considering the example of a capacitor whose manufacturer guarantees a maximum voltage of 50 V. If, in the application concerned, a voltage of 20 V is applied, the derating will be 20/50 = 40%. In order to check if this derating is acceptable, the derating rules must be clarified.

Derating has a positive impact on the reliability of components. Consider the three types of failures mentioned in Chapter 1. It is clear that derating has little to no influence on youth failures because they are generally the result of manufacturing errors.

However, derating has some influence on catastrophic failures. It is important to recall that the latter are normally the result of accidental overloads, for example, overvoltage. If we return to the example of the capacitor mentioned above, we see that, in certain cases, derating may prevent a failure from occurring if the value of the overvoltage remains below the guaranteed maximum voltage. Similarly, a slightly undersized component can lead to premature aging. The derating applied may then push this aging beyond the point when the product integrating the component is in operation.

There are several data sources that indicate the derating rules to be applied. Some of them are listed below:

  • – Certain rules indicated by the manufacturers of components are detailed in section 3.2.
  • – Rules outlined in derating standards are listed in section 3.3.

To our knowledge, there is no justification for the rules proposed in the standards and fairly often these rules continue to be applied from one generation of products to the next, while component technology continues to evolve. Furthermore, these rules do not seem to be established according to physical laws of failures that model the component failure mechanisms. Finally, these rules are sometimes different from one standard to another, most likely due to the domain of the product application (aeronautics, rail, space, automotive, etc.).

On the basis of these findings, section 3.3 proposes a method for minimizing these defects and, above all, provides justification for the derating rules under consideration.

3.2. Rules provided by the manufacturers of components

3.2.1. CMS resistors

For this type of component, there are three parameters for which the maximum value guaranteed by the manufacturer must not be exceeded.

3.2.1.1. Dissipated power

3.2.1.1.1. Steady state

The maximum dissipated power depends on the type of enclosure and on the ambient temperature. It is generally provided in the datasheet for an ambient temperature between -55°C and +70°C. Taking the example of Vishay resistors (Vishay 2018), this power decreases linearly above +70°C until it becomes zero at a temperature around 155°C, as illustrated in the figure below (Vishay 2018).

Schematic illustration of the power derating according to the temperature of a CMS resistor.

Figure 3.1. Power derating according to the temperature of a CMS resistor

For example, a 1210 resistor can dissipate a maximum power of 500 mW, up to an ambient temperature of 70°C. The table below indicates the maximum power by the type of CMS resistor.

Table 3.1. Power dissipated by each type of resistor

Resistor typeMaximum direct power (mW)
040263
0603100
0805125
1206250
1210500
12181,000
2010500
25121,000

The temperature derating curve can be modeled as follows:

[3.2]image

For example, for a 0805 enclosure and an ambient temperature of 85°C, the following data are obtained:

image

or Pr(85°C)~103 mW

3.2.1.1.2. Transient state

For transient power dissipations, the maximum power depends on the duration of this transient state (Vishay 2018).

Schematic illustration of the power derating for a Vishay CMS resistor under single pulse state.

Figure 3.2. Power derating for a Vishay CMS resistor under single pulse state

For repetitive pulses, Figure 3.3 is obtained (Vishay 2018).

Schematic illustration of the power derating for a Vishay CMS resistor under repetitive pulses.

Figure 3.3. Power derating for a Vishay CMS resistor under repetitive pulses

For example, a 1206 resistor can dissipate a maximum power of 300 mW for 1 s.

3.2.1.2. Applied voltage

3.2.1.2.1. Steady state

Under a steady state, the voltage across resistors must not exceed the maximum value guaranteed by the manufacturer. These values are given in the following table.

Table 3.2. Voltage depending on the type of resistor

Type of resistorsMaximum voltage (V)
040250
060375
0805150
1206200
1210200
1218200
2010400
2512500
3.2.1.2.2. Transient state

In a transient state, the voltage applied may be higher than in a continuous state.

Schematic illustration of the voltage derating for a Vishay CMS resistor.

Figure 3.4. Voltage derating for a Vishay CMS resistor

For example, for a 1206 resistor, a maximum voltage of ~500 V can be applied for 10 ms.

3.2.2. Capacitors

In this section, we will discuss ceramic capacitors (types I and II), solid tantalum capacitors and electrolytic capacitors.

3.2.2.1. Ceramic capacitors

The parameter of which the maximum value should not be exceeded is the voltage across the capacitor. This voltage depends on the type of enclosure. Generally, there is no derating mentioned as a function of temperature.

However, certain manufacturers specify (but do not always guarantee) a lifetime under specific conditions (derating), as illustrated below (Murata 2020).

Graph depicts the lifetime of an MLCC (multilayer ceramic capacitor) as a function of temperature.

Figure 3.5. Lifetime of an MLCC (multilayer ceramic capacitor) as a function of temperature. For a color version of this figure, see www.iste.co.uk/bayle/maturity1.zip

NOTE.– For this manufacturer, lifetime is defined by the time elapsed until 1% of the components fail;

  • – since the three lines are parallel, the activation energy is the same for the three classes of temperature.

3.2.2.2. Tantalum capacitors

For this type of component, there are three parameters for which the maximum value guaranteed by the manufacturer should not be exceeded.

3.2.2.2.1. Direct voltage

Direct voltage is the voltage across the capacitor. It should not exceed the maximum value UR guaranteed by the manufacturer. A temperature derating is provided by the manufacturer (Firadec 2015).

Graph depicts the temperature derating of voltage across a tantalum capacitor.

Figure 3.6. Temperature derating of voltage across a tantalum capacitor

This temperature derating curve can be modeled as follows:

[3.3]image

with Tmax = 125°C and T85 = 85°C.

3.2.2.2.2. Dissipated power

This is presented in Figure 3.7 (Firadec 2015).

This temperature derating can be modeled as follows:

[3.4]image

with a = 1.1279; b = 0.086395; c = 0.018611.

Graph depicts the temperature derating of the power dissipated by a tantalum capacitor.

Figure 3.7. Temperature derating of the power dissipated by a tantalum capacitor

3.2.2.3. Electrolytic capacitors

Four stresses should be considered for electrolytic capacitors:

  • – The direct voltage applied, equal to the continuous voltage plus the positive peak voltage due to the equivalent series resistance (ESR) of the capacitor.
  • – Overvoltage for short periods, which should not exceed 1.15 times the rated voltage guaranteed by the manufacturer.
  • – The reverse voltage applied that must be below or equal to 1 V.
  • – Storage duration. There is no variation in electrical characteristics when stored for long periods of time, but leakage current may increase. This is due to chemical reactions between the alumina dielectric and the electrolyte. These reactions are reversible when the capacitor is under voltage. The manufacturer normally guarantees storage duration without reformation under well-defined temperature conditions and durations, for example, up to temperatures of 50°C under the following conditions:
    • - Voltage below 100 V ➔ 5 years.
    • - Between 100 V and 360 V ➔ 3 years.
    • - Between 360 V and 500 V ➔ 1 year.
    • - Above 500 V ➔ 6 months.
A photograph of an electrolytic capacitor.

Figure 3.8. Example of electrolytic capacitor

Similar to with tantalum capacitors, it is recommended to have voltage derating depending on the operating temperature. A 60% derating is often recommended.

NOTE.– This type of capacitor is mainly used as an energy reserve (compensating for the power supply microcuts). Due to their large overall external dimensions, a 60% derating rate, as mentioned in the “derating summary” table (Table 3.6), is not achievable at the industrial scale. Moreover, a more significant derating is often considered as going up to 90%.

3.2.3. Magnetic circuits

The parameters to be monitored are:

  • – maximum temperature;
  • – saturation current.

Generally, there are no derating rules imposed by the manufacturers.

3.2.4. Fuses

The main stresses are:

  • – the current through the fuse (breaking capacity);
  • – operating temperature;
  • – voltage across the fuse when it is “open”.

Generally, there are no derating rules imposed by the manufacturers.

3.2.5. Resonators

The main stress is the operating temperature. Generally, there are no derating rules imposed by the manufacturers.

3.2.6. Oscillators

The main stresses are:

  • – operating voltage;
  • – supply voltage.

Generally, there are no derating rules imposed by the manufacturers.

3.2.7. Photocouplers

There are many stresses to be considered:

  • – photodiode reverse voltage;
  • – photodiode reverse peak voltage;
  • – photodiode direct current;
  • – maximum power dissipated in the photodiode;
  • – breakdown voltage VCEo of the phototransistor;
  • – breakdown voltage VCBo of the phototransistor;
  • – breakdown voltage VBEo of the phototransistor;
  • – maximum power dissipated in the phototransistor;
  • – maximum operating temperature.

Generally, there are no derating rules imposed by the manufacturers.

3.2.8. Diodes

The main stresses are:

  • – maximum direct current If;
  • – maximum repetitive peak current IFRm;
  • – maximum continuous reverse voltage Vr;
  • – maximum repetitive peak reverse voltage VRRm;
  • – maximum junction temperature;
  • – maximum dissipated power.

Generally, there are no derating rules imposed by the manufacturers.

3.2.9. Zener diodes

The main stresses are:

  • – maximum dissipated power;
  • – maximum junction temperature.

Generally, there are no derating rules imposed by the manufacturers.

3.2.10. Tranzorb diodes

The main stresses are:

  • – maximum pulse power Pppm;
  • – maximum operating temperature;
  • – steady-state power.

3.2.10.1. Maximum pulse power

Maximum pulse power is derated depending on pulse duration. The curve below, derived from the manufacturer data, is defined for a non-repetitive bi-exponential wave. This is generally how lightning pulses are described in the specifications of the product concerned.

Schematic illustration of the acceptable maximum peak power in a Tranzorb diode.

Figure 3.9. Acceptable maximum peak power in a Tranzorb diode

3.2.10.2. Steady-state power

Generally, the manufacturer provides a temperature derating of the steady-state dissipated power, as illustrated below.

Schematic illustration of the temperature derating of the steady-state dissipated power.

Figure 3.10. Temperature derating of the steady-state dissipated power

3.2.10.3. Pulse power

Generally, the manufacturer provides a temperature derating of the steady-state dissipated power, as illustrated below.

Schematic illustration of the temperature derating of the dissipated pulse power.

Figure 3.11. Temperature derating of the dissipated pulse power

There is no derating for the junction temperature.

3.2.11. Low power bipolar transistors

The main stresses are:

  • – collector emitter voltage VCEo;
  • – emitter base voltage VBE;
  • – collector direct current;
  • – junction temperature.

Generally, there are no derating rules imposed by the manufacturers.

3.2.12. Power bipolar transistors

The main stresses are:

  • – collector emitter voltage VCEo;
  • – emitter base voltage VBE;
  • – permanent collector direct current;
  • – transient collector direct current;
  • – base current;
  • – junction temperature.

Generally, there are no derating rules imposed by the manufacturers.

3.2.13. Low power MOSFET transistors

The main stresses are:

  • – drain source voltage Vds;
  • – grid source voltage Vgs;
  • – grid drain voltage Vgd;
  • – steady-state direct current ID;
  • – pulsed state direct current ID;
  • – maximum junction temperature;
  • – maximum dissipated power.

Generally, there are no derating rules imposed by the manufacturers.

3.2.14. High power MOSFET transistors

The main stresses are:

  • – drain source voltage Vds;
  • – grid source voltage Vgs;
  • – grid drain voltage Vgd;
  • – steady-state direct current ID;
  • – pulsed state direct current ID;
  • – junction temperature;
  • – steady-state dissipated power.

There is generally a derating of the dissipated power depending on the case temperature Tc, as illustrated below.

Graph depicts the power derating of a power MOSFET.

Figure 3.12. Power derating of a power MOSFET

3.2.15. Integrated circuits

The main stresses are:

  • – junction temperature;
  • – supply voltage.

Generally, there are no derating rules imposed by the manufacturers.

3.3. Reference-based approach

There are no standards defining the maximum load rate per family of components; however, methodology guides do exist. Load rates often differ from one guide to another, and sometimes the stress parameters of a family of components are not all identical. Moreover, most of the time, these derating rules are not justified and therefore not readily applicable to a given application. Our first approach was to list all the derating values obtained and to thus draw a common basis, as shown by the following table.

Table 3.3. Summary of derating rules according to the literature

Family of componentsPhysical contributionDerating rules
ResistorsVoltage80%
Power60%
CapacitorsVoltage60%
ConnectorsCurrent60%
FusesCurrent50%
InductancesCurrent60%
Hotspot temperature60%
TransformersCurrent60%
Hotspot temperature60%
Voltage60%
DiodesReverse voltage75%
Junction temperature70%
OptocouplersVoltage75%
Reverse voltage75%
Junction temperature70%
Bipolar transistorsVoltage Vce75%
Voltage Vbe75%
Junction temperature70%
MOSFET transistorsVoltage Vds75%
Voltage Vgs75%
Junction temperature70%
Analog circuitsSupply voltage75%
Junction temperature80%
Logic circuitsSupply voltage75%
Junction temperature80%

NOTE.– The rates in the table are an average of the rates issued from the following guides:

  • – MIL-HDBK-338B (1988);
  • – NAV-SEA (1991);
  • – MIL-STD-975 NASA (2003).

3.4. Creation of derating rules

The derating rules proposed in this book were established in order to provide a justification for the rules generally used in the design of electronic circuits. This analysis relies on the physics of the failure of components.

It therefore seems appropriate to take into account the reliability level of the component, depending on the physical contribution involved in these derating rules. More specifically, the focus will be on the sensitivity of component reliability with respect to the empirical acceleration law modeling the influence of the considered physical contribution.

As already noted, the derating rate is defined as the ratio of the value applied to the component and the maximum value guaranteed by the manufacturer of the component. It therefore ranges between 0 and 100%. It therefore seems relevant to consider that the maximum acceptable derating DR_Max is applicable to the family of components most sensitive to the physical contribution being considered.

Moreover, it is appropriate to take a minimal derating rate DR_Min to avoid needless overdesign. This derating rate will be assigned to the family of components least sensitive to the applied physical contribution. The value of this margin depends on the type of application (consumer products, aeronautics, automotive and aerospace industries, etc.).

Schematic illustration of the compromise between reliability and overdesign.

Figure 3.13. Compromise between reliability and overdesign. For a color version of this figure, see www.iste.co.uk/bayle/maturity1.zip

The value of these derating rates is the result of a compromise between “overdesign” and a good level of reliability, as illustrated in the figure above.

This qualitative analysis must be followed by a quantitative approach to building these rules. This involves using the sensitivity of a function of a given parameter as the ratio between the relative variation of the function and the relative variation of the considered variable. The sensitivity of the function “f” with respect to the variable x is given by:

[3.5]image

An equivalent form of the sensitivity of a function is generally expressed as:

[3.6]image

For the derating, the function “f” is considered as the acceleration factor of the underlying physical law governing the failure. As for the parameter “xp”, the characteristic parameter of this law is considered (e.g. the activation energy for the temperature). The following derating rule “DR” is then proposed:

[3.7]image

where “a” and “b” are two parameters to be calculated. The problem is that the parameter “p” can take various values depending on the type of component and therefore on the failure mechanism being considered. Therefore, two extreme cases must be considered, namely the minimum value p_min and the maximum value p_max. The previous qualitative rules lead to the following product of equations:

[3.8a]image
[3.8b]image

The values of DR_Max and DR_Min correspond, respectively, to the minimal and maximum values of the derating rules. The method proposed here is first illustrated in Figure 3.14.

A compromise between the robustness margin and overdesign can lead to the following rules:

  • – DR_Max = 90%;
  • – DR_Min = 50%.
Schematic illustration of the derating rules.

Figure 3.14. Illustration of derating rules. For a color version of this figure, see www.iste.co.uk/bayle/maturity1.zip

The next step is then to determine the values of the parameters DR_Max and DR_Min. These values depend on the field of application and should therefore be estimated by those responsible for derating studies in the company concerned. For example, the MIL-HDBK-338B handbook (MIL 1998) provides similar information in the following table.

PART TYPEDERATING PARAMETERDERATING LEVEL
I
(Space)
II
(Airborne)
III
(Ground)

TRANSISTORS

  • Thyristors
    (SCR/TRIAC)
On-State Current (It – % Rated)50%70%70%
Off-State Voltage (VDM – % Rated)70%70%70%
Max T (°C)95°105°125°
  • Field Effect
Power Dissipation (% Rated)50%60%70%
reakdown Voltage (% Rated)60%70%70%
Max T (°C)95°105º125°
  • Bipolar
Power Dissipation (% Rated)50%60%70%
Breakdown Voltage (% Rated)60%70%70%
Max T (°C)95°105°125°

For certain applications, such as those in the aerospace sector, where the stakes of reliability, safety, etc. are very high, the following rules can be considered:

  • – DR_Max = 80%;
  • – DR_Min = 30%.

The next step is to calculate parameters a and b satisfying the previous product of equations, depending on the physical law of the failure. The result is then:

[3.9]image
[3.10]image

PROOF.–

The previous product of equations leads to:

image

The ratio of the two equations term by term leads to eliminating parameter a. Parameter b can then be calculated as follows:

image

The natural logarithm of the previous equation gives:

image

or finally

image

Inserting the value of b in the first equation, the value of parameter “a” is obtained.

image

or finally

image

End

The derating rules are then written for constant temperature as follows:

[3.11]image

PROOF.–

As already noted: image therefore: image

Hence:

image

End

3.4.1. Rules for constant temperature

The failure mechanisms accelerated by temperature are generally governed by the Arrhenius law (Arrhenius 1889) whose acceleration factor is given by:

[3.12]image

NOTE.– This is an acceleration with respect to the reference temperature θo.

  • – Here, T designates the junction temperature θj for the active components and the hotspot temperature Th for the passive components.

Let us then study the sensitivity of this acceleration factor with respect to the activation energy Ea. This can be written as:

image

or

image

Consequently, parameters “a” and “b” are written as:

[3.13a]image
[3.13b]image

The derating rules can then be written for the constant temperature as:

[3.14]image

PROOF.–

It is known that: image and that image

Combining these two equations leads to:

image

or finally:

image

End

Based on the FIDES guide for predictive reliability (FIDES 2009), the following table presents activation energy as a function of component type.

Table 3.4. Activation energy for various types of components

Types of componentsEa (eV)
Ceramic capacitors0.1
Electrolytic capacitors0.4
Tantalum capacitors0.15
Plastic capacitors0.25
CMS resistors0.15
Fuses0.15
Magnetic components0.15
Diodes0.7
Transistors0.7
Integrated circuits0.7
LED0.6
Optocouplers0.4
ASIC0.7
Relay0.25
Interrupters and switches0.25
Connectors0.1
Hybrid0.7
RF and HF Circuits1.5
LCL STN screen0.6
LCD TFT screen0.5
Lithium battery0.4

Therefore, Ea_Min = 0.1 eV and Ea_Max = 0.7eV. Using the proposed derating rules, the following derating rates are obtained.

Table 3.5. Temperature derating rate

Types of componentsDerating
Ceramic capacitors50%
Connectors50%
Tantalum capacitors54.6%
CMS resistors54.6%
Fuses54.6%
Magnetic components54.6%
Plastic capacitors61%
Relay61%
Interrupters and switches61%
Electrolytic capacitors67.6%
Optocouplers67.6%
Lithium battery67.6%
LCD TFT screen70.9%
LED73.8%
LCL STN screen73.8%
Diodes76.3%
Transistors76.3%
Integrated circuits76.3%
ASIC76.3%
Hybrid76.3%
RF and HF circuits90.0%

This can be illustrated by Figure 3.15.

To illustrate the method, the acceleration factor can be calculated with respect to a maximum temperature of 125°C, and to the derated temperature, as illustrated in Figure 3.16.

Graph depicts the derating rate depending on activation energy.

Figure 3.15. Derating rate depending on activation energy. For a color version of this figure, see www.iste.co.uk/bayle/maturity1.zip

A bar graph depicts the acceleration factor depending on the derated temperature.

Figure 3.16. Acceleration factor depending on the derated temperature. For a color version of this figure, see www.iste.co.uk/bayle/maturity1.zip

It can be noted that the acceleration factors are relatively homogeneous.

3.4.2. Rule for voltage

Failure mechanisms accelerated by voltage are generally governed by a power law whose acceleration factor is given by:

[3.15]image

Let us study the sensitivity of this acceleration factor with respect to parameter ∈. The following relation can be written:

image

or

image

This leads to:

[3.16]image

PROOF.–

It is known that: image and that image

Combining these two equations leads to:

image

or

image

End

3.5. Summary

The proposed method for the estimation of derating rules relies on the physical laws of failure. Unfortunately, the parameters of a component that are guaranteed by the manufacturer cannot all be modeled by the laws of physics. Therefore, in order to have a summary of the various rules proposed (by the manufacturer, by standards and by the proposed method), only the parameters meeting this constraint are listed in the following table.

Table 3.6. Summary of derating rules

Family of componentsPhysical contributionDerating referencesProposed derating
Chip resistorsHotspot temperature80%54.6%
Ceramic capacitorsHotspot temperature60%50%
Direct voltage60%71.7%
Electrolytic capacitorsHotspot temperature60%67.6%
Direct voltage90%71.7%
Tantalum capacitorsHotspot temperature60%54.6%
Direct voltage60%71.7%
TransformersHotspot temperature60%54.6%
InductancesHotspot temperature60%54.6%
ConnectorsHotspot temperatureTmax – 25%50%
FusesHotspot temperature50%54.6%
DiodesJunction temperature70%76.3%
OptocouplersJunction temperature70%67.6%
Bipolar transistorsJunction temperature70%76.3%
Analog circuitsJunction temperature80%76.3%
Logic circuitsJunction temperature80%76.3%
RF and HF circuitsJunction temperature80%90%
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