Vive la differential

The primary motivation for using a differential pair as the input stage of an amplifier is usually its low DC offset. Apart from its inherently lower offset due to the cancellation of the V_be voltages, it has the added advantage that its standing current does not have to flow through the feedback network. However a second powerful reason is that its linearity is far superior to single-transistor input stages. Figure 23.1 shows three versions, in increasing order of sophistication. The resistor-tail version in Figure 23.1(a) has poor CMRR and PSRR and is generally a false economy; it will not be further considered. The mirrored version in Figure 23.1(c) has the best balance, as well as twice the transconductance of that in Figure 23.1(b).

Figure 23.1 Three versions of an input pair: (a) Simple tail resistor; (b) Tail currentsource; (c) With collector current-mirror to give inherently good lc balance.

Intuitively, the input stage should generate a minimal proportion of the overall distortion because the voltage signals it handles are very small, appearing as they do upstream of the VAS that provides almost all the voltage gain. However, above the first pole frequency P1, the current required to drive C_dom dominates the proceedings, and this remorselessly doubles with each octave, thus:

For example the current required at 100 W, 8 Ω and 20 kHz, with a 100 pF C_dom is 0.5 mA peak, which may be a large proportion of the input standing current, and so the linearity of transconductance for large current excursions will be of the first importance if we want low distortion at high frequencies.

Figure 23.2, curve A, shows the distortion plot for a model amplifier (at +16 dBu output) designed so that the distortion from all other sources is negligible compared with that from the carefully balanced input stage. With a small-signal class A stage this essentially reduces to making sure that the VAS is properly linearised. Plots are shown for both 80 kHz and 500 kHz measurement bandwidths to show both HF behaviour and LF distortion. It demonstrates that the distortion is below the noise floor until 10 kHz, when it emerges and heaves upwards at a precipitous 18 dB/octave.

Figure 23.2 Distortion performance of model amplifier differential pair at A compared with singleton input at B. The singleton generates copious second-harmonic distortion.

This rapid increase is due to the input stage signal current doubling with every octave to drive C_dom; this means that the associated third harmonic distortion will quadruple with every octave increase. Simultaneously the overall NFB available to linearise this distortion is falling at 6 dB/octave since we are almost certainly above the dominant pole frequency P1. The combined effect is an 18 dB/octave rise. If the VAS or the output stage were generating distortion, this would be rising at only 6 dB/octave and would look quite different on the plot.

This form of non-linearity, which depends on the rate-of-change of the output voltage, is the nearest thing to what we normally call TID, an acronym that now seems to be falling out of fashion. Slew-induced-distortion SID is a better description of the effect.

If the input pair is not accurately balanced, then the situation is more complex. Second as well as third harmonic distortion is now generated, and by the same reasoning this has a slope of closer to 12 dB/octave. This vital point requires examination.

Input stage in isolation

The use of a single input transistor (Figure 23.3(a)) sometimes seems attractive, where the amplifier is capacitor-coupled or has a separate DC servo; it at least promises strict economy. However, the snag is that this singleton configuration has no way to cancel the second-harmonics generated by its strongly-curved exponential V_in / I_out characteristic. [1] The result is shown in Figure 23.2 curve B, where the distortion is much higher, though rising at the slower rate of 12 dB/octave.

Although the slope of the distortion plot for the whole amplifier tells much, measurement of input-stage nonlinearity in isolation tells more. This may be done with the test circuit of Figure 23.4. The op-amp uses shunt feedback to generate an appropriate AC virtual earth at the input-pair output. Note that this current-to-voltage conversion op-amp requires a third −30 V rail to allow the i/p pair collectors to work at a realistic DC voltage—i.e. about one diode’s-worth above the −15 V rail. R_f can be scaled to stop op-amp clipping without effect to the input stage. The DC balance of the pair may be manipulated by VR₁: it is instructive to see the THD residual diminish as balance is approached until, at its minimum amplitude, it is almost pure third harmonic.

The differential pair has the great advantage that its transfer characteristic is mathematically highly predictable. [2] The output current is related to the differential input voltage V_in by:

where V_t is the usual ‘thermal voltage’ of about 26 mV at 25 °C and I_e the tail current.

This equation demonstrates that the transconductance, g_m, is highest at V in = 0 when the two collector currents are equal, and that that the value of this maximum is proportional to the tail current, I_e. Note also that beta does not figure in the equation, and that the performance of the input pair is not significantly affected by transistor type.

Figure 23.5(a) shows the linearising effect of local feedback or degeneration on the voltage-in/current-out law. Figure 23.5(b) plots transconductance against input

Figure 23.3 Singleton and differential pair input stages showing typical DC conditions. The large DC offset of the singleton(2.8 V) is largely due to all the stage current flowing through the feedback resistor RF1.

Figure 23.4 Test circuit for examining input stage distortion in isolation. The shunt-feedback opamp is biased to provide the right DC conditions for Tr2.

Figure 23.5 Effect of degeneration on input pair V/l law, showing how transconductance is sacrificed in favour of linearity (SPICE simulation).

voltage and demonstrates a reduced peak transconductance value but with the curve made flatter and more linear over a wider operating range. Adding emitter degeneration markedly improves input stage linearity at the expense of noise performance. Overall amplifier feedback factor is also reduced since the HF closed-loop gain is determined solely by the input transconductance and the value of the dominant-pole capacitor.

Input stage balance

One relatively unknown property of the differential pair in power amplifiers is its sensitivity to exact DC balance. Minor deviations from equality of I_c in the pair seriously upset the second-harmonic cancellation by moving the operating point from A in Figure 23.5(a) to B. Since the average slope of the characteristic is greatest at A, serious imbalance also reduces the open-loop gain. The effect of small amounts of imbalance is shown in Figure 23.6 and Table 23.1: for an input of −45 dBu a collector current imbalance of only 2% increases THD from0.10% to 0.16%; for 10% imbalance this deteriorates to0.55%. Unsurprisingly, imbalance in the other direction (I_c1 > I c2) gives similar results.

This gives insight [4] into the complex changes that accompany the simple changing the value of R₂. For example, we might design an input stage as per Figure 23.7(a), where R₁ has been selected as 1 kΩ by uninspired guesswork and R₂ made highish at 10 kΩ in a plausible but misguided attempt to maximise o/l gain by minimising loading on Tr 1 collector. R₃ is also made 10 kΩ to give the stage a notional ‘balance’, though unhappily this is a visual rather than electrical balance. The asymmetry is shown in the resulting collector currents: this design will generate avoidable second harmonic distortion, displayed in the 10 kΩ curve of Figure 23.8.

However, recognising the importance of DC balancing, the circuit can be rethought as per Figure 23.7(b). If the collector currents are to be roughly balanced, then R₂ must be about 2 × R₁, as both have about 0.6 V across them. The effect of this change is shown in the 2.2 kΩ curve of Figure 23.8. The improvement is accentuated as the o/l gain has also increased by some 7 dB, though this has only a minor effect on the closed-loop linearity compared with the improved balance of the input pair. R₃ has been excised as it contributes little to stage balance.

The joy of current mirrors

While the input pair can be approximately balanced by the correct choice of R₁ and R₂, other circuit tolerances are significant and Figure 23.6 shows that balance is critical, needing to be accurate to at least 1% for optimal linearity. The standard current-mirror configuration

Figure 23.6 Effect of collector-current imbalance on an isolated input pair; the second harmonic rises well above the level of the third if the pair moves away from balance by as little as 2%.

Figure 23.7 Improvements to the input pair: (a) Poorly designed version; (b) Better … partial balance by correct choice of R2.(c) Best … near-perfect Ic balance enforced by mirror.

Figure 23.8 Distortion of model amplifier: (a) Unbalanced with R2 = 10 kΩ; (b) Partially balanced with R = 2.2 kΩ; (c) Accurately balanced by current-mirror.

shown in Figure 23.7(c) forces the two collector currents very close to equality, giving proper cancellation of second harmonic. The resulting improvement shows up in the current-mirror curve of Figure 23.8. There is also less DC offset due to unequal base currents flowing through input and feedback resistances; we often find that a power-amplifier improvement gives at least two separate benefits. This simple mirror has its own residual base current errors but they are not large enough to affect distortion.

The hyperbolic tangent law also holds for the mirrored pair, [3] though the output current swing is twice as great for the same input voltage as the resistor-loaded version. This doubled output occurs at the same distortion level as for the single-ended version, as linearity depends on the input voltage, which has not changed. Alternatively, to get the same output we can halve the input which, with a properly balanced pair generating only third harmonic, will produce just one-quarter the distortion, a pleasing result.

A low cost mirror made from discrete transistors forgoes the V_be matching available to IC designers, and so requires its own emitter degeneration for good current-matching. A voltage drop across the mirror emitter resistors in the range 30–60 mV will be enough to make the effect of V be tolerances on distortion negligible If degeneration is omitted, there is significant variation in HF distortion performance with different specimens of the same transistor type. Adding a current mirror to a reasonably well balanced input stage will increase the total o/l gain by at least 6 dB, and by up to 15 dB if the stage was previously poorly balanced. This needs to be taken into account in setting the compensation. Another happy consequence is that the slew-rate will be roughly doubled, as the input stage can now source and sink current into C_dom without wasting it in a collector load. If C_dom is 100 pF, the slewrate of Figure 23.7(b) is about 2.8 V/μs up and down, while Figure 23.7(c) gives5.6 V/μs. The unbalanced pair in Figure 23.7(a) displays further vices by giving 0.7 V/μs positive-going and 5 V/μs negative-going.

Improving linearity

Now that the input pair has been fitted with a mirror, we may still feel that the HF distortion needs further reduction; after all, once it emerges from the noise floor it goes up eight times with each doubling of frequency, and so it is well worth pushing the turn point as far as possible up the frequency range. The input pair shown has a conventional value of tail-current. We have seen that the stage transconductance increases with I c, and so it is possible to increase the g_m by increasing the tail-current, and then return it to its previous value (otherwise C dom would have to be increased proportionately to maintain stability margins) by applying local NFB in the form of emitter-degeneration resistors. This ruse powerfully improves input linearity despite its rather unsettling flavour of something-for-nothing. The transistor nonlinearity can here be regarded as an internal nonlinear emitter resistance r_e, and what we have done is to reduce the value of this (by increasing I_c) and replace the missing part of it with a linear external resistor, R_e.

For a single device, the value of r_e can be approximated by:

Our original stage at Figure 23.9(a) has a perdevice I_c of 600 μA, giving a differential (i.e. mirrored) g_m of 23 mA/V and r_e = 41.6 Ω. The improved version at Figure 23.9(b) has I c = 1.35 mA and so r_e = 18.6 Ω. Emitter degeneration resistors of 22 Ω are required to reduce the g_m back to its original value, as 18.6 + 22 = 41.6. The distortion measured by the circuit of Figure 23.4 for a −40 dBu input voltage is reduced from 0.32% to0.032%, which is an extremely valuable linearisation, and will translate into a distortion reduction at HF of about five times for a complete amplifier. For reasons that will emerge later the full advantage is rarely gained. The distortion remains a visually pure third harmonic so long as the input pair remains balanced. Clearly this sort of thing can only be pushed so far, as the reciprocal-law reduction of re is limited by practical values of tail current. A name for this technique seems to be lacking; ‘constant- g_m degeneration’ is descriptive but rather a mouthful.

Since the standing current is roughly doubled so has the slew rate: 10 V/μs to 20 V/μs. Once again we gain two benefits for the price of one modification.

For still better linearity, various techniques exist. When circuit linearity needs a lift, it is often a good approach to increase the local feedback factor, because if this operates in a tight local NFB loop there is often little effect on the overall global-loop stability. A reliable method is to replace the input transistors with complementary-feedback (CFP or Sziklai) pairs, as shown in the stage of Figure 23.10(a). If an isolated input stage is measured using the test circuit of Figure 23.4, the constant g_m degenerated version shown in Figure 23.9(b) yields 0.35% third-harmonic distortion for a −30 dBu input voltage, while the CFP version gives 0.045%. Note that the input level here is 10 dB up on the previous example to get well clear of the noise floor. When this stage is put to work in a model amplifier, the third-harmonic distortion at a given frequency is roughly halved, assuming other distortion sources have been appropriately minimised. However, given the steep slope of input stage

Figure 23.9 Input pairs before and after constant-gm degeneration showing how to double stage current while keeping transconductance constant: distortion is reduced by about ten times.

Figure 23.10 Some enhanced differential pairs: (a) The complementary feedback pair; (b) The cross-quad; (c) The cascomp.

Figure 23.11 Whole-amplifier THD with normal and CFP input stages; input stage distortion only shows above noise floor at 20 kHz, so improvement occurs above this frequency. The noise floor appears high as the measurement bandwidth is 500 kHz.

distortion, this extends the low distortion regime up in frequency by less than an octave. See Figure 23.11.

The CFP circuit does require a compromise on the value of R_c, which sets the proportion of the standing current that goes through the NPN and PNP devices on each side of the stage. In general, a higher value of R_c gives better linearity, but more noise, due to the lower I_c in the NPN devices that are the inputs of the input stage, as it were, causing them to match less well the relatively low source resistances. 2.2 kΩ is a reasonable compromise.

Other elaborations of the basic input pair are possible. Power amp design can live with a restricted common-mode range in the input stage that would be unusable in an op-amp, and this gives the designer great scope. Complexity in itself is not a serious disadvantage as the small-signal stages of the typical amplifier are of almost negligible cost compared with mains transformers, heat-sinks, etc.

Two established methods to produce a linear input transconductance stage (often referred to in opamp literature simply as a transconductor) are the cross-quad [5] and the cascomp [6] configurations. The cross-quad (Figure 23.10(b)) gives a useful reduction in input distortion when operated in isolation but is hard to incorporate in a practical amplifier because it relies on very low source resistance to tame the negative conductances inherent in its operation. The cross-quad works by imposing the input voltage to each half across two base-emitter junctions in series, one in each arm of the circuit. In theory the errors due to non-linear r_e of the transistors is divided by beta, but in practice things seem less rosy.

The cascomp (Figure 23.10(c)) does not have this snag, though it is significantly more complex to design. Tr₂, Tr₃ are the main input pair as before, delivering current through cascode transistors Tr 4, Tr₅ (this does not in itself affect linearity) which, since they carry almost the same current as Tr₂, Tr₃ duplicate the input V_bev errors at their emitters. This is sensed by error diff-amp Tr 6, Tr₇ whose output currents are summed with the main output in the correct phase for error-correction. By careful optimisation of the (many) circuit variables, distortion at −30 dBu input can be reduced to about 0.016% with the circuit values shown. Sadly, this effort provides very little further improvement in whole-amplifier HF distortion over the simpler CFP input, as other distortion mechanisms are coming into play—for instance the finite ability of the VAS to source current into the other end of C_dom.

Power amplifiers with pretensions to sophistication sometimes add cascoding to the standard input differential amplifier. This does nothing to improve input stage linearity as there is no appreciable voltage swing on the input collectors; its main advantage is reduction of the high V_ce that the input devices work at. This allows cooler running, and therefore possibly improved thermal balance; a V ce of 5 V usually works well. Isolating the input collector capacitance from the VAS input often allows C_dom to be somewhat reduced for the same stability margins, but it is doubtful if the advantages really outweigh the increased complexity.

Other considerations

As might be expected, the noise performance of a power amplifier is set by the input stage, and so it is briefly examined here. Power amp noise is not an irrelevance: a powerful amplifier is bound to have a reasonably high voltage gain and this can easily result in a faint but irritating hiss from efficient loudspeakers even when the volume control is fully retarded. In the design being evolved here the EIN has been measured at −120 dBu, which is only 7 or 8 dB inferior to a first-class microphone preamplifier. The inferiority is largely due to the source resistances seen by the input devices being higher than the usual 150 Ω microphone impedance. For example, halving the impedance of the feedback network shown in ptl (22 kΩ and 1 kΩ) reduces the EIN by approx 2 dB.

Slew rate is another parameter usually set by the input stage, and has a close association with HF distortion. The amplifier slew rate is proportional to the input’s maximum-current capability, most circuit configurations being limited to switching the whole of the tail current to one side or the other. The usual differential pair can only manage half of this, as with the output slewing negatively half the tail-current is wasted in the input collector load R₂. The addition of an input current-mirror, as advocated, will double the slew rate in both directions. With a tail current of 1.2 mA, the slew rate is improved from about 5 V/μs to 10 V/μs. (for C_dom = 100 pF) The constant g_m degeneration method of linearity enhancement in Figure 23.9 further increases it to 20 V/μs. The mathematics of voltage-slewing is simple:

Slew rate = I/C dom in V/μs for maximum I in μΑ, C_dom in pF.

The maximum output frequency for a given slew rate and voltage is:

Likewise, a sinewave of given amplitude has a maximum slew-rate (at zero-crossing) of:

So, for example, with a slew rate of 20 V/μs the maximum frequency at which 35 V r.m.s. can be sustained is 64 kHz, and if C_dom is 100 pF, then the input stage must be able to source and sink 2 mA peak.

A vital point is that the current flowing through C_dom must be sourced/sunk by the VAS as well as the input pair. Sinking is usually no problem, as the VAS common-emitter transistor can be turned on as hard as required. The current source or bootstrap at the VAS collector will however have a limited sourcing ability, and this can often turn out to be an unexpected limitation on the positive-going slew rate.