The designer may be wanting 2 mV pk–pk ac signals at the input to be amplified up to 2-V pk–pk signals at the output. If the dc conditions are taken for granted then you might expect at least 20 dB of headroom: ±1 V output swing with ±10 V available. But, with a worst-case V_OS device virtually no headroom will be available for one polarity of input and 20 V will be available for the other. Unipolar (asymmetrical) clipping will result. The worst outcome is if the design is checked on the bench with a device, which has a much-better-than-worst-case offset, say 1 mV. Then the dc output voltage will only be 1 V, and virtually all the expected headroom will be available. If this design is let through to production then the scene is set for unexpected customer complaints of distortion! An additional problem presents itself if the output coupling capacitor is polarized: the dc output voltage can assume either polarity depending on the polarity of the offset. If this is not recognized it can lead to early failure of the capacitor in some production units.

The solutions are plentiful. The easiest is to change the feedback to ac coupling, which gives a dc gain of unity so that the output dc voltage offset is the same as the input offset (Fig. 5.2). The inverting configuration is simpler in this respect. The difficulty with this solution is that the time constant R_f × C can be inordinately long, leading to power-on delays of several seconds.

Offset voltage drift is closely related to initial offset voltage and is a measure of how V_OS changes with temperature and time. Most manufacturers will specify drift with temperature, but only those offering precision devices will specify drift over time. Present technology for standard devices allows temperature coefficients of between 5 and 40 μV/°C, with 10 μV/°C being typical. For bipolar inputs, the magnitude of drift is directly related to the initial offset at room temperature. A rule of thumb is 3.3 μV/°C for each millivolt of initial offset. This drift has to be added to the worst-case offset voltage when calculating offset effects and can be significant when operating over a wide temperature range.

Microprocessor control has allowed new analog techniques to be developed and one of these is the nulling of input amplifier offsets, as in Fig. 5.3. With this technique the initial circuit offsets can be calibrated out of the system by applying a zero input, storing the resultant input value (which is the sum of the offsets) in nonvolatile memory and subsequently subtracting this from real-time input values. With this technique, only offset drifts, not absolute offset values, are important. Alternatively, for the cost of a few extra components—analog switches and interfacing—the nulling can be done repetitively in real time, and even the drift can be subtracted out. (This is the microprocessor equivalent of the chopper op-amps discussed earlier.)

Input bias currents of bipolar devices range from a few microamps down to a few nanoamps, with most industry-standard devices offering better than 0.5 μA. There is a well-established trade-off between bias current and speed; high speeds require higher first-stage collector currents to charge the internal node capacitance faster, which in turn requires higher bias currents. Precision bipolar op-amps achieve less than 20 nA while some devices using current nulling techniques can boast picoamp levels. Junction field-effect transistor (JFET) and CMOS devices routinely achieve input currents of a few picoamps or tens of picoamps at 25°C, but because this is almost entirely reverse-bias junction leakage it increases exponentially with temperature (see Section 4.1.3). Industry-standard JFET op-amps are therefore no better than bipolar ones at high temperatures, though precision JFET and CMOS still show nanoamp levels at the 125°C extreme. Note that even the 25°C figure for JFETs can be misleading, because it is quoted at 25°C junction temperature: many JFET op-amps take a fairly high supply current and warm up significantly in operation, so that the junction temperature is actually several degrees or tens of degrees higher than ambient.

Of more importance is the bias current's contribution to offsets. The bias current flowing in the source resistance R_S at each terminal generates a voltage in series with the input; if the bias currents and source resistances were equal, the voltages would cancel out and no extra offset would be added (Fig. 5.4).

An ideal op-amp will not produce an output when both inputs, ignoring offsets, are at the same (common mode) potential throughout the input range. In practice, gain differences between the two inputs, and variations in offset with common-mode voltage, combine to produce an error at the output as the common-mode voltage varies. This error is referred to the input (that is, divided by the gain) to produce an equivalent input common-mode error voltage. The ratio of this voltage to the actual common-mode input voltage is the CMRR, usually expressed in decibels. For example, a CMRR of 80 dB would give an equivalent input voltage error of 100 μV for every 1 V change at both + and − inputs together. The inverting amplifier configuration is inherently immune to common-mode errors since the inputs stay at a constant level, whereas the noninverting and differential circuits are susceptible.

PSRR is similar to CMRR but relates to error voltages referred to the input as a result of changes in the power rail voltages. As before, a PSRR of 80 dB with a rail voltage change of 1 V would result in an equivalent input error of 100 μV. Again, PSRR worsens with increasing frequency and may be only 20–30 dB in the tens-to-hundreds of kilohertz range, so that high-frequency noise on the power rails is easily reflected on the output. There may also be a difference of several tens of decibels between the PSRRs of the positive and negative supply rails, due to the difference in internal biasing arrangements. For this reason, it is unwise to expect equal but antiphase power rail signals, such as mains frequency ripple, to cancel each other out.

The common-mode operating input voltage is normally different from the absolute maximum input voltage range, which is usually equal to the supply voltage. If you exceed the maximum input voltage without current limiting then you are likely to destroy the device; this can quite easily happen inadvertently, apart from circuits connected to external inputs, if for instance a large-value capacitor is discharged directly through the input. Even if current is limited to a safe value, overvoltages on the input can lead to unpredictable behavior. Latch-up, where the IC locks itself into a quasistable state and may draw large currents from the power supply, leading to burnout, is one possibility. Another is that the sign of the inputs may change, so that the inverting input suddenly becomes noninverting. (This was a well-known fault on early devices such as the 709.) These problems most frequently arise with capacitive coupling direct to one or other input, or when power rails to different parts of the circuit are turned on or off at different times. The safe way to guard against them is to include a reasonable amount of resistance at each input, directly in series with the input pin.

It should be obvious that the output cannot swing to a greater value than either power rail. Unfortunately it is often easy to overlook this fact, particularly as the power connections are frequently omitted from circuit diagrams, and with different quad op-amp packages being supplied from different rails it is hard to keep track of which device is powered from what voltage. More seriously, with unregulated supplies the actual voltage may be noticeably less than the nominal. The required output must be calculated for the worst-case supply voltage.

Output also depends on the circuit load impedance. This may again seem obvious, but there is an erroneous belief that because feedback reduces the output impedance of an op-amp in proportion to the ratio of open- to closed-loop gains, it should be capable of driving very low–load resistors. Well, of course, to an extent it is, but Ohm's law is not so easily flouted, and a low output resistance can only be driven to a low output voltage swing, depending entirely on the current drive capability of the output stage. The maximum output current that can be obtained from most devices is limited by package dissipation considerations to about ±10 mA. In some cases, the output current spec is given as a particular output voltage swing when driving a stated value of load, typically 2–10 kΩ. The “rail-to-rail” op-amps with CMOS output will in fact only give a full rail-to-rail swing if they are driven into an open circuit; any output load, including, of course, the feedback resistor, reduces the total available swing in proportion to the ratio of output resistance to load resistance (Fig. 5.7).

The exact value of the price is measured by the slew rate. From the above circuit, you can see that the rate of change of V_out is determined entirely by i_out1 and C_c (remember dV/dt = I/C). As an example, the 741's input section current source can supply 20 μA and its compensation capacitor is 30 pF, so its maximum slew rate is 0.67 V/μs. Op-amp designers have the freedom to set both these parameters within certain limits, and this is what distinguishes a fast, high supply–current device from a slow, low supply–current one. “Programmable” devices such as the LM4250 or LM346 make the trade-off more obvious by putting it in the circuit designer's hands.

Slew-rate limitations on dV_out/dt can be equated to the maximum rate of change of a sine wave output. The time derivative of a sine wave is

where ω = 2πf.

Operating an op-amp above the slew-rate limit will cause slewing distortion on the output. In the limit the output will be a triangle wave (Fig. 5.10) as it alternately switches between positive and negative slewing, which will decrease in amplitude as the frequency is raised further. If the positive and negative slew rates differ, there will be asymmetrical distortion on the output. This can generate an unexpected effect equivalent to a dc offset voltage, due to rectification of the asymmetrical feedback waveform or overloading of the input stage by large distortion signals at the summing junction. Also, slewing is not always linear from start to finish but may exhibit a fast rise for the first part of the change followed by a reversion to the expected rate for the latter part.

Ground loops or other types of incorrect grounding cause coupling from output back to input of the circuit via a common impedance in its grounded segment. This effect has been covered in Chapter 1, but the circuit topology is repeated here, in Fig. 5.12. If the resulting feedback sense gives an output component in-phase with the input then positive feedback occurs, and if this overrides the intended negative feedback you will have oscillation. The frequency will depend on the phase contribution of the common impedance, which will normally be inductive and can vary over a wide range.

Power supplies should be properly bypassed to avoid similar coupling through the common-mode power supply impedance. PSRR falls with frequency, and typical 0.01–0.1 μF decoupling capacitors may resonate with the parasitic inductance of long power leads in the mehahertz region, so these problems usually show up in the 1–10 MHz range. Using 1–10 μF tantalum capacitors for power rail bypassing will drop the resonant frequency and stray circuit Q to the level at which problems are unlikely (compare Fig. 3.19 for capacitor resonances).

Localized output-stage instability is most common when the device is driving a capacitive load. This can create output oscillations in the high-MHz range, which are generally cured by good power rail decoupling close to the power supply pins, with the decoupling ground point close to the return point of the load impedance, or by including a low-value series resistor in the output within the feedback loop.

A further phase lag is introduced by the stray capacitance C_S at the op-amp's inverting input. With normal layout practice, this is of the order of 3−5 pF, which becomes significant when high-value feedback resistors are used, as is common with MOS- and JFET-input amplifiers. The roll-off frequency due to this capacitance is determined by the feedback network impedance as seen from the inverting input. The small-value direct feedback capacitance C_F of Fig. 5.14 can be added to combat this roll-off, by roughly equating time constants in the feedback loop and across the input. In fact this technique is recommended for all low-frequency circuits as with it you can restrict loop bandwidth to the minimum necessary, thereby cutting down on noise, interference susceptibility, and response instability.

Finally in the catalog of instability sources, remember to watch out for parasitic coupling mechanisms, especially from the output to the noninverting input. Any coupling here creates unwanted positive feedback. Layout is the most important factor: keep all feedback and input components close to the amplifier, separate input and output components, keep all pc tracks short and direct, and use a ground plane and/or shield tracks for sensitive circuits.

A_OL does, in fact, change quite markedly with both frequency and temperature. We have already seen (Fig. 5.11) that the ac A_OL rolls off at a constant rate, usually 20 dB/decade, and this determines the gain that can be achieved for any given bandwidth. In fact when the frequency starts approaching the maximum bandwidth the excess gain available becomes progressively lower, and this affects the validity of the high-A_OL approximation. If your circuit has a requirement for precise gain then you need to evaluate the actual gain that will be achieved.

which shows a 10% gain reduction at one-tenth the desired bandwidth!

Two important definitions for noise calculations are the mean value and the root mean square (RMS) value. For any signal we can calculate the mean value using the integration over a time period as shown by:

We have considered the mathematical nature of noise signals using RMS calculations; however, it is important to note that the noise is always spread out over the frequency spectrum. We therefore must consider not only the RMS noise but also the way that the noise is distributed over the spectrum and how we can possibly mitigate the effects of noise as a result on our design. The way that we think about noise is that the overall spectrum is divided into 1-Hz bandwidth “slices” so the noise power density is the mean square noise within that 1-Hz bandwidth.

where S(f) is the autocorrelation function. It is beyond the scope of this book to go much further into the description of how this is derived, however, it can be calculated using the Wiener–Khinchin theorem, which states that the spectral density is the Fourier transform of the autocorrelation function of a random signal (further details can be found in many signal processing textbooks).

We have two main types of noise to consider in practice—thermal noise and flicker noise. White noise has a flat (or constant) spectral density, i.e., S(f) is a constant and is produced by thermal noise generators (or Johnson, Boltzmann). Examples of sources of such noise are resistors, bipolar transistors, diodes, and MOSFET transistors. While, of course, the noise may be not exactly white up to infinity, we can assume the noise is effectively white into the terahertz range. Flicker noise has a different characteristic where the noise spectral density is proportional to 1/f (where f is the frequency). Flicker noise is particularly important in MOS transistors, especially at low frequencies as we shall see. It is important to remember that MOS transistors have both flicker noise and white noise.

The other two sources, such as the dc offset and bias error components discussed earlier, are conventionally referred to the op-amp input. Thermal, or “Johnson” noise is generated in the resistive component of any circuit impedance by thermal agitation of the electrons. All resistors around the input circuit contribute this. It is given by

where e_n = RMS value of noise voltage, k = Boltzmann's constant, 1.38 × 10⁻²³ J/K, T = absolute temperature, B = bandwidth in which the noise is measured, R = circuit resistance.

Amplifier noise is what you will find specified in the data sheet (sometimes; where it is not specified it can be two to four times worse than an equivalent low-noise part). It is characterized as a voltage source in series with one input, and a current source in parallel with each input, with the amplifier itself being considered noiseless. The values are specified at unity bandwidth, as RMS nanovolts or nanoamps per root-hertz; alternatively they may be specified over a given bandwidth. Because you need to add together all noise contributions, it is usually easiest to calculate them at unity bandwidth and then multiply the overall result by the square root of the bandwidth. This assumes a constant noise spectral density over the bandwidth of interest, which is true for resistors but may not be for the op-amp (see later). Noise, being statistical, is added on a root-mean-square basis. So the general noise model for an op-amp circuit is as shown in Fig. 5.17.

Deciding the actual noise bandwidth is not always simple. The bandwidth used in the noise calculations is a notional “brick-wall” value, which assumes infinite attenuation above the cut-off frequency. This of course is not achievable in practice, and the circuit bandwidth has to be adjusted to reflect this fact. For a single-pole response with a cut-off frequency f_c and a roll-off of 6 dB/octave, the noise bandwidth is 1.57f_c. For a cascade of single-pole filters the ratio of the noise bandwidth to cut-off frequency decreases.

Luckily, we have the option to carry out noise analysis using simulations, and we have two choices to consider when we do that. The first option is to add random noise sources that have the correct RMS value of noise and complete time domain simulations, and while this is very accurate, it is also extremely time consuming to complete. The second option is to work in the frequency domain, and in this way the noise analysis in a simulators works like a small-signal frequency analysis (ac) by sweeping the frequency and plotting the output. In the noise analysis, however, unlike the conventional frequency analysis, the sum of the individual noise contributions over the frequency range specified is calculated.

By far the largest number of recent op-amp introductions is aimed at low-power, single-supply applications where the circuit is battery operated. The lithium battery voltage of 3 V is a major driving force in this trend. Although “low power” and “single supply” are independent parameters, they usually coexist as circuit specifications. A few years ago, op-amps were associated with ±15 V supplies, which shrank to ±5 V then to just +5 V; now, nominal +3 V supplies are common, with surprisingly little sacrifice in device performance. But low-power, low-voltage devices are not as forgiving of system design shortcomings because they have less input range to accommodate poorly behaved input signals, less head room to deal with dynamic range requirements, and less output drive capacity. System design decisions should still favor higher voltage rails where these are possible.

One of the disbenefits of not showing supply connections is that it is easy to forget about supply current (I_S). Data sheets will normally give typical and maximum figures for I_S at a specified voltage and no load. If the supply voltages are the same in the circuit as on the data sheet, and if none of the outputs are required to deliver any significant current, then it is reasonable just to add the maximum figures for all the devices in circuit to arrive at a worst-case power consumption. At other supply voltages, you will have to make some estimate of the true supply current, and some data sheets include a graph of typical I_S versus supply voltage to aid in this. Also, note that I_S varies with temperature, usually increasing with cold.

Op-amp supply current is usually a trade-off against speed. You can find devices that are spec'd at 10 μA I_S, but such a part can only offer a slew rate of 0.03 V/μs. Conversely, fast devices require more current, often up to 10 mA. At these levels, package dissipation rears its head. An op-amp run at ±15 V with 10 mA I_S is dissipating 300 mW. With a thermal resistance of 100–150°C/W (the data sheet will give you the exact value) its junction temperature will be 30–45°C above ambient (see Section 9.5.1), and this is before it drives any load! This could well prevent the use of the part at high ambient temperatures and will also affect other parameters that are temperature sensitive. With such a device, make sure you know what its operating temperature will be before getting deeply involved in performance calculations.

The manufacturer will specify temperature-sensitive parameters (which is most of them) either at a nominal temperature (25°C) or over the temperature range. These specifications have bite, in that if the part fails to meet them the customer is entitled to return it and ask for a replacement. So the manufacturer will test the parts at the specification limits. However, he is not responsible for what happens outside the temperature range, and it is more than likely that some parameters will drift out of their specification when the temperature limits are overstepped. Very often these parameters are unimportant in the application, such as offset voltage in an ac amplifier. Therefore you can, with care, design a circuit with wider tolerances than that would be needed for the published figures and trust that these will be sufficient for wide temperature range abuse.

The second factor is reliability. The reliability of any semiconductor device worsens with increasing temperature; a temperature rise of 10°C halves the expected lifetime. So operating ICs at high temperatures is to be avoided wherever possible, but there is no magic cut-off at 70 or 85°C. The maximum junction temperature should always be observed, but this is usually in the region of 100–150°C.

The virtue of selecting industry standards is that the parts are well established, unlikely in the extreme to run into sourcing problems or be withdrawn (the humble 741 has been around for over 30 years!) and, because of the competition between manufacturers, they will remain cheap. If they will do the job, use them in preference to a sole-sourced device. For companies with many different designs of product, keeping the variety of component parts low and reusing them in new designs has the benefit of increasing the total purchase of any given part. This potentially reduces its price further.

Within the last few years there has been a countertrend to the imperative for multisourcing, and the use of industry standards. Hundreds of new types have been introduced, and many of them are much better than their predecessors. They not only minimize the trade-offs between speed, power, precision and cost but are also more fully specified. You can select a part by function and application—for instance, a DAC buffer or 75-Ω cable driver—rather than by comparing technologies, or by looking at a particular specification such as gain-bandwidth product. Following the manufacturer's selection guides on the basis of application will often lead quickly to the most suitable part.

Comparing prices, the LM324 does offer, in fact, the lowest cost-per-op-amp (5 p). This points up another factor to bear in mind when selecting devices: choose a quad or dual package in preference to a single device, when your circuit uses several gain stages. This reduces both unit cost and production cost. Such parts often have quiescent supply currents only slightly greater than a single-channel device, but with better offset, temperature tracking of drift, matching, and other specs. The disadvantages are inflexibility in supply voltage and pc layout, and possible thermal, power rail, or RF interaction between gain blocks on a single substrate.

For the specifications, an input step function is applied, which forces the differential input voltage from one polarity to the other. The overdrive, as in Fig. 5.22, is the final steady-state differential voltage. Usually, the step amplitude is held constant, and its offset is varied to give different overdrive values. The greater the overdrive, the more current is available from the differential input stage to propagate the change of state through to the output, although beyond a certain point there is no gain to be had from increasing it. Small overdrives can lead to surprisingly long response times, and you should check the data sheet carefully to see if the device is being specified in similar fashion to how your circuit will drive it.

The output load resistance R_L (for open-collector types) and capacitance C_L have a major influence on the output slewing rate. The capacitance includes the device output capacitance, circuit strays and the input capacitance of the driven circuit (this last is usually the most significant). The slewing rate is determined by the current that is available to charge and discharge the capacitance, following the rule dV/dt = I/C. For the negative-going transition this current is supplied by the output sink transistor and is in the region of 10–50 mA, assuring a fast edge, but the current available to charge the positive transition is supplied by the pull-up device or resistor and may be an order of magnitude lower. The choice of output resistor directly affects the positive-going rise time (Fig. 5.19) and the power dissipation of the circuit (Fig. 5.23).

On this latter point, it is worth remembering that if you expect low duty–cycle pulses at the output, want low power drain and a fast leading edge and have a choice of logic polarity, that the preferable configuration is to use an active low output as in Fig. 5.24A. The signal is normally off so that power drain is low, and the leading edge transition depends on the output transistor rather than the pull-up. If a fast trailing edge is also needed, the pull-up can be reduced in value without significantly affecting power drain if the duty cycle is low. It is easy and cheap to provide a logic inverter if you really need positive-going pulses.

Continuing this train of thought, you can see that it is quite easy for the pulse timing to be affected by the output rise- and fall-times. This is quite often the source of unexpected errors in circuits, which convert analog levels into pulse widths for timing measurement. Because the pulse rising edge is slowed to a greater extent than the falling edge, the point at which it crosses the following logic gate's switching threshold is different, so that rising and falling analog inputs result in different switching points. This effect is demonstrated in Fig. 5.25. The problem is generally more visible with CMOS-input-level gates than it is with TTL-input-level ones, as TTL's switching threshold is closer to 0 V whereas the CMOS threshold is ill-defined, being anywhere between 0.3 and 0.7 times its supply rail. The difference can amount to a microsecond or more in low-power circuits.

This oscillation can be particularly troublesome if you are interfacing to fast logic circuits, especially when connecting to a clock input. It can be hard to spot on an oscilloscope, as you will probably have the time base set low for the analog signal frequency, but the oscillations appear to the digital input as multiple edges and are treated as such: so for instance a clock counter might advance several counts when it appears to have had only one edge, or a positive-going clock input might erroneously trigger on a negative-going edge.

The preferred solution to this problem is to reduce the stray feedback path to a minimum so that the comparator remains stable even when crossing the linear region. This is achieved by following three golden rules:

Another approach to the problem of unwanted oscillation is to kill it with hysteresis. This approach is used when the above methods fail or cannot be applied, and you can also use it as a legitimate circuit technique in its own right, as in the well-known Schmitt trigger. Hysteresis is the application of deliberate positive feedback to propel the output speedily and predictably through the linear region. The principle of hysteresis is shown in Fig. 5.27.

Also, while considering large differential input voltages, remember that unexpected things can happen to the comparator even when the limits are not exceeded. Response time is usually specified for a common-mode voltage of zero and may degrade when the common-mode limits are approached; this applies equally to bias currents. Some data sheets show curves of input bias current, which have step changes (Fig. 5.28) at certain differential input voltages, due to internal dc feedback. Notice these and make sure your circuit can cope!

There is an obvious trade-off between initial voltage tolerance and tempco on the one hand, and cost and availability on the other, since the manufacturer has to accept a lower yield and longer test and trim time for the closer tolerances. Initial voltage can be trimmed exactly with a potentiometer, but this method adds both parts and production cost, which will offset the higher cost of a tighter tolerance part. Trimming the reference voltage can also worsen the reference temperature coefficient in some configurations, and there is the extra tempco of the trimming components to include. Table 5.2 shows a sample of typical two-terminal 1.2-V references, including their tolerance, tempco, minimum operating current and cost. Most of these are available in different grades, corresponding to tighter or looser tolerances and tempcos.

Line regulation is the change in output voltage due to a specified change in input voltage, normally quoted in microvolts per volt. Load regulation is a similar change due to a change in load current, expressed either in percent for a given current change or as a dynamic resistance in ohms. It should, but does not always, include self-heating effects due to dissipation change.

This is the deviation from nominal output voltage. It is quoted at a given temperature and input voltage or current, and the nominal voltage will differ under other conditions. Generally it is expressed as a percentage figure, but the asymmetry of device yields may persuade a manufacturer to quote upper and lower bounds and the nominal figure may not be in the middle of them. In your circuit design, it is best to ignore the nominal voltage and work everything out for upper and lower limits.

This is the output voltage change due to an ambient temperature difference, usually from 25°C. Because neither band-gap nor zener references exhibit a straight line voltage–temperature curve (see Fig. 5.26) manufacturers choose different ways to express their temperature coefficients, sometimes as an average value across the range in ppm/°C, sometimes as different values at a series of spot temperatures, and sometimes as a worst-case error band in mV. To evaluate different manufacturers' references properly you need to correct for these differences in specification (Fig. 5.30).

Usually expressed in ppm/1000 h or in microvolts change from the nominal voltage, this is a difficult specification to verify and so is often quoted as a typical figure based on characterization of a sample. It is rarely specified on the cheaper components. Zeners tend to stabilize after a couple of years, so for ultraprecision applications the practice of burning in zener references at high temperatures to speed up the settling process is sometimes followed.

This is the time taken for the output to settle within a specified error band after application of power. It is typically in the tens-to-hundreds of microseconds region, and is normally only of interest if you are concerned about the dynamic performance of the reference circuit—for instance, if the application has to wake up rapidly from “sleep” mode. It does not include any long-term effects due to thermal shifts, but of course these do occur, more noticeably at higher operating currents.

The regulation of a two-terminal device is not maintained below a certain minimum current. Typical values for band-gap references are 50–100 μA, with 10 μA being available although some earlier devices are much higher than this. The very low useable operating currents combined with low dynamic resistance at these currents make band-gap devices very much preferable to zener types for low-power circuitry. The maximum operating current is usually based on the point at which the device goes outside its regulation specification, but may also be determined by allowable power dissipation.