Basic insulation provides one level of protection but is not considered fail-safe, and the other level is provided by safety earthing. A failure of the insulation is therefore protected against by the earthing system.

Earthing is not required because the two levels of protection are provided by redundant insulation barriers, one layer of basic plus another supplementary; if one fails the other is still present, and so this system is regarded as fail-safe. The double-square symbol indicates the use of double insulation.

Two layers of insulation can be replaced by a single layer of greater strength to give an equivalent level of protection.

When two nonconductive materials are rubbed together, electrons from one material are transferred to the other. This results in the accumulation of triboelectric charge on the surface of the material. The amount of the charge caused by movement of the materials is a function of the separation of the materials in the triboelectric series, an example of which is shown in Fig. 9.3. Additional factors are the closeness of contact, rate of separation, and humidity. Fig. 8.3 shows the electrostatic voltage related to materials and humidity, from which you can see that possible voltages can exceed 10 kV.

To protect against ESD damage, you need to prevent static buildup and to dissipate or neutralize existing charges. At the same time, operators (including yourself and your design colleagues) need to be aware of the potential hazard. The methods used to do this include the following:

Functional testing may more easily be carried out by ATE. In this case, the function of the human tester is reduced to that of loading and unloading the unit under test, pressing the “go” button and observing the pass/fail indicator. The testing is comprehensively deskilled; the total unit test time is reduced to a few minutes or less. This minimizes the test cost.

In 1985, an ad hoc group created the Joint Test Action Group (JTAG). JTAG had over 200 members around the world, including major electronics and semiconductor manufacturers. This group met to establish a solution to the problems of board test and to promote a solution as an industry standard. They subsequently developed a standard for integrating hardware into compliant devices, which could be controlled by software. This was termed boundary-scan testing. The JTAG proposal was approved in 1990 by the IEEE and defined as IEEE Standard 1149.1-1990 Test Access Port and Boundary Scan Architecture. Since the 1990 approval, updates have been published in 1993 as supplement IEEE Std 1149.1a-1993 and in 1995 as IEEE Std 1149.1b-1994.

Boundary scan is a special type of scan path with a register added at every I/O pin on a device. Although this requires special extra test latches on these pins, the technique offers several important benefits, the most obvious being that it allows fault isolation at the component level. A major problem driving the development of boundary scan has been the adverse effect on testability of surface-mount technology. The inclusion of a boundary-scan path in surface-mount components is sometimes the only way to perform continuity tests between devices. By placing a known value on an output buffer of one device and observing the input buffer of another interconnected device, it is easy to check the interconnection of the PCB net. Failure of this simple test indicates broken circuit traces, dry solder joints, solder bridges, or ESD-induced failures in an IC buffer—all common problems on PCBs.

Every IEEE Std 1149.1-compatible device has four additional pins—two for control and one each for input and output serial test data. These are collectively referred to as the “test access port” (TAP). To be compatible, a component must have certain basic test features, but the standard allows designers to add test features to meet their own unique requirements. A JTAG-compliant device can be a microprocessor, microcontroller, programmable logic device, complex programmable logic device, field programmable gate array, ASIC, or any other discrete device that conforms to the 1149.1 specification. The TAP pins are:

Although the boundary-scan method has enormous advantages for designers faced with the testing of complex, tightly packed circuits, it is not without cost. There is a significant logic overhead in the ICs as well as a small overhead on the board in implementing the TAP, and there is the need for your test department to invest in the resources and become familiar with the method as well as programming each product. As a rough guide, you can use the following rule² (relating to ASIC design) to decide on whether or not the extra effort will be cost-effective:

If you will be using a bed-of-nails fixture, then the PCB layout should allow this. Leave a large area around the outside of the board, and make sure there are no unfilled holes, to enable a good vacuum pressure to be developed to force the board onto the probes. Or if the board will be clamped to the fixture, make sure there is space on the top of the board for the clamps. Decide where your test nodes need to be electrically, and then lay out the board to include target pads on the underside for the probes. These pads should be spaced on a 0.1″ (2.5 mm) grid for accurate drilling of the test jig; down to 0.05″ or 1 mm is possible if the board layout is tight. It is not good practice to use component lead pads as targets, since pressure from the probe may cause a defective joint to appear good. Ensure that tooling holes are provided and are accurately aligned with the targets.

If your test department does not want to use bed-of-nails probing, then help them find the test points that are necessary by bringing them out to test connectors. These can be cheap-and-cheerful pin strips on the board since they will normally only be used once. The matching test jig can then take signals from these connections direct to the test instrumentation via a switch arrangement. Of course, preexisting connectors such as multiway or edge connectors can be used to bring out test signals on unused pins. Be careful, though, that you do not bring long test tracks from one side of the board to the other and thereby compromise the circuit's cross talk, noise susceptibility, and stability. Extra local test connectors are preferable.

There are many design tricks to make testing easier. A simple one is to include a series resistor in circuits where you will want to back-drive against an output, or where you will want to measure a current (Fig. 9.7A). The cost of the resistor is minimal compared to the test time it might save. Of course, you must ensure that the resistor does not affect normal circuit operation. Also, unused digital gate inputs may be taken to a pull-up resistor rather than direct to supply or ground (cf. Section 6.1.5), and this point can then be used to inhibit or enable logic signals for testing purposes only (Fig. 9.7B).

For most of the life of a piece of electronic equipment, its failure rate (denoted by λ) is constant. In the early stages of operation it could be high and decrease as weak components fail quickly and are replaced; late in its life components may begin to “wear out” or corrosion may take its toll, and the failure rate may start to rise again. The reciprocal of failure rate during the constant period is known as the mean time between failures (MTBFs). This is generally quoted in hours, while failure rate is quoted in faults per hour. For instance, an MTBF of 10,000 h is equivalent to a failure rate of 0.0001 faults per hour or 100 faults per 10⁶ h. MTBF has the advantage that it does not depend on the operating period and is therefore more convenient to use than reliability.

MTBF measures equipment reliability on the assumption that it is repaired on each failure and put back into service. For components that are not repairable, their reliability is quoted as mean time to failure (MTTF). This can be calculated statistically by observing a sample from a batch of components and recording each one's working life, a procedure known as life testing. The MTTF for this batch is then given by the mean of the lifetimes.

System users need to know for what proportion of time their system will be available to them. This figure is given by the ratio of “uptime” (U), during which the system is switched on and working, to total operating time. The difference between the two is the “downtime” (D) during which the system is faulty and/or under repair. Therefore we can define the availability, A, using Eq. (9.1):

High temperature is the biggest enemy of all electronic components and measures to keep it down are vital. Temperature rise accelerates component breakdown because chemical reactions occurring within the component, which govern bond fractures, growth of contamination or other processes, have an increased rate of reaction at higher temperature. The rate of reaction is determined by the Arrhenius equation,

where λ gives a measure of failure rate; K is a constant depending on the component type; E is the reaction's activation energy; k is Boltzmann's constant, 1.38 × 10⁻²³ J/K; T is absolute temperature.

There is a very significant improvement to be gained by operating a component well within its nominal rating. For most components this means either its voltage or power rating, or both.

Component manufacturers' reputations are seriously affected by the perceived reliability or otherwise of their product, so most will go to considerable effort not to ship defective parts. However, the cost of detecting and replacing a faulty part rises by an order of magnitude at each stage of the production process, starting at goods inwards inspection, proceeding through board assembly, test and final assembly, and ending up with field repair. You may therefore decide (even in the absence of mandatory procurement requirements on the part of your customer) that it is worth spending extra to specify and purchase parts with a guaranteed reliability specification at the “front end” of production.

Initially it was military requirements, where reliability was more important than cost that drove forward schemes for assessed quality components. More recently many commercial customers have also found it necessary to specify such components. The need for a common standard of assessed quality is met in Europe by the CECC³ scheme. This has superseded the earlier national BS9000 series of standards. CECC documents refer to a “harmonized system of quality assessment for electronic components.”

These specifications all include some degree of stress screening. This phrase refers to testing the components under some type of stress, typically at elevated temperature, under vibration or humidity and with maximum rated voltage applied, for a given period. This practice is also called “burning in.” The principle is that weak components will fail early in their life and the failures can be accelerated by operating them under stress. These can then be weeded out before the parts are shipped from the manufacturer. A typical test might be 160 h at 125°C. Another common test is a repeated temperature cycle between the extremes of the permitted temperature range, which exposes failures due to poor bonding or other mechanical faults.

The failure rate of an electronic assembly is roughly equal to the sum of the failure rates of all its components. This assumes that a failure in any one component causes the failure of the whole assembly. This is not necessarily a valid assumption, but to assume otherwise you would have to work out the assembly's failure modes for each component failure and for combinations of failures, which is not practical unless your customer is prepared to pay for a great deal of development work.

Redundancy is employed at the system level by connecting the outputs of two or more subsystems together such that if one fails, the others will continue to keep the system working. A typical example might be several power supplies, each connected to the same power distribution rail (via isolating diodes) and each capable of supplying the full load. If the reliability of the interconnection is neglected, the probability of all supplies failing simultaneously is the product of the probabilities of failure of each supply on its own, assuming that a common-mode failure (such as the mains supply to all units going off) is ruled out.

An effective and relatively painless way of guarding against design faults is for your product development department to instigate a system of frequent design reviews. In these, a given designer's circuit is subjected to a peer critique to probe for flaws, which might not be apparent to the circuit's originator. The critique can check that the basic circuit concept is sound and cost effective, that all component tolerances have been accounted for, that parts will not be operated outside their ratings, and so on. The depth of the review is determined by the resources that are available within the group; the reviewers should preferably have no connection with the project being reviewed, so that they are able to question underlying and unstated assumptions. Naturally, the effectiveness of such a system depends on the resources a company is prepared to devote to it, and it also depends on the willingness of the designer to undergo a review. Personality clashes tend to surface on these occasions. Each designer develops pet techniques and idiosyncrasies during their career, and provided these are not actually wrong they should not attract criticism. Nevertheless, design reviews are valuable for testing the strength of a design before it gets to the stage where the cost of mistakes becomes significant.

When you have data on the component's thermal resistance directly to ambient, and your mounting method is simple, then the basic model of Fig. 9.11 is adequate. For components that require more sophisticated mounting and whose heat transfer paths are more complicated, you can extend the model easily. The most common application is the power semiconductor mounted via an insulating washer to a heat sink (Fig. 9.12A).

The previous analysis assumed a steady-state heat flow, in other words constant power dissipation. If this is not a good description of your application, you may need to take account of the thermal capacity of the heat sink. The electrical analogue circuit of Fig. 9.12 can be modified according to Fig. 9.13:

In applications where the power dissipated in the device consists of continuous low duty cycle periodic pulses, faster than the heat sink thermal time constant, the instantaneous or peak junction temperature may be the limiting condition rather than the average temperature. In this case you need to consult curves for transient thermal resistance. These curves are normally provided by power semiconductor manufacturers in the form of a correction factor that multiplies R_θj−c to allow for the duty cycle of the power dissipation. Fig. 9.13 shows a family of such curves for the IRF640. Because the period for most pulsed applications is much shorter than the heat sink's thermal time constant, the values of R_θh−a and R_θc−h can be multiplied directly by the duty cycle. Then the junction temperature can now be calculated from Eq. (9.7)

where δ is the duty cycle, and K is derived from curves as in Fig. 9.14 for a particular value of δ. P_Dmax is still the maximum power dissipated during the conduction period, not the power averaged over the whole cycle. At frequencies greater than a few kHz, and duty cycles more than 20%, cycle-by-cycle temperature fluctuations are small enough that the peak junction temperature is determined by the average power dissipation, so that K tends toward δ.

Convective heat loss from a heat sink can be enhanced by forcing the convective medium across its surface. Detailed design of forced air-cooled heat sinks is best done empirically. Simulation software is available to map heat flow and the resulting thermal transfer in complex assemblies; most heat sink applications will be too involved for simple analytical methods to give better than ballpark results. It is not too difficult to use a thermocouple to measure the temperature rise of a prototype design with a given dissipation, most easily generated by a power resistor attached to a dc supply.

where ρ is the density of the medium (air at 30°C and atmospheric pressure is 1.3 kg/m³); c is the specific heat capacity of the medium (air at 30°C is around 1000 J/kg°C).

Radiative cooling is something of a mixed blessing. Radiant heat travels in line of sight and is therefore as likely to raise the temperature of other components in an assembly as to be dissipated to ambient. For the same reason, radiation is rarely a significant contribution to cooling by a finned heat sink, since the finned areas that make up most of the surface merely heat each other. However, radiation can be used to good effect when a clear radiant path to ambient can be established, particularly for high-temperature components in a restricted air flow. The thermal loss through radiation is defined in Eq. (9.9)

where ε is the emissivity of the surface, compared to a black body; ΔT is the temperature difference between the component and environment; Q is given in watts per second per square centimeter.

The heat sink should have a flatness and finish comparable to that of the device package. The higher the power dissipation, the more attention needs to be paid to surface finish. A finish of 50–60 microinches is adequate for most purposes. Surface flatness, which is the deviation in surface height across the device-mounting area, should be less than 4 mils (0.004″) per inch.

Bending the leads of any semiconductor package stresses the lead interface and can result in cracking and consequent unreliability. If possible, mount your devices upright on the PCB so that lead bending is unnecessary. Plastic-packaged devices (TO220, TO126 etc.) can have their leads bent, provided that

In most devices, the heat transfer tab or case is connected directly to one of the device terminals, and this raises the problem of isolating the case. The best solution from the point of view of thermal resistance is to isolate the entire heat sink rather than use any insulating device between the package and the heat sink. This is often not possible, for electromagnetic interference or safety reasons, because the chassis serves as the heat sink, or because several devices share the same heat sink. Some devices are now available in fully isolated packages, but if you are not using one of these you will have to incorporate an insulating washer under the package.

A combination of machine screws, compression washers, flat washers, and nuts is satisfactory for any type of package that has mounting holes. Check the specified mounting hole tolerances carefully; there is a surprisingly wide variation in hole dimensions for the same nominal package type across different manufacturers. A flat, preferably rectangular (in the case of plastic packages) washer under the screw head is vital to give a properly distributed pressure, otherwise cracking of the package is likely. A conical compression washer is a very useful device for ensuring that the correct torque is applied. This applies a constant pressure over a wide range of physical deflection and allows proper assembly by semiskilled operators without using a torque wrench or driver. Tightening the fasteners to the correct torque is very important; too little torque results in a high thermal impedance and long-term unreliability due to overtemperature, while too much can overstress the package and result in long-term unreliability due to package failure.