The Designer’s Guide to VHDL is organized so that it can be read linearly from front to back. This path offers a graduated development, with each chapter building on ideas introduced in the preceding chapters. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are three case studies, which bring together preceding material in the form of extended worked examples.

Chapter 1 introduces the idea of a hardware description language and outlines the reasons for its use and the benefits that ensue. It then proceeds to introduce the basic concepts underlying VHDL, so that they can serve as a basis for examples in subsequent chapters. The next three chapters cover the aspects of VHDL that are most like conventional programming languages. These may be used to describe the behavior of a system in algorithmic terms. Chapter 2 explains the basic type system of the language and introduces the scalar data types. Chapter 3 describes the sequential control structures, and Chapter 4 covers composite data structures used to represent collections of data elements. In Chapter 5, the main facilities of VHDL used for modeling hardware are covered in detail. These include facilities for modeling the basic behavioral elements in a design, the signals that interconnect them and the hierarchical structure of the design.

The next group of chapters extends this basic set of facilities with language features that make modeling of large systems more tractable. Chapter 6 introduces procedures and functions, which can be used to encapsulate behavioral aspects of a design. Chapter 7 introduces the package as a means of collecting together related parts of a design or of creating modules that can be reused in a number of designs. Chapter 8 deals with the important topic of resolved signals, and Chapter 9 describes a number of predefined and standard packages for use in VHDL designs. The combination of facilities described in these early chapters is sufficient for many modeling tasks, so Chapter 10 brings them together in the first case study, in which a multiplier/accumulator circuit is designed.

The third group of chapters covers advanced modeling features in VHDL. Chapter 11 covers aliases as a way of managing the large number of names that arise in a large model. Chapter 12 describes generics as a means of parameterizing the behavior and structure of a design and enhancing the resusability of designs. This leads to a discussion of abstract data types as a means of managing the complexity associated with large designs. Chapter 13 deals with the topics of component instantiation and configuration. These features are important in large real-world models, but they can be difficult to understand. Hence this book introduces structural modeling through the mechanism of direct instantiation in earlier chapters and leaves the more general case of component instantiation and configuration until this later chapter. In Chapter 14, generated regular structures are covered.

The fourth group of chapters covers language facilities generally used for system-level modeling. Chapter 15 introduces the notion of access types (or pointers) and uses them to develop linked data structures. The topic of abstract data types is revisited in the context of container data types. Chapter 16 covers the language facilities for input and output using files, including binary files and text files. Chapter 17 is a case study in which a package for designing memories is developed. The package draws upon features described in the third and fourth groups of chapters.

In the fifth group of chapters, we introduce language features for advanced design and verification. Chapter 18 deals with features for test bench support and verification. It describes how specifications written in the IEEE standard Property Specification Language (PSL) can be embedded in VHDL models. Chapter 19 covers protected types and their use as a means of concurrency control. Chapter 20 describes how we can annotate items in a design with attributes to specify information to be used by design automation tools. This leads into Chapter 21, which covers guidelines for writing synthesizable models. This group of chapters is drawn together in a further case study, Chapter 22, showing development of a synthesizable processor core and its use in a small embedded system, a digital alarm clock.

The final chapter, Chapter 23, is a miscellany of advanced topics not covered in the previous chapters. It includes a discussion of blocks and guarded signals, which are not as widely used in modern designs as previously. Nonetheless, we describe them here for completeness. The chapter also covers use of features for encrypting the source text of models as a means of protecting intellectual property (IP), and use of features of the VHDL Procedureall Interface (VHPI) for incorporating models and applications written in non-VHDL programming languages.

Each chapter in the book is followed by a set of exercises designed to help the reader develop understanding of the material. Where an exercise relates to a particular topic described in the chapter, the section number is included in square brackets. An approximate “difficulty” rating is also provided, expressed using the following symbols:

Answers for the first category of exercises are provided in Appendix C. The remaining categories involve developing VHDL models. Readers are encouraged to test correctness of their models by running them on a VHDL simulator. This is a much more effective learning exercise than comparing paper models with paper solutions.

The first edition of this book was published in 1995, just as VHDL-93 was gaining acceptance. The second edition was updated to reflect the changes in VHDL-2002. Many of the changes in the language standard corrected ambiguities in the previous standard that caused incompatibility between VHDL tools from different vendors. There were also changes that enhanced the usability of the language. The text and examples in the second edition were revised where necessary to reflect the changes in the language. Furthermore, following publication of the first edition, a number of VHDL-related standards were published and gained widespread acceptance. The second edition added descriptions of the IEEE 1076.3 synthesis and IEEE 1076.2 math packages, and was revised to cover the IEEE 1076.6 Synthesis Interoperability Standard.

The latest revision of the language, VHDL-2008, adds a number of significant new language features, making this edition of The Designer’s Guide to VHDL significantly bigger than its predecessors. VHDL-2008 also specifies numerous minor new features and changes to existing features to enhance the usability of the language. This edition integrates descriptions of all of the new and revised features into the text. The differences between the various versions are highlighted in call-outs within the text, headed with “VHDL-2002,” “VHDL-93,” or “VHDL-87,” as appropriate. In addition, some of the material has been removed or rearranged. The case study on a package for arithmetic on bit-vector operands has been deleted because the standard numeric packages have now become widespread. The first case study in this book is a revised version of the MAC case study in previous editions, and shows how the standard packages can be used. The chapter on blocks and guarded signals has been contracted and moved to a section in the last chapter, since the features are now little used in practice. There is a greater emphasis on synthesis in this edition. What was an appendix on the topic in previous editions has been substantially revised and promoted to full chapter status. The large case study showing development of a 32-bit processor model has been revised to show a smaller synthesizable model of an 8-bit microcontroller core and its use in an embedded system. This is much more relevant, both for educational purposes and professional practice. Finally, this edition includes a listing of all of the VHDL standard packages as an appendix for reference.

Although this book attempts to be comprehensive in its coverage of VHDL, there will no doubt be questions that it does not answer. For these, the reader will need to seek other resources. A valuable source of experience and advice, often overlooked, is one’s colleagues, either at the workplace or in user groups. User groups generally hold regular meetings that either formally or informally include a time for questions and answers. Many also run e-mail lists and on-line discussion groups for problem solving.

Accellera is one of a number of organizations that sponsors the EDA Industry Working Groups Web server (www.eda.org). The server has links to Web pages and repositories of several VHDL standards groups and user groups.

Readers who have access to the Usenet electronic news network will find the news group comp.lang.vhdl a valuable resource. This discussion group is a source of announcements, sample models, questions and answers and useful software. Participants include VHDL users and people actively involved in the language standard working group and in VHDL tool development. The “frequently asked questions” (FAQ) file for this group is a mine of useful pointers to books, products and other information. It is archived at www.eda.org.

One resource that must be mentioned is IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual, sometimes referred to as the “VHDL Bible.” It is the authoritative source of information about VHDL. However, since it is a definitional document, not a tutorial, it is written in a complex legalistic style. This makes it very difficult to use to answer the usual questions that arise when writing VHDL models. It should only be used once you are somewhat familiar with VHDL. It can be ordered from the IEEE at standards.ieee.org.

This book contains numerous examples of VHDL models that may also serve as a resource for resolving questions. The VHDL source code for these examples and the case studies, as well as other related information, is available on the companion website for the book at books.elsevier.com/companions/9780120887859.

Although I have been careful to avoid errors in the example code, there are no doubt some that I have missed. I would be pleased to hear about them, so that I can correct them in the on-line code and in future printings of this book. Errata and general comments can be e-mailed to me at [email protected].

The seeds for this book go back to 1990 when I developed a brief set of notes, The VHDL Cookbook, for my computer architecture class at the University of Adelaide. At the time, there were few books on VHDL available, so I made my booklet available for on-line access. News of its availability spread quickly around the world, and within days, my e-mail in-box was bursting. At the time of writing this, nearly 20 years later, I still regularly receive messages about the Cookbook. Many of the respondents urged me to write a full textbook version. With that encouragement, I embarked upon the exercise that led to the first edition of The Designer’s Guide to VHDL. Two years after publication of The Designer’s Guide, the need for a book specifically for students became evident. That led to publication of the first edition of The Student’s Guide to VHDL. I am grateful to the many engineers, students and teachers around the world who gave me the impetus to write these books and who made them such a success. I hope this new edition will continue to meet the need for a comprehensive guide to VHDL.

In the previous editions of The Designer’s Guide and The Student’s Guide, I had the opportunity to extend thanks to the many people who assisted in development of the books. They included my colleagues at the University of Adelaide; my research collaborators, Phil Wilsey at the University of Cincinnati and Perry Alexander at the University of Kansas; the staff at Morgan Kaufmann Publishers, including, in particular, Denise Penrose; the reviewers of the manuscript for the first edition, namely, Poras Balsara of the University of Texas, Paul Menchini of Menchini & Associates, David Pitts of GTE Labs and the University of Lowell and Philip Wilsey of the University of Cincinnati; David Bishop for his contribution to the material on synthesis in the first edition of The Designer’s Guide; and Mentor Graphics Corporation, for use of their ModelSim simulator to check the example models. I remain grateful to all of these people and organizations for their valuable contributions to the earlier editions and to this edition.

For the current edition, I would also like to thank Jim Lewis, who collaborated on a recent book, VHDL-2008: Just the New Stuff. Much of the material from that book has found its way into this book in one form or another. Thanks also to Mentor Graphics Corporation for continued use of the ModelSim simulator to check the example code. I continue to enjoy an excellent working relationship with the staff at Morgan Kaufmann Publishers and their parent company, Elsevier. Thanks to Chuck Glaser, Senior Acquisitions Editor, for his support in the continued development of these VHDL books; to Dawnmarie Simpson, Senior Project Manager in the Production Department, for her meticulous attention to detail; and to Denise Penrose, Publisher, for her longstanding support of my writing endeavors.

The previous editions of The Designer’s Guide to VHDL were dedicated to my wife Katrina. As I said in the first edition preface, I used to think that authors dedicating their books to their partners was somewhat contrived, but that Katrina’s understanding, encouragement and support taught me otherwise. I remain deeply grateful for her continued support and am honored to also dedicate this third edition to her.