Both constants and variables need to be declared before they can be used in a model. A declaration simply introduces the name of the object, defines its type and may give it an initial value. The syntax rule for a constant declaration is

   constant_declaration  ⇐
      constant identifier {, ... } : subtype_indication [ := expression ];

The identifiers listed are the names of the constants being defined (one per name), and the subtype indication specifies the type of all of the constants. We look at ways of specifying the type in detail in subsequent sections of this chapter. The optional part shown in the syntax rule is an expression that specifies the value that each constant assumes. This part can only be omitted in certain cases that we discuss in Chapter 7. Until then, we always include it in examples. Here are some examples of constant declarations:

   constant number_of_bytes : integer := 4;
   constant number_of_bits : integer := 8 * number_of_bytes;
   constant e : real := 2.718281828;
   constant prop_delay : time := 3 ns;
   constant size_limit, count_limit : integer := 255;

The reason for using a constant is to have a name and an explicitly defined type for a value, rather than just writing the value as a literal. This makes the model more intelligible to the reader, since the name and type convey much more information about the intended use of the object than the literal value alone. Furthermore, if we need to change the value as the model evolves, we only need to update the declaration. This is much easier and more reliable than trying to find and update all instances of a literal value throughout a model. It is good practice to use constants rather than writing literal values within a model.

The form of a variable declaration is similar to a constant declaration. The syntax rule is

   variable_declaration ⇐
      variable identifier {, ... } : subtype_indication [ := expression ];

Here also the initialization expression is optional. If we omit it, the default initial value assumed by the variable when it is created depends on the type. For scalar types, the default initial value is the leftmost value of the type. For example, for integers it is the smallest representable integer. Some examples of variable declarations are

   variable index : integer := 0;
   variable sum, average, largest : real;
   variable start, finish : time := 0 ns;

If we include more than one identifier in a variable declaration, it is the same as having separate declarations for each identifier. For example, the last declaration above is the same as the two declarations

   variable start : time := 0 ns;
   variable finish : time := 0 ns;

This is not normally significant unless the initialization expression is such that it potentially produces different values on two successive evaluations. The only time this may occur is if the initialization expression contains a call to a function with side effects (see Chapter 6).

Constant and variable declarations can appear in a number of places in a VHDL model, including in the declaration parts of processes. In this case, the declared object can be used only within the process. One restriction on where a variable declaration may occur is that it may not be placed so that the variable would be accessible to more than one process. This is to prevent the strange effects that might otherwise occur if the processes were to modify the variable in indeterminate order. The exception to this rule is if a variable is declared specially as a shared variable. We discuss shared variables in the full edition of this book. We will leave discussion of shared variables until Chapter 19.

   entity ent is
   end entity ent;
   architecture sample of ent is
    constant pi : real := 3.14159;
   begin
    process is
      variable counter : integer;
    begin
      -- ...        -- statements using pi and counter
    end process;
   end architecture sample;

Once a variable has been declared, its value can be modified by an assignment statement. The syntax of a variable assignment statement is given by the rule

   variable_assignment_statement ⇐ [ label : ] name := expression;

The optional label provides a means of identifying the assignment statement. We will discuss reasons for labeling statements in Chapter 20. Until then, we will simply omit the label in our examples. The name in a variable assignment statement identifies the variable to be changed, and the expression is evaluated to produce the new value. The type of this value must match the type of the variable. The full details of how an expression is formed are covered in the rest of this chapter. For now, just think of expressions as the usual combinations of identifiers and literals with operators. Here are some examples of assignment statements:

   program_counter := 0;
   index := index + 1;

The first assignment sets the value of the variable program_counter to zero, overwriting any previous value. The second example increments the value of index by one.

It is important to note the difference between a variable assignment statement, shown here, and a signal assignment statement, introduced in Chapter 1. A variable assignment immediately overwrites the variable with a new value. A signal assignment, on the other hand, schedules a new value to be applied to a signal at some later time. We will return to signal assignments in Chapter 5. Because of the significant difference between the two kinds of assignment, VHDL uses distinct symbols: “:=” for variable assignment and “<=” for signal assignment.

We introduce new types into a VHDL model by using type declarations. The declaration names a type and specifies which values may be stored in objects of the type. The syntax rule for a type declaration is

   type_declaration ⇐ type identifier is type_definition;

One important point to note is that if two types are declared separately with identical type definitions, they are nevertheless distinct and incompatible types. For example, if we have two type declarations:

   type apples is range 0 to 100;
   type oranges is range 0 to 100;

we may not assign a value of type apples to a variable of type oranges, since they are of different types.

An important use of types is to specify the allowed values for ports of an entity. In the examples in Chapter 1, we saw the type name bit used to specify that ports may take only the values ‘0’ and ‘1’. If we define our own types for ports, the type names must be declared in a package, so that they are visible in the entity declaration. We will describe packages in more detail in Chapter 7; we introduce them here to enable us to write entity declarations using types of our own devising. For example, suppose we wish to define an adder entity that adds small integers in the range 0 to 255. We write a package containing the type declaration, as follows:

   package int_types is
    type small_int is range 0 to 255;
   end package int_types;

This defines a package named int_types, which provides the type named small_int. The package is a separate design unit and is analyzed before any entity declaration that needs to use the type it provides. We can use the type by preceding an entity declaration with a use clause, for example:

   use work.int_types.all;

   entity small_adder is
    port ( a, b : in small_int; s : out small_int );
   end entity small_adder;

When we discuss packages in Chapter 7, we will explain the precise meaning of use clauses such as this. For now, we treat it as “magic” needed to declare types for use in entity declarations.

In VHDL, integer types have values that are whole numbers. An example of an integer type is the predefined type integer, which includes all the whole numbers representable on a particular host computer. The language standard requires that the type integer include at least the numbers –2,147,483,647 to +2,147,483,647 (–231 + 1 to +231 – 1), but VHDL implementations may extend the range.

We can define a new integer type using a range-constraint type definition. The simplified syntax rule for an integer type definition is

   integer_type_definition ⇐
      range simple_expression ( to | downto ) simple_expression

which defines the set of integers between (and including) the values given by the two expressions. The expressions must evaluate to integer values. If we use the keyword to, we are defining an ascending range, in which values are ordered from the smallest on the left to the largest on the right. On the other hand, using the keyword downto defines a descending range, in which values are ordered left to right from largest to smallest. The reasons for distinguishing between ascending and descending ranges will become clear later.

An an example, here are two integer type declarations:

   type day_of_month is range 0 to 31;
   type year is range 0 to 2100;

These two types are quite distinct, even though they include some values in common. Thus if we declare variables of these types:

   variable today : day_of_month := 9;
   variable start_year : year := 1987;

it would be illegal to make the assignment

   start_year := today;

Even though the number 9 is a member of the type year, in context it is treated as being of type day_of_month, which is incompatible with type year. This type rule helps us to avoid inadvertently mixing numbers that represent different kinds of things.

If we wish to use an arithmetic expression to specify the bounds of the range, the values used in the expression must be locally static; that is, they must be known when the model is analyzed. For example, we can use constant values in an expression as part of a range definition:

   constant number_of_bits : integer := 32;
   type bit_index is range 0 to number_of_bits - 1;

The operations that can be performed on values of integer types include the familiar arithmetic operations:

The result of an operation is an integer of the same type as the operand or operands. For the binary operators (those that take two operands), the operands must be of the same type. The right operand of the exponentiation operator must be a non-negative integer.

The identity and negation operators are unary, meaning that they only take a single, right operand. The result of the identity operator is its operand unchanged, while the negation operator produces zero minus the operand. So, for example, the following all produce the same result:

   A + (-B)    A - (+B)    A - B

The division operator produces an integer that is the result of dividing, with any fractional part truncated toward zero. The remainder operator is defined such that the relation

   A = (A / B) * B + (A rem B)

is satisfied. The result of Arem B is the remainder left over from division of A by B. It has the same sign as A and has absolute value less than the absolute value of B. For example:

   5 rem 3  = 2      (–5) rem 3  = –2
   5 rem (–3) = 2   (–5) rem (-3) = –2

Note that in these expressions, the parentheses are required by the grammar of VHDL. The two operators, rem and negation, may not be written side by side. The modulo operator conforms to the mathematical definition satisfying the relation

   A = B * N   +   (A mod B)    -- for some integer N

The result of Amod B has the same sign as B and has absolute value less than the absolute value of B. For example:

   5 mod 3    = 2     (–5) mod 3    = 1
   5 mod (–3) = –1    (–5) mod (–3) = –2

In addition to these operations, VHDL defines operations to find the larger (maximum) and the smaller (minimum) of two integers. For example

   maximum(3, 20) = 20    minimum(3, 20) = 3

While we could use an if statement for this purpose, such as the following:

   if A > B then
    greater := A;
   else
    greater := B;
   end if;

using the maximum or minimum operation is much more convenient:

   greater := maximum(A, B);

When a variable is declared to be of an integer type, the default initial value is the leftmost value in the range of the type. For ascending ranges, this will be the least value, and for descending ranges, it will be the greatest value. If we have these declarations:

   type set_index_range is range 21 downto 11;
   type mode_pos_range is range 5 to 7;
   variable set_index : set_index_range;
   variable mode_pos : mode_pos_range;

the initial value of set_index is 21, and that of mode_pos is 5. The initial value of a variable of type integer is –2,147,483,647 or less, since this type is predefined as an ascending range that must include –2,147,483,647.

Floating-point types in VHDL are used to represent real numbers. Mathematically speaking, there is an infinite number of real numbers within any interval, so it is not possible to represent real numbers exactly on a computer. Hence floating-point types are only an approximation to real numbers. The term “floating point” refers to the fact that they are represented using a mantissa part and an exponent part. This is similar to the way in which we represent numbers in scientific notation.

Floating-point types in VHDL conform to IEEE Standard 754 or 854 for floating-point computation and are represented using at least 64 bits. This gives approximately 15 decimal digits of precision, and a range of approximately –1.8E+308 to +1.8E+308. An implementation may choose to use a larger representation, providing correspondingly greater precision or range. There is a predefined floating-point type called real, which includes the greatest range allowed by the implementation’s floating-point representation. In most implementations, this will be the range of the IEEE 64-bit double-precision representation.

We define a new floating-point type using a range-constraint type definition. The simplified syntax rule for a floating-point type definition is

   floating_type_definition ⇐
     range simple_expression ( to | downto ) simple_expression

This is similar to the way in which an integer type is declared, except that the bounds must evaluate to floating-point numbers. Some examples of floating-point type declarations are

   type input_level is range –10.0 to +10.0;
   type probability is range 0.0 to 1.0;

The operations that can be performed on floating-point values include the arithmetic operations addition and identity (“+”), subtraction and negation (“-”), multiplication (“*”), division (“/”), absolute value (abs), exponentiation (“**”), maximum, and minimum. The result of an operation is of the same floating-point type as the operand or operands. For the binary operators (those that take two operands), the operands must be of the same type. The exception is that the right operand of the exponentiation operator must be an integer. The identity and negation operators are unary (meaning that they only take a single, right operand).

Variables that are declared to be of a floating-point type have a default initial value that is the leftmost value in the range of the type. So if we declare a variable to be of the type input_level shown above:

   variable input_A : input_level;

its initial value is –10.0.

The remaining numeric types in VHDL are physical types. They are used to represent real-world physical quantities, such as length, mass, time and current. The definition of a physical type includes the primary unit of measure and may also include some secondary units, which are integral multiples of the primary unit. The simplified syntax rule for a physical type definition is

   physical_type_definition ⇐
     range simple_expression ( to | downto ) simple_expression
        units
           identifier ;
           { identifier = physical_literal ; }
        end units [ identifier ]
   physical_literal ⇐ [ decimal_literal | based_literal ] unit_name

A physical type definition is like an integer type definition, but with the units definition part added. The primary unit (the first identifier after the units keyword) is the smallest unit that is represented. We may then define a number of secondary units, as we shall see in a moment. The range specifies the multiples of the primary unit that are included in the type. If the identifier is included at the end of the units definition part, it must repeat the name of the type being defined.

To illustrate, here is a declaration of a physical type representing electrical resistance:

   type resistance is range 0 to 1E9
    units
      ohm;
   end units resistance;

Literal values of this type are written as a numeric literal followed by the unit name, for example:

   5 ohm    22 ohm    471_000 ohm

Notice that we must include a space before the unit name. Also, if the number is the literal 1, it can be omitted, leaving just the unit name. So the following two literals represent the same value:

   ohm    1 ohm

Note that values such as -5 ohm and 1E16 ohm are not included in the type resistance, since the values -5 and 1E16 lie outside of the range of the type.

Now that we have seen how to write physical literals, we can look at how to specify secondary units in a physical type declaration. We do this by indicating how many primary units comprise a secondary unit. Our declaration for the resistance type can now be extended:

   type resistance is range 0 to 1E9
    units
      ohm;
      kohm = 1000 ohm;
      Mohm = 1000 kohm;
    end units resistance;

Notice that once one secondary unit is defined, it can be used to specify further secondary units. Of course, the secondary units do not have to be powers of 10 times the primary unit; however, the multiplier must be an integer. For example, a physical type for length might be declared as

   type length is range 0 to 1E9
    units
       um;                  -- primary unit: micron
       mm = 1000 um;        -- metric units
       m = 1000 mm;
       inch = 25400 um;     -- imperial units
       foot = 12 inch;
    end units length;

We can write physical literals of this type using the secondary units, for example:

   23 mm    2 foot    9 inch

When we write physical literals, we can write non-integral multiples of primary or secondary units. If the value we write is not an exact multiple of the primary unit, it is rounded down to the nearest multiple. For example, we might write the following literals of type length, each of which represents the same value:

   0.1 inch    2.54 mm    2.540528 mm

The last of these is rounded down to 2540 um, since the primary unit for length is um. If we write the physical literal 6.8 um, it is rounded down to the value 6 um.

Many of the arithmetic operators can be applied to physical types, but with some restrictions. The addition, subtraction, identity, negation, abs, mod, rem, maximum, and minimum operations can be applied to values of physical types, in which case they yield results that are of the same type as the operand or operands. In the case of mod and rem, the operations are based on the number of primary units in each of the operand values, for example:

   20 mm rem    6 mm =    2 mm
   1  m  rem  300 mm =  100 mm

A value of a physical type can be multiplied by a number of type integer or real to yield a value of the same physical type, for example:

   5 mm * 6 = 30 mm

A value of a physical type can be divided by a number of type integer or real to yield a value of the same physical type. Furthermore, two values of the same physical type can be divided to yield an integer, for example:

   18 kohm / 2.0    = 9 kohm
   33 kohm / 22 ohm = 1500

Also, the abs operator may be applied to a value of a physical type to yield a value of the same type, for example:

   abs 2 foot    = 2 foot
   abs (-2 foot) = 2 foot

The restrictions make sense when we consider that physical types represent actual physical quantities, and arithmetic should be done so as to produce results of the correct dimensions. It doesn’t make sense to multiply two lengths together to yield a length; the result should logically be an area. So VHDL does not allow direct multiplication of two physical types. Instead, we must convert the values to abstract integers to do the calculation, then convert the result back to the final physical type. (See the discussion of the ‘pos and ‘val attributes in Section 2.4.)

A variable that is declared to be of a physical type has a default initial value that is the leftmost value in the range of the type. For example, the default initial values for the types declared above are 0 ohm for resistance and 0 um for length.

   type time is range implementation defined
     units
       fs;
       ps = 1000 fs;
       ns = 1000 ps;
       us = 1000 ns;
       ms = 1000 us;
       sec = 1000 ms;
       min = 60 sec;
       hr = 60 min;
     end units;

   signal triangle_wave : real;
   ...
   wave_proc : process is
    variable phase : time;
   begin
    phase := (now + t_offset) mod t_period_wave;
    if phase <= t_period_wave/2 then
      triangle_wave <= 4.0 * real(phase/t_period_wave) - 1.0;
    else
      triangle_wave <= 3.0 - 4.0 * real(phase/t_period_wave);
    end if;
    wait for tperiod_sample;
   end process wave_proc;

Often when writing models of hardware at an abstract level, it is useful to use a set of names for the encoded values of some signals, rather than committing to a bit-level encoding straightaway. VHDL enumeration types allow us to do this. For example, suppose we are modeling a processor, and we want to define names for the function codes for the arithmetic unit. A suitable type declaration is

   type alu_function is
    (disable, pass, add, subtract, multiply, divide);

Such a type is called an enumeration, because the literal values used are enumerated in a list. The syntax rule for enumeration type definitions in general is

enumeration_type_definition ⇐ ( ( identifier | character_literal ) { , ... } )

There must be at least one value in the type, and each value may be either an identifier, as in the above example, or a character literal. An example of this latter case is

   type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7'),

Given the above two type declarations, we could declare variables:

   variable alu_op : alu_function;
   variable last_digit : octal_digit := '0';

and make assignments to them:

   alu_op := subtract;
   last_digit := '7';

Different enumeration types may include the same identifier as a literal (called overloading), so the context of use must make it clear which type is meant. To illustrate this, consider the following declarations:

   type logic_level is (unknown, low, undriven, high);
   variable control : logic_level;
   type water_level is (dangerously_low, low, ok);
   variable water_sensor : water_level;

Here, the literal low is overloaded, since it is a member of both types. However, the assignments

   control := low;
   water_sensor := low;

are both acceptable, since the types of the variables are sufficient to determine which low is being referred to.

When a variable of an enumeration type is declared, the default initial value is the leftmost element in the enumeration list. So unknown is the default initial value for type logic_level, and dangerously_low is that for type water_level.

There are three predefined enumeration types defined as

   type severity_level is
    (note, warning, error, failure);
   type file_open_status is
    (open_ok, status_error, name_error, mode_error);
   type file_open_kind is
    (read_mode, write_mode, append_mode);

The type severity_level is used in assertion statements, which we will discuss in Chapter 3, and the types file_open_status and file_open_kind are used for file operations, which we will discuss in Chapter 16. For the remainder of this section, we look at the other predefined enumeration types and the operations applicable to them.

   type character is (
     nul,    soh,    stx,    etx,    eot,    enq,    ack,    bel,
     bs,     ht,     lf,     vt,     ff,     cr,     so,    si,
     dle,    dc1,    dc2,    dc3,    dc4,    nak,    syn,    etb,
     can,    em,    sub,    esc,    fsp,    gsp,    rsp,    usp,
     ' ',    '!',    '"',    '#',    '$',    '%',    '&',    ''',
     '(',    ')',    '*',    '+',    ',',    '-',    '.',    '/',
     '0',    '1',    '2',    '3',    '4',    '5',    '6',    '7',
     '8',    '9',    ':',    ';',    '<',    '=',    '>',    '?',
     '@',    'A',    'B',    'C',    'D',    'E',    'F',    'G',
     'H',    'I',    'J',    'K',    'L',    'M',    'N',    'O',
     'P',    'Q',    'R',    'S',    'T',    'U',    'V',    'W',
     'X',    'Y',    'Z',    '[',    '',    ']',    '∧',    '_',
     '`',    'a',    'b',    'c',    'd',    'e',    'f',    'g',
     'h',    'i',    'j',    'k',    'l',    'm',    'n',    'o',
     'p',    'q',    'r',    's',    't',    'u',    'v',    'w',
     'x',    'y',    'z',    '{',    '|',    '}',    '~',    del,
     c128,   c129,   c130,   c131,   c132,   c133,   c134,   c135,
     c136,   c137,   c138,   c139,   c140,   c141,   c142,   c143,
     c144,   c145,   c146,   c147,   c148,   c149,   c150,   c151,
     c152,   c153,   c154,   c155,   c156,   c157,   c158,   c159,
     ' ',    'i',    '¢',    '£',    '¤',    '¥',    '¦',    '§',
     '..;',   '©',    'a',    '≪',   '¬',    '-',    '®',    '-',
     '°',    '±',    '2',    '3',    ''',    'μ',    '¶',    '·',
     '¸',    '1",    '○',    '≫',   '¼',    '½',    '¾',    '¿',
     'À',    'Á',    'Â',    'Ã',    'Ä',    'Å',    'Æ',    'Ç',
     'È',    'É',    'Ê',    'Ë',    'Ì',    'Í',    'Î',    'Ï',
     'Đ',   'Ñ',    'Ò',    'Ó',    'Ô',    'Õ',    'Ö',    '×',
     '⊘',   'Ù',    'Ú',    'Û',    'Ü',    'Ý',    'þ',    'ß',
     'à',    'á',    'â',    'ã',    'ä',    'å',    'æ',    'Ç',
     'è',    'é',    'ê',    'ë',    'ì',    'í',    'î',    'ï',
     'đ',   'ñ',    'ò',    'ó',    'ô',    'õ',    'ö',    '÷',
     '⊘',   'ù',    'ú',    'û',    'ü',    'ý',    'þ',    'ÿ'),

   variable cmd_char, terminator : character;

   cmd_char := 'P'
   terminator := cr;

   type boolean is (false, true);

   123 = 123     'A' = 'A'     7 ns = 7 ns

   123 = 456     'A' = 'z'     7 ns = 2 us

   123 < 456     789 ps <= 789 ps     '1' > '0'

   96 >= 102     2 us < 4 ns     'X' < 'X'

   (b /= 0) and (a/b > 1)

   type bit is ('0', '1'),

   '0' and '1' = '0',   '1' xor '1' = '0'

   '0' and true

   write_reg_n := not ( not write_enable_n and not select_reg_n );

  type std_ulogic is ('U',        -- Uninitialized
                      'X',        -- Forcing Unknown
                      '0',        -- Forcing zero
                      '1',        -- Forcing one
                      'Z',        -- High Impedance
                      'W',        -- Weak Unknown
                      'L',        -- Weak zero
                      'H',        -- Weak one
                      '-'),       -- Don't care

   library ieee; use ieee.std_logic_1164.all;

   '1' ?= 'H' = '1'     '1' ?/= 'H' = '0'
   '0' ?= 'H' = '0'     '0' ?/= 'H' = '1'

   'Z' ?= 'H'     = 'X'     'W' ?/= 'H'    = 'X'
   '0' ?= 'U'     = 'U'     '0' ?/= 'U'    = 'U'
   '1' ?= '-'     = '1'     '-' ?/= '-'    = '0'

   signal cs1, ncs2, cs3 : std_ulogic;

   if cs1 and not cs2 and cs3 then
    ...
   end if;

   wait until clk;

   if ?? (cs1 and not cs2 and cs3) then
     ...
   end if;

   if cs1 and cs3 and alu_op = pass then ... -- illegal

   if cs1 = '1' and cs3 = '1' and alu_op = pass then ...

   if cs1 = '1' and ncs2 = '0' and cs3 = '1' then
     ...
   end if;

In Section 2.2 we saw how to declare a type, which defines a set of values. Often a model contains objects that should only take on a restricted range of the complete set of values. We can represent such objects by declaring a subtype, which defines a restricted set of values from a base type. The condition that determines which values are in the subtype is called a constraint. Using a subtype declaration makes clear our intention about which values are valid and makes it possible to check that invalid values are not used. The simplified syntax rules for a subtype declaration are

   subtype_declaration ⇐ subtype identifier is subtype_indication;
   subtype_indication ⇐
     type_mark [ range simple_expression ( to | downto ) simple_expression ]

We will look at more advanced forms of subtype indications in later chapters. The subtype declaration defines the identifier as a subtype of the base type specified by the type mark, with the range constraint restricting the values for the subtype. The constraint is optional, which means that it is possible to have a subtype that includes all of the values of the base type.

Here is an example of a declaration that defines a subtype of integer:

   subtype small_int is integer range –128 to 127;

Values of small_int are constrained to be within the range -128 to 127. If we declare some variables:

   variable deviation : small_int;
   variable adjustment : integer;

we can use them in calculations:

   deviation := deviation + adjustment;

Note that in this case, we can mix the subtype and base type values in the addition to produce a value of type integer, but the result must be within the range -128 to 127 for the assignment to succeed. If it is not, an error will be signaled when the variable is assigned. All of the operations that are applicable to the base type can also be used on values of a subtype. The operations produce values of the base type rather than the subtype. However, the assignment operation will not assign a value to a variable of a subtype if the value does not meet the constraint.

Another point to note is that if a base type is a range of one direction (ascending or descending), and a subtype is specified with a range constraint of the opposite direction, it is the subtype specification that counts. For example, the predefined type integer is an ascending range. If we declare a subtype as

   subtype bit_index is integer range 31 downto 0;

this subtype is a descending range.

The VHDL standard includes two predefined integer subtypes, defined as

   subtype natural is integer range 0 to highest_integer;
   subtype positive is integer range 1 to highest_integer;

Where the logic of a design indicates that a number should not be negative, it is good style to use one of these subtypes rather than the base type integer. In this way, we can detect any design errors that incorrectly cause negative numbers to be produced. There is also a predefined subtype of the physical type time, defined as

   subtype delay_length is time range 0 fs to highest_time;

This subtype should be used wherever a non-negative time delay is required.

Sometimes it is not clear from the context what the type of a particular value is. In the case of overloaded enumeration literals, it may be necessary to specify explicitly which type is meant. We can do this using type qualification, which consists of writing the type name followed by a single quote character, then an expression enclosed in parentheses. For example, given the enumeration types

   type logic_level is (unknown, low, undriven, high);
   type system_state is (unknown, ready, busy);

we can distinguish between the common literal values by writing

   logic_level'(unknown)     system_state'(unknown)

Type qualification can also be used to narrow a value down to a particular subtype of a base type. For example, if we define a subtype of logic_level

   subtype valid_level is logic_level range low to high;

we can explicitly specify a value of either the type or the subtype

   logic_level'(high)     valid_level'(high)

Of course, it is an error if the expression being qualified is not of the type specified.

When we introduced the arithmetic operators in previous sections, we stated that the operands must be of the same type. This precludes mixing integer and floating-point values in arithmetic expressions. Where we need to do mixed arithmetic, we can use type conversions to convert between integer and floating-point values. The form of a type conversion is the name of the type we want to convert to, followed by a value in parentheses. For example, to convert between the types integer and real, we could write

   real(123) integer(3.6)

Converting an integer to a floating-point value is simply a change in representation, although some loss of precision may occur. Converting from a floating-point value to an integer involves rounding to the nearest integer. Numeric type conversions are not the only conversion allowed. In general, we can convert between any closely related types. Other examples of closely related types are certain array types, discussed in Chapter 4.

One thing to watch out for is the distinction between type qualification and type conversion. The former simply states the type of a value, whereas the latter changes the value, possibly to a different type. One way to remember this distinction is to think of “quote for qualification.”