FIXED- AND FLOATING-POINT PROCESSORS

As depicted in Figure 3-5, DSPs are organized around a fixed or floating-point architecture. The fixed-point architecture is the simplest approach and was the original way that DSPs were designed. The floating-point architecture uses the conventional mantissa and exponent notations. Just like any other processor, fixed-point operations yield more precision but yield a lesser range of fractions. The fixed-point processors are available in 16-bit, 20-bit, or 24-bit word sizes. In contrast, floating-point processors use a 32-bit word length. For purposes of efficiency and expense, designers attempt to use the smallest word size to support the application. Currently, the most common word size for a fixed point processor is 16 bits. It is likely the reader has studied the arithmetic of fixed- and floating-point operations, so we will not dwell on these operations here.

One last point is relevant to this discussion. Be aware that as a general practice, the word size of the instruction word size is the same in most processors. However, exceptions do exist, and some implementations support a part 16-bit word size, and a 24-bit instruction word size.