PREDICTABILITY OF PERFORMANCE

Earlier, we discussed the critical need for DSPs to support real-time applications. Therefore, they must exhibit predictable execution performance because of the tight time constraints involved in real-time execution. In contrast, some generalized processors use code that may consume a different number of instruction cycles depending on what branching operations may take place. Consequently, it is quite difficult with these architectures to predict how long it will take for certain operations to take place. This lack of predictability makes it difficult to optimize code or to predict the timing of the execution of the code in certain situations.

Since the DSP programmer determines the exact set of instructions when they are processed, it is a relatively easy task to predict the time required in executing the code on a DSP. In a nutshell, DSPs do not use the general processor's concepts of branch predictions and speculative execution. The DSP executes highly specialized instruction sets to perform certain functions in a very efficient manner.

An interesting aspect of this situation from a programming standpoint is that the code is certainly less than intuitive, and may require some retraining on the part of a conventional application programmer. To illustrate this point, consider this instruction based on the Motorola DSP 56300 system [EYRE98]. X and Y represent two Harvard architecture memory spaces:

This instruction directs the DSP to do the following:

• Multiply the contents of registers X0 and Y0.

• Add the result to a running total stored in accumulator A.

• Load register X0 from X, pointed to by register R0.

• Load register Y0 from Y, pointed to by register R4.

• Postincrement R0 by one; and

• Postincrement R4 by the contents of register R4.

It is tight code, and is quite specialized. This single line of code encompasses all the operations to calculate an FIR filter trap.

Compilers are available to allow programmers to write in C or C++ for translations for execution on DSPs. Generally, they do not work very well because the use of multiple memory spaces, irregular instruction sets, and the use of multiple buses and memory locations makes it a particularly big challenge to write efficient compilers for DSPs.