Noise

Noise generally refers to any signal that interferes with or degrades a signal of interest. It is often used with an adjective for problems, such as phase noise, switching noise, cross talk noise, and reflection noise. In this text we will limit the term noise to mean random or pseudo-random, natural signals, which are generally not a result of the PCB design. Functional problems such as cross talk or ringing (which are PCB-related problems) will be named as such. From this perspective there are two basic categories of noise: background noise and intrinsic component noise. These noise problems are generally addressed by the circuit designer, not the PCB designer, but are discussed here briefly for completeness.

Distortion

Distortion is an issue more related to analog circuitry because of the nature of continuous signals. In analog circuitry, all voltages between the power supply rails may be of significance. Digital signals are not continuous: they are either HI or LO and usually nothing in between matters. As long as voltage levels meet threshold specifications, there is no ambiguity and therefore no quality issues. Ringing on the rising and falling edges of a square wave might be considered distortion, but that is handled differently, as described below. Distortion of a sinusoidal signal (which normally has a single spike on a frequency spectrum) begins to occur in amplifiers as the sine waves either are clipped or experience a phase reversal. Op amps have amplitude limits imposed by the power supplies, their drive capabilities, and their frequency response. If the amplitude of a sinusoidal output signal (as determined by the input signal times the gain) exceeds the output capability of the op amp, then the output signal will be clipped off and begin to resemble a square wave. Square waves are composed of many sine waves, which are primarily odd harmonics of the fundamental frequency of the square wave. The dominant harmonic is typically the third one, so as a sine wave begins to clip the onset of third harmonic distortion is observed.

If the input signal exceeds the op amp’s input limits (as imposed by the power supply rails), the output signal will also be distorted. Some amplifiers simply clip the signal (causing third harmonic distortion), while other op amps experience phase inversion, which also causes harmonic distortion.

These problems are caused by the circuit design and component selection and are not the fault of the PCB design. These effects are mentioned because, if you are not used to them or do not know about them, they can be confused with PCB layout problems. Along with harmonic distortion ringing will produce unwanted frequency components, which can be seen with a spectrum analyzer and may be confused with other forms of distortion or noise. Ringing is caused by reflections, which in turn are caused by impedance mismatches on PCB traces, which is a function of the PCB design.

Frequency response

Both analog and digital circuits have frequency limits. In digital circuitry, if frequency limits are exceeded the signal level may rise and fall before a gate has a chance to switch states. This may give the appearance that the signal is attenuated or that the receiving gate is “not seeing” the signal. This too is a circuit design problem and not a PCB problem. In circuit design, we need to make sure that the components selected are within design constraints.

When signals exceed the frequency limits of analog circuitry, the output signal will also be attenuated, and distortion will result if the sine wave begins to look like a triangle wave at the output of the frequency-limited component. This is a function of the amplifier’s slew rate, −3 dB BW, and gain bandwidth product. Again these issues need to be handled at the circuit design level, well before the PCB design stage.

Electromagnetic interference and cross talk

There are three goals in designing PCBs for electrical performance and signal integrity: (1) The PCB should be immune from interference from other systems, (2) it should not produce emissions that cause problems for other systems, and (3) it should demonstrate the desired signal quality. A common factor relating these three issues is electromagnetic waves. As Fig. 6.1 shows, “noise” can be introduced into your PCB from outside sources, and it can produce noise that is radiated to other systems and to itself.

When electromagnetic waves get into your system, this is referred to as electromagnetic interference (EMI). On the flip side, your PCB can be the source of EMI and cause problems for other systems. The ability for systems to “play nice together” is referred to as electromagnetic compatibility (EMC). The FCC has established rules for many types of systems regarding EMI and EMC, which, depending on your application, your PCB may have to abide by. Properly laying out your PCB can greatly reduce EMI and improve EMC. In this section we take a look at how to minimize EMI and its effects. There are many good books available that address these issues in greater detail. The material in this chapter is not intended to duplicate those works but to provide an overview of the issues and provide insight on how to design PCBs with PCB Editor with regard to signal integrity issues.

The method by which systems and circuits can “reach out and touch” another circuit is inductive and capacitive coupling of electromagnetic fields.

In the 1820s Faraday and Henry showed that an electric current could be produced in a conductor by changing the current in another, nearby conductor (Serway, 1992, p. 806). And years later, Maxwell showed that changing electric fields also produce magnetic fields. These fields are the source of many woes in PCB design. We begin by looking at magnetic fields and inductive coupling.

Magnetic fields and inductive coupling

As shown in Fig. 6.2 a magnetic field vector, B, is developed around a conductor when current flows through the conductor, into the “X” end and out of the “Dot” end of the conductor. The right-hand rule (from Ampere’s law) is used to determine the direction of the field: If the thumb of the right-hand points in the direction of conventional current flow (movement of positive charges), then the magnetic field curls in the direction of the fingers. This is defined mathematically by a cross product called the Biot–Savart law. By applying some calculus, which will not be shown here, an equation can be derived for the scalar (nonvector) magnitude, B, of the magnetic field vector, B, near the conductor.

The magnitude of the magnetic field a distance, r, from a long straight conductor (Serway, 1992, p. 838) is given by Eq. (6.1),

$B=\frac{{\mu }_{0}I}{2\pi r^2},$ (6.1)

(6.1)

where B is the magnitude of the magnetic field in Wb/m², μ₀ is the permeability of free space (μ₀=4π×10⁻⁷ Wb/A m), I is the current in amps (A), and r is the distance from the conductor.

The total magnetic field within or through an area is called magnetic flux, Φ, which has units of Wb and is described by Eq. (6.2) (Serway, 1992, p. 849; Wb/m²×m²=Wb):

$\Phi =BA\cos (\theta ),$ (6.2)

(6.2)

where B is the magnetic field magnitude per unit area (Wb/m²), A is the area intersected by the magnetic field (m²), and θ is the angle between B and A.

Magnetic flux expands or contracts in proportion to changes in current flow. As the flux expands or contracts around the conductor, we see from Faraday’s Law of Induction, given in Eq. (6.3) (Serway, 1992, p. 877), that a voltage is induced into the conductor. This is known as self-induced electromotive force (emf):

$E=-\frac{d\Phi }{dt}.$ (6.3)

(6.3)

The minus sign in Eq. (6.3) is a result of Lenz’s law, which states that the emf induced into the conductor produces a current in the conductor that creates a magnetic flux that will oppose the changing magnetic flux. This effect is called self-inductance. The self-inductance tends to limit how fast the current can change in a conductor. This is what makes an inductor have inductance and oppose AC currents in analog circuits and fast rise times in digital circuits. The magnitude of the inductance, L, is shown in Eq. (6.4):

$L=\frac{N{\Phi }_m}{I}.$ (6.4)

(6.4)

The inductance is directly proportional to N, the number of turns on a coil (N=1 for a PCB trace and its return path), and the magnetic flux and is inversely proportional to the current, I.

If a secondary conductor is near a primary conductor, which is carrying current as shown in Fig. 6.3, some of the flux will be felt by the secondary conductor. If the current through the primary conductor changes with respect to time (as in the case of a rising edge of a digital signal or an AC signal) the magnetic field (and therefore the magnetic flux) also changes with respect to time as it increases in strength and expands outward (or decreases in strength and contracts inward) from (or toward) the primary conductor.

When the flux that is impinging on the secondary conductor changes with respect to time, as it expands or contracts, we see again from Faraday’s Law of Induction in Eq. (6.3) that a voltage, E_g, is induced into the secondary conductor. Using the right-hand rule for electric generators, the direction of the induced current can be determined. To use the right-hand rule point the thumb in the direction of the motion of the conductor (relative to the expanding/shrinking flux—ν_C), point the first finger in the direction of the B field, and the middle finger will point in the direction of the force applied to the positive charges $({\mathrm{F}}_c^{+})$ and therefore the positive current flow. The resultant voltage and current are shown in Fig. 6.3. Notice that the current in the secondary conductor flows in the direction opposite that of the current in the primary conductor as a result of the induced voltage. This produces a secondary magnetic field that opposes and partially cancels the primary magnetic field (by Lenz’s law).

If the induced current flow in the secondary conductor is changing with respect to time (which it is because the primary conductor is causing it to) and it is in close proximity to the first conductor (which it is), then the secondary conductor will also induce an emf back into the primary conductor. The magnetic flux that goes back and forth between the two conductors is called mutual inductance.

The emf (voltage) generated into the primary conductor (by the secondary conductor) will be in a direction that aids the original current flow in the primary conductor as the secondary flux tries to oppose the primary flux. If the original flux is partially canceled, then the self-inductance is also partially canceled and the changing current in the primary conductor is not as limited (i.e., it sees less inductance).

It would seem that unlimited current could flow in the primary inductor since the secondary conductor aids it, but the secondary inductor also experiences its own self-inductance and is therefore limited. Also the amount of mutual inductance between the two conductors is limited by how much of the flux couples the two conductors. This is similar to the coupling coefficient in transformers and in both circumstances is never 100%.

When a trace on a PCB induces a voltage into an adjacent signal trace we call that cross talk, which is bad because it generates noise in the adjacent signal trace. But if the second conductor is the PCB’s ground plane, that is good because it reduces the trace’s inductance and therefore the overall loop inductance of the circuit. For the time being we will stick with using the term return plane, rather than ground plane, for reasons described later.

Loop inductance

In Fig. 6.3 only segments of the traces were shown. Of course for current to flow through the circuit, a closed path must exist, as shown in Fig. 6.4. Any conductor in the circuit that carries current will produce a magnetic field as indicated by the circular arrows.

An equation for inductance is given in Eq. (6.5) (Serway, 1992, p. 905),

$L={\mu }_0{n}^{2}A\ell ,$ (6.5)

(6.5)

where n is the number of turns (1), A$\ell$ is the volume that the circuit occupies, and μ₀ is the relative permeability of the material in which the circuit exists. For most materials used in PCBs, μ₀=1. So the inductance is a function of the volume of the inductor and the number of turns of the conductor around the space. Therefore, inductance is dependent on the circuit geometry, by which a smaller volume results in a smaller circuit or loop inductance.

If we look at the closed-loop circuit shown in Fig. 6.4 with respect to its volume, we can see that, if the circuit is physically large and makes a large loop, it will have what is referred to as high loop inductance.

If on the other hand we arrange the circuit as shown in Fig. 6.5, we can see from Eq. (6.5) that the loop inductance will be less since there is less volume. If you notice the direction of the arrows (the magnetic fields) you can see that the source current and the return current magnetic fields oppose each other, thereby reducing the flux and inductance.

Fig. 6.6A shows the resultant magnetic field of two conductors in close proximity where the currents are in the same direction. As indicated the magnetic fields circulate in the same direction and aid each other. This is the case for an inductor in which the turns are wound in the same direction and build up an overall strong magnetic field.

Fig. 6.6B shows the resultant magnetic field when the currents of the two conductors are in opposite directions. The magnetic fields oppose each other and result in partial flux cancellation. The amount of cancellation depends on the amount of mutual inductance, which in turn depends in part on the distance between the conductors.

The situations in Figs. 6.4–6.6 are steady-state DC circuits, but if we apply the concept in Fig. 6.3 and Eq. (6.3) for time-varying currents, then we can see that, if the return trace on a circuit board is in close proximity to the signal trace, then the inductance of the traces is reduced; that is, the loop inductance of the closed-loop circuit is reduced. If the loop inductance is reduced in an AC circuit, then by Eq. (6.6) it can be seen that there will be less inductive reactance (X_L), less voltage drop, and less cross talk (fewer EMI problems):

$X_L=2\pi fL$ (6.6)

(6.6)

To maintain a small X_L (and low loop inductance), we need to have the return path as wide as possible (low self-inductance) and as close as possible to the signal path wherever possible (maximum coupling and small cross-sectional areas). The easiest way to do this is by using a plane layer as the return path. The return plane has historically (and most often inappropriately) been called the ground plane, but it is being referred to more often as an image plane or a return plane. In PCB design a return plane has low inductance (and therefore low self-inductance) and it is everywhere the signal trace is and therefore allows for maximum coupling between the signal trace and the plane for any and all widths of the signal trace.

From this discussion then we can say that one of the most important functions of the return (image) plane is to reduce loop inductance. Reducing loop inductance (and the magnetic fields related to it) provides a low-impedance return path for power and signal lines and reduces unwanted cross talk to nearby conductors. It should also be stated that cross talk between unrelated conductors is also reduced by keeping them farther apart (i.e., r is large).

Electric fields and capacitive coupling

We saw in the previous paragraphs that keeping signal and power lines close to their return paths provides flux cancellation and reduces loop inductance, which is beneficial in all respects. But what happens with the electric fields under these circumstances and what is the effect on the circuit? Fig. 6.7A shows electric field lines for a single charged conductor, which can represent a signal trace that is a long way away from its return path. Fig. 6.7B shows electric field lines between two oppositely charged conductors, which can represent a signal or power line close to its return path. As shown, the solitary conductor radiates electric field lines in all directions, while the coupled conductors contain (or at least concentrate) the electric field between them.

The Ampere–Maxwell law (Serway, 1992, p. 851) states that “magnetic fields are produced both by conduction currents and by changing electric fields.” So, to minimize cross talk, it would seem to be in our best interest not to allow traces to radiate electric fields in an uncontrolled manner but to keep the signal (and power) traces close to their return paths. This is true for both magnetic and electric fields.

But what happens to the capacitance of the traces relative to the return plane when we do this? The equation of a parallel plate capacitor (in farads) in air is given in Eq. (6.7) (Serway, 1992, p. 712),

$C=\frac{{\epsilon }_{0}A}{d},$ (6.7)

(6.7)

where C is capacitance (in farads), ε₀ is permittivity of free space, A is the area common to the parallel plates, and d is the distance between the plates. As indicated, as the plates become closer together or as the area becomes larger, the capacitance increases. This also holds for the capacitance between a trace and the return plane, although as we will see later the equation is slightly different and the units are in F/in. to make it easier to calculate capacitance for various trace lengths.

From Eq. (6.8) we can see that as the capacitance, C, increases the capacitive reactance decreases:

$X_C=\frac{1}{2\pi fC}.$ (6.8)

(6.8)

By combining Eqs. (6.7) and (6.8) as shown in Eq. (6.9), we can see that, by keeping traces and power planes close to their return planes (small d), the capacitive reactance between the trace and the return plane is reduced (coupling is increased):

$X_C=\frac{d}{2\pi f{\epsilon }_{0}A}.$ (6.9)

(6.9)

And by keeping unrelated signal traces farther apart (large d), the reactance between the traces is higher and the coupling (cross talk) is reduced. With both magnetic and electric fields, the wider the return path (the areas of the conductor), the better the coupling, and the closer the signal or power conductor is to the return plane, the better the coupling.

What Ground is and what it is not

Ground Symbol

In the previous discussion, the term return plane was used instead of the term ground plane. Unless the return plane is physically connected to the earth by some means, it really has nothing to do with “ground.” The ground symbol, , has long been used on schematics (in academia and in practice) to indicate a connection to the point to which all closed-circuit currents must return. An example is shown in Fig. 6.8. This gives the impression that ground, somehow, is an omnipresent, unfaltering current sink and equipotential reference. Equipotential means that the voltage is the same everywhere, regardless of how much current is flowing through it. This is a myth.

Although the depiction of the ground connection shown in Fig. 6.8 is convenient to use on the schematic, in reality there has to be a physical, real-world connection. And, just so you know, the official ground symbols per IEEE Std 315-1975 (ANSI Y32.2-1975) are given in Table 6.1. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner. However, it is quite common that the ground and return symbols are used otherwise. Since the ground concept has been around a long time, it is unlikely that its use will change overnight. The important thing is that it is clear what the symbol means. The standard states that the symbols can be given supplementary information (such as names) on the schematic to specifically annotate the symbol’s purpose or function.

Table 6.1

IEEE/ANSI standard ground symbols.

Symbol	Name	Purpose/usage
	Earth GND	A direct connection to the earth.
		A direct connection to a vehicle’s or an airplane’s frame that serves the same function as earth ground
	Noiseless GND	Used to indicate a low or noiseless earth ground
	Safety GND	Used to indicate a ground connection that serves a safety function against electric shock
	Chassis GND	A connection to a chassis, or frame, or similar connection of a printed circuit board and may be completely different from earth ground
	Return	Used to indicate common return connections

Source: Adapted and reprinted with permission from IEEE, ©2003.

There are two basic ground and source connection schemes, parallel and series connections, as shown in Fig. 6.9. A parallel ground system is shown in Fig. 6.9A. A parallel ground system is also called a separate ground system, since the current flow in each branch is supplied by and returns to the source through completely separate paths. A series-connected ground system is shown in Fig. 6.9B. The series-connected ground system is also referred to as a common ground system or daisy chain, since the current flows in the two branches share a common path.

At the schematic level the circuits in Fig. 6.9 are identical; mathematically the circuits are also identical, that is, I_T=I₁+I₂ and V_R1=V_R2=V_s. Furthermore, as indicated in Fig. 6.9B, you could connect R₁ to the common return path at either point (1) or point (2) without changing the meaning of the circuit description in any way. However, on the PCB, the two circuits shown in Fig. 6.9 can be significantly different. There may even be significant differences between points (1) and (2) in Fig. 6.9B.

It was said earlier that any conductor that carries current will produce a magnetic field. Even if there is very tight coupling between the signal conductor and its return conductor, some inductance will always exist because the coupling is not 100.0% complete; that is, there is less than perfect mutual inductance from the primary trace to the secondary trace (the return plane) and from the secondary trace back to the primary trace.

With this understanding we can see from Fig. 6.10 that there is an “unseen” schematic within the PCB. As a result, although the relationship I_T=I₁+I₂ is still true, it should be realized that V_R1=V_R2=V_s is no longer true because there are voltage drops along the shared and individual impedances between the source and each of the loads. Furthermore points (1) and (2) and any other points along the return path are not equipotential. The ideal, equipotential ground plane does not exist in practice.

Common impedance is particularly troublesome when high-power or noisy signals share common return paths (Z_COMMON1 and Z_COMMON2) with low-power signals. High-speed digital signals operating near low-level analog signals are an example.

Clearly then, it would seem that the best return system is the parallel system shown in Fig. 6.9A. However, a potential problem arises when we try to implement this approach on the PCB. Fig. 6.11 shows the routing scenarios in which Fig. 6.11A is the parallel connection, and Fig. 6.11B is the series connection. As described above and shown in Fig. 6.11A, the current paths do not interfere with each other in the parallel connection since their paths are completely separate, and since each signal path is directly above its return path, there is tight coupling between the signal and the return, and therefore the inductance is minimized. The problem is that it would become incredibly cumbersome to route a PCB using this approach with even a few additional components and worse on a high-density, multilayer PCB. If components are moved, movement of the signal and return paths would have to be carefully coordinated, resulting in many opportunities for routing “errors” that could be difficult to detect.

The series connection in Fig. 6.11B is obviously much easier to route, but it loses the benefit of the separate signal and return paths. Even with the signal and return paths tightly coupled, the common paths (impedances) could be problematic for circuits operating at high frequency or with fast rise times.

Ground (return) planes

Above, we said that we want the return path to be as wide as possible and as “everywhere” as possible, which, when taken to the extreme, causes the return path to become a plane. But since (at first glance) it appears that a plane is potentially a common return path (a common impedance), the question arises as to whether this is really the best solution to overcome the inconvenience of the routing problem. If we reroute the circuit of Fig. 6.8 as shown in Fig. 6.12, in which the return path is the GND plane in PCB Editor (where the thermal reliefs indicate a connection to the GND plane), we can analyze the situation. If the signal path is relatively close to the return path, the return signal will automatically flow through the GND plane directly below the signal trace. The reason this happens is that by doing so the loop inductance of the circuit is minimized. As is commonly known in DC circuits, current follows the path of least resistance. Perhaps not as commonly known, AC currents will follow the path of least impedance and, particularly on PCBs, the path of least inductance. The only way for that to happen is if the return current travels directly under the signal trace on its way back to the source. This is true no matter what kind of crazy path the signal trace makes, as long as no discontinuities exist in the return plane.

So (in Fig. 6.12) even if R₂ was directly between R₁ and the PCB connector, the return paths would not be common as long as the signal traces to R₁ and R₂ did not overlap (which can happen if the signal traces were routed on different layers) or become “too” close. We will look at the appropriate trace separation (what too close means) in the routing section discussed later.

Ground bounce and rail collapse

In a typical PCB the power distribution system contains one or more power and ground planes. The power and ground planes are like very wide traces (have little inductance) and are usually adjacent to each other (high capacitance). This is exactly what we want for the power distribution system. However, despite these advantages, a problem occurs in high-speed digital systems when gates switch from one state to another. The problem in general is known as switching noise.

Fig. 6.13 shows a representative CMOS logic gate. The capacitor, C_L, represents all of the capacitances related to construction of the CMOS transistors Q1 and Q2. When the gate switches from one state to another, C_L has to charge (or discharge) before the gate can reach its steady-state value. For example, at a logic state of 0, Q1 is off and Q2 is on, the output (and VC_L) is at V_SS (0 V). When the gate tries to switch to a high state, logic level 1, Q1 turns on, Q2 turns off, and C_L begins to charge to V_DD. During this transition the gate consumes significant power because for a brief moment Q1 and Q2 are both partially on. A short circuit exists from V_DD to V_SS through Q1 and Q2 and through C_L (which has low impedance while it charges). Because a high current results (even if only briefly) the voltage at the V_DD pin tends to drop until the switching is complete and C_L is fully charged. A similar thing happens when the gate tries to change from a logic 1 to a logic 0 state, except that as C_L tries to discharge through Q2 (which is turning on as Q1 turns off) the voltage at the V_SS pin tends to rise until the switching is complete and C_L is fully discharged.

Because the power and ground planes are not superconductors, there is a drop in voltage between the supply pins of the gate and where power is connected to the PCB (same for the return plane). Remember that there is always some amount of resistance and inductance—even on the so-called ground plane. This is shown in Fig. 6.14, in which we see the supply voltages across the PCB while the gate is switching. The drop in the positive rail is called rail collapse and the rise in ground potential is called ground bounce. Note that, since there is really nothing magical about the so-called ground plane, the term rail collapse can refer to the ground rail rising as well as the supply rail dropping.

The solid line in Fig. 6.14 shows that a relatively linear drop in positive rail voltage (or rise in ground potential) occurs along the distance from the connector to the switching gate when none of the ICs on the PCB have bypass capacitors. The worst voltage drop occurs at the gate itself, but any gates located between the switching gate and the connector will “feel” the voltage drop as well.

The dashed lines in Fig. 6.14 indicate the voltage drop (or rise in ground potential) when all of the ICs have bypass capacitors. The capacitors act as current reservoirs and help hold up the positive rail voltage and keep down the return (ground) rail voltage except at close proximity to the gate that is switching (although it is minimized there as well).

The primary purpose of bypass capacitors in digital circuits is to promote a stable PCB power distribution system and prevent rail collapse and ground bounce—that is, to keep switching noise off from the rails. Conversely, the purpose of analog bypass capacitors is to keep any power supply noise that does exist from getting to the analog circuitry; that is, the bypass capacitors act as low-pass filters and short out power supply transients (noise) before they get to the amplifiers.

Since analog circuits (particularly amplifiers) are usually designed to operate strictly between (and a safe distance from) the rails, they rarely cause rail collapse but are usually the victims of it. The purpose of amplifier circuits is to amplify small signals, which are often in the millivolt or microvolt range; thus a very quiet circuit environment is highly desirable. Since digital switching noise can be as much as 100 mV or more, making analog and digital systems work together on the same PCB can be a significant challenge.

Even when a PCB’s power distribution system is well-designed (low inductance planes and lots of bypass caps) switching noise can be a significant problem for analog circuits (and other digital circuits for that matter) as the switching currents surge across the PCB planes. This is particularly true if the analog circuitry is between the PCB connector and the noise digital circuitry. Any voltage drops along the path will be seen as noise by the analog system.

It was said earlier (see Fig. 6.12) that, as long as traces did not overlap or if they were not too close, the return currents would tend to stay directly under the signal traces and cross talk would be minimized. However, in very high-frequency analog or high-speed digital systems, return currents (whether signal or power return) may deviate from the ideal path because of imperfections in the PCB’s copper plating and variations in the laminate materials. As a result, high-frequency analog and high-speed digital return currents may actually spread across a return plane “looking” for the path of least inductance. This occurs particularly when a signal leaves one layer and goes to another through a via and the return currents do not have an easy path from the one return plane to another that is closer to the new signal layer.

Split power and ground planes

The solution to the problem of digital noise being injected into analog circuitry through the supply planes is to segregate the analog components from the digital ones and eliminate common return paths. Segregating the components is straightforward; the components are physically placed in different places on the board. Eliminating common return paths can be accomplished by splitting the ground and power planes into separate areas. The various planes are shown in Fig. 6.15. A typical plane is one continuous sheet (an entire layer dedicated to a single power or ground connection) as shown in Fig. 6.15A. But it is possible and advantageous to break up the plane into sections or to create completely separate planes for the digital and analog areas. Fig. 6.15B shows a split plane that provides isolated areas on a single layer while providing an electrically common reference point. This configuration is common where power electronics are placed over the plane area that is close to the board connectors, and analog and digital electronics are placed over their respective return planes. This allows all circuits on the board to be referenced to a common ground but forces the specific return currents to stay within their own areas. This is demonstrated in the PCB Design Examples.

Return planes can also be completely separate areas by using moats as in Fig. 6.15C or distinct continuous planes as shown in Fig. 6.15D. Moated planes are sometimes used as local ground or reference planes for high-speed clocks or small sections of a circuit that require their own regulated supply or ground potential, and isolated planes are used where parts of the system do not share a common ground reference or power supply system.

Care must be exercised when using split or multiple isolated ground and power planes. Even if the planes are separated physically, noise can be capacitively coupled from one plane to the next as shown in Fig. 6.16A and B. To minimize noise coupling between analog and digital planes, split planes on different layers should be prevented from overlapping each other, as shown in Fig. 6.16C, or should be separated with a shield plane, as shown in Fig. 6.16D. This is demonstrated in Example 3 in Chapter 9, PCB design examples.

On rare occasions the analog and digital return or reference planes of a PCB may be on different layers (and not overlapping or separated by a shield plane) but must be referenced to a common point (for example, when working with analog-to-digital and digital-to-analog converters). So the question becomes how to keep them physically separated but electrically connected. The easiest way is by using the isolated planes (Fig. 6.15C) and then connecting the planes at a point using a plated through hole as shown in Fig. 6.17A or a shorting bar. Moated planes (Fig. 6.15C) can also be connected using the shorting bar. Both of these methods can be used in PCB Editor and are demonstrated in the PCB Design Examples.

Characteristic impedance

It was stated earlier that to minimize cross talk we want to minimize trace (loop) inductance and maximize the capacitance to the return plane. What does this do to the characteristic impedance, Z₀, of a trace?

Perhaps the first thing to do is to look at what characteristic impedance really is. For example RG58 is a coaxial cable that is often used as a shielded transmission line in 50-Ω systems. Actually, RG58 is about 52 Ω, not 50 Ω. But even so, what does that mean? If you use an ohmmeter to measure the resistance from the center conductor to the shield, you will see that it is neither 52 nor 50 Ω. So how is its characteristic impedance 52 Ω?

Fig. 6.18 shows a model of a transmission line, which consists of series inductors and parallel capacitors. This is called the lumped-element model, which assumes that the series resistance is negligibly small and that the transmission line is infinitely long (or at least long enough to watch what happens). Each LC “lump” represents a finite section of the transmission line, and the sum total of the elements is representative of the total inductance and capacitance of the transmission line.

We begin the analysis with all of the capacitors discharged and all currents at zero. At time t=0 seconds the switch is shut, which applies the source voltage, V_S, to the transmission line through the source resistance R_s as shown in Fig. 6.19. Initially C₁ acts as a short circuit so I=V_S/R_S. Current, I, begins to charge capacitor C₁, and a return current will also flow out of the bottom of C₁ back to the source (note that this is a displacement current as postulated by Maxwell rather than a conduction current as defined by Ampere). The instantaneous impedance is Z_C1=V_line/I.

As C₁ charges (no longer acting like a short), current begins to flow into L₁. Each inductor pair (L₁ and L₂, L₃ and L₄, etc.) is mutually coupled, so the magnetic field of L₁ induces the return current in L₂.

As current flows past L₁, C₂ begins charging positively on the topside; and as L₂ forces return current to flow back to the source (due to mutual inductance), C₂ begins charging negatively on the bottom side (relative to its top lead).

At some point C₁ becomes fully charged to a value of V_C1=V_line=V_S−I×R_S and then the displacement current no longer flows through C₁, so the instantaneous impedance at C₁ is Z_C1=∞ and Z_C2=V_line/I. Current continues down the line, charging up each capacitor in turn to a value of V_Cn=V_line.

As each capacitor along the way is charging, the instantaneous impedance across the line is Z_Cn=V_line/I_Cn as shown in Fig. 6.20. As each capacitor becomes fully charged, its impedance goes to infinity because the displacement current through it goes to zero. As seen from the source (V_S) the impedance of the line is Z_line=V_line/I=V_line/I_Cn and is dynamic since it travels along the line. Furthermore, the impedance farther down the line is unknown.

The speed at which the instantaneous impedance travels along the line is dependent on the inductance and the capacitance of each section. It was said above it is desirable to have as little loop inductance as possible (which will never be zero) and as much capacitance as possible (which will never be infinite). Thus there will always be finite inductive reactance (X₁) and capacitive reactance (X_C) during any transient. However, the capacitors that are charged have nothing to do with the impedance (since they look like open circuits) and the inductors that have steady-state current flowing through them have nothing to do with the impedance (since they look like shorts). The capacitors and inductors farther down the line have nothing to do with the impedance either, since they do not see any action until the capacitors and inductors before them have approached a steady-state condition. Until the voltage (V_line) reaches the load, Z_T, the source actually has no idea the load, Z_T, even exists; neither does it know how many sections of L and C there are until all of the previous sections have reached steady state. If the impedance of each section is the same all along the line, then we call the instantaneous impedance the characteristic impedance of the transmission line and give it the special symbol Z₀.

Before we consider what happens to the current flow and line voltage in Fig. 6.20 once all of the capacitors are charged and the line voltage and current reach Z_T, we need to take a closer look at the behavior of the transmission line. From the above discussion we see that it takes a finite amount of time for the applied voltage (minus the voltage drop, $V_{RS}$) to propagate down the line, and, as the applied voltage propagates, it essentially behaves as a wave. In fact the effects described here are due to wave properties and not directly due to electrons flowing (at least not like we normally think of them). The key to understanding Z₀ (and reflections and ringing, as we will see shortly) is in understanding how and at what speed the waves travel.

If you ask an average person how fast electricity travels, you will usually get the answer that it travels at the speed of light. Except in one particular case, that answer is not correct. If we think of electricity as flowing electrons, then electricity actually travels at only about 1 cm/s (Bogatin, 2004, p. 211), pretty slow really. This seems counterintuitive since when we turn on a light switch the lights come on seemingly immediately, as if the “electricity” traveled at the speed of light from the switch to the light bulb. But what does travel at (almost) the speed of light is the electromagnetic wave that is launched into the wiring by the switch closing.

Fig. 6.21 can be used to explain the difference between the speed of electrons and the electromagnetic wave velocity. The figure shows a copper tube, which contains marbles that are separated by small springs. If an additional marble (No. 5) is shoved into the tube, marble 4 is shoved further into the tube, compressing the spring between it and marble 3. Note that in this early stage marbles 2 and 1 have no idea what is going on yet. As No. 5 is shoved into No. 4’s place the rest of the marbles must “do the wave” to make room for it. Eventually all of the marbles have slid over by one marble space and marble 1 pops out the other end.

Notice now that all of the marbles have moved a distance of only one marble space, but the effect of this movement (a wave) is felt at the end of the tube in about the same amount of time. The speed of the wave is determined for the most part by the value of the spring constants and partly by the momentum of the marbles.

So in a transmission line the electrons travel slowly, but the electromagnetic (EM) waves travel fast. The speed of the EM wave is determined by how quickly the magnetic fields in the inductors and the electric fields in the capacitors can be built up or dissipated, which is influenced by the material properties and geometry of the PCB through which the wave travels.

The velocity of an EM wave through a medium is described by Eq. (6.10),

$v_{\mathrm{EM}}=\frac{1}{\sqrt{{\epsilon }_0{\epsilon }_r{\mu }_0{\mu }_r}},$ (6.10)

(6.10)

where v_EM is the velocity of the EM wave in a given material, ε₀ is the permittivity of free space (8.89×10⁻¹² F/m), ε_r is the relative permittivity (dielectric constant) of the material (a unitless constant relative to ε₀), μ₀ is the permeability of free space (4π×10⁻⁷ H/m), and μ_r is the relative permeability of the material (a unitless constant relative to μ₀).

You may recall that the speed of light, c (a special EM wave), in free space is

$c=\frac{1}{\sqrt{{\epsilon }_0{\mu }_0}}.$ (6.11)

(6.11)

So we can rewrite Eq. (6.10) as

$v_{\mathrm{EM}}=c\times \frac{1}{\sqrt{{\epsilon }_r{\mu }_r}}.$ (6.12)

(6.12)

As stated, the terms ε_r (relative permittivity) and μ_r (relative permeability) are unitless. Furthermore μ_r is equal to 1 in. free space and in most polymers (including FR4 laminate), so we can further simplify Eq. (6.12) as shown in Eq. (6.13):

$v_{\mathrm{EM}}=c\times \frac{1}{\sqrt{{\epsilon }_r}}.$ (6.13)

(6.13)

From Eq. (6.13) we see that the velocity of an EM wave (which comprises both electric and magnetic fields) in a PCB varies inversely with the relative permittivity, ε_r.

Relating this observation with Eq. (6.7), we can state (without rigorous proof) that the capacitance of a transmission line is determined by the geometry of the transmission line and the relative dielectric constant (ε_r) within the transmission line. And the inductance of a transmission line (specifically the loop inductance) is determined by the geometry, but μ_r falls out since it is equal to 1 [see Eq. (6.5) and Figs. 6.4 and 6.5)].

In practice, calculating the characteristic impedance, capacitance, and inductance can be fairly complex, depending on the geometry of the circuit, but fortunately that has been done for us for the most common transmission line configurations. The equations are shown in Tables 6.2–6.5. The PCB designer has full control over the trace width (w) and partial control over the trace thickness (t) by selecting the ounces per square foot but may have little or no control over the thickness of the laminate (h). These equations are solved for w and presented later in this chapter (in Tables 6.6 and 6.7).

Table 6.2

Surface microstrip transmission lines.

Microstrip transmission lines		Z0(Ω)	C0 (pF/in.)
Surface		$Z_0=\frac{k}{\sqrt{{\epsilon }_r+1.41}}\ln \left(\frac{5.98h}{0.8w+t}\right)$	$C_0=\frac{0.67({\epsilon }_r+1.41)}{\ln \left(5.98h/\left(0.8w+t\right)\right)}$
Surface differential		$Z_{\mathrm{diff}}=2Z_0\left[1-0.48\times {\mathrm{e}}^{\left(-0.964\left(d/h\right)\right)}\right]$
		Z0 same as surface microstrip

$L_0=(Z_0^2\times C_0)/12$ in nH/in, where k=87 for 15<w<25 mil and k=79 for 5=<w<15 mil. Restrictions: 0.1<w/h<3.0 and 1<ε_r<15 (typically 4.0–4.5 for FR4).

Table 6.3

Embedded microstrip transmission lines.

Microstrip transmission lines		Z0(Ω)	C0 (pF/in.)
Embedded		$Z_0=\frac{k}{\sqrt{{\epsilon }_r+1.41}}\ln \left(\frac{5.98h}{0.8w+t}\right)\left(1-\frac{h_1}{0.1}\right)$	$C_0=\frac{1.41{\epsilon }_{r,\mathrm{eff}}}{\ln \left(5.98h/\left(0.8w+t\right)\right)}$
		OR
		$Z_0=\frac{k}{{\epsilon }_{r,\mathrm{eff}}+1.41}\ln \left(\frac{5.98h_2}{0.8w+t}\right)$
		${\epsilon }_{r,\mathrm{eff}}={\epsilon }_r(1-e^{-1.55H/h_2})$
Embedded edge coupled differential		$Z_{\mathrm{diff}}=2Z_0\left(1-0.48\times e^{-0.964/\left(2h-t\right)}\right)$
		h=h1=h2
		Z0 same as embedded microstrip

k=87. Restrictions: 0.1 w/h<3.0, 1<ε_r<15, and Z₀<Z_diff<2Z₀.

Table 6.4

Balanced stripline.

Stripline transmission lines		z0(Ω)	C0 (pF/in.)
Balanced (symmetric)		$Z_0=\frac{60}{\sqrt{{\epsilon }_r}}\ln \left[\frac{1.9(H+h+t)}{0.8w+t}\right]$	$C_0=\frac{1.41{\epsilon }_r}{\ln \left(3.81h/\left(0.8w+t\right)\right)}$
		OR
		$Z_0=\frac{60}{\sqrt{{\epsilon }_r}}\ln \left[\frac{1.9(2h+t)}{0.8w+t}\right]$
Differential (edge coupled)		$Z_{\mathrm{diff}}=2Z_0\left(1+0.347\times e^{-298/\left(2h+t\right)}\right)$
		Z0 same as symmetric stripline

Restrictions: w/(h−t) < 0.35 and w/h<2.0, t/h<0.25, and 0.005<w<0.015 in.

Table 6.5

Unbalanced stripline.

Stripline transmission lines		Z0(Ω)	C0 (pF/in.)
Unbalanced (asymmetric)		$Z_0=\frac{80}{\sqrt{{\epsilon }_r}}\ln \left[\frac{1.9(H+h+t)}{0.8w+t}\right]\left[1-\frac{h}{4(H+h+t)}\right]$	$C_0=\frac{2.82{\epsilon }_r}{\ln \left[\left(2(h-t)\right)/\left(0.268w+0.335t\right)\right]}$
Differential (broadside coupled)		$Z_{\mathrm{diff}}=\frac{82.2}{\sqrt{{\epsilon }_r}}\ln \left(\frac{5.98H}{0.8w+t}\right)(1-e^{-0.6h})$
		Z0 same as unbalanced stripline

Note: Unless otherwise noted, $L_0=\left(Z_0^2\times C_0\right)/1000$ in nH/in.

Source: Brooks, D. (2003). Signal integrity issues and printed circuit board design (p. 203). Upper Saddle River, NJ: Pearson Educational; IPC-2141A. (2004). Controlled impedance circuit boards and high speed logic design. Northbrook, IL: IPC-Association Connecting Electronics Industries; IPC-2221B (2012). Generic standard on printed board design. Northbrook, IL: IPC-Association Connecting Electronics Industries; Montrose, M.I. (1999). EMC and the printed circuit board: Design, theory, and layout made simple (2nd ed.; pp. 171–177) New York: IEEE Press.

Table 6.6

Microstrip transmission line configurations.

Microstrip transmission lines		Characteristics	Intrinsic propagation delay
Surface	Topology	Characteristic impedance	$t_{\mathrm{PD}}=84.75\sqrt{0.475{\epsilon }_r+0.67}(\mathrm{ps}/\mathrm{in}.)$
		$Z_0=\frac{k}{\sqrt{{\epsilon }_r+1.41}}\ln \left(\frac{5.98h}{0.8w+t}\right)\mathrm{ohms}$
		k=87 for 15<w<25 mil (IPC-2141A, 2004; IPC-2251, 2003, p. 32; Montrose, 1999, p. 172; Montrose, 2000, p. 101)
		k=79 for 5<w<15 mil (Montrose, 1999, p. 172; Montrose, 2000, p. 101)
		Restrictions
		0.1<w/h<3.0 (IPC-2251, 2003, p. 32)
		1<εr<15 (IPC-2251, 2003, p. 32)
		Design equations
		Trace routing width to use in PCB Editor
		$\mathrm{w}=7.475h\times {\mathrm{e}}^{(-Z_0\sqrt{{\epsilon }_r+1.41})/k}-1.25t$
		(use k=87, then check against width rules, use k=79 if necessary)
Surface differential	Topology	Characteristic impedance
		$Z_0=\frac{87}{\sqrt{{\epsilon }_r+1.41}}\ln \left(\frac{5.98h}{0.8w+t}\right)\mathrm{ohms}$	$t_{\mathrm{PD}}=84.75\sqrt{0.475{\epsilon }_r+0.67}(\mathrm{ps}/\mathrm{in}.)$
		(Same as surface microstrip) (IPC-2251, 2003, p. 36; Montrose, 1999, p. 177; Montrose, 2000, p. 107)
		Differential impedance
		$Z_{\mathrm{diff}}=2Z_0\left[1-0.48{\mathrm{e}}^{\left(-0.96\left(d/h\right)\right)}\right]\mathrm{ohm}$
		Restrictions
		None specifically noted except as applies to the surface microstrip
		Design equations
		Trace routing width to use in PCB Editor
		$w=7.475h\times e^{(\mathbf{-}{\mathrm{Z}}_0\sqrt{{\epsilon }_r+1.41})/k}\mathbf{-}1.25t$
		Trace separation:
		$d=\ln \left(2.08\frac{-1.04Z_{\mathrm{diff}}}{Z_0}\right)\left(\frac{-h}{0.96}\right)$
Embedded	Topology	Characteristic impedance
		$Z_0=\frac{87}{\sqrt{{\epsilon \prime }_r+1.41}}\ln \left(\frac{5.98h}{0.8w+t}\right)(\mathrm{ohms})$ (IPC-2141A, 2004; Montrose, 1999, p. 177; Montrose, 2000, p. 103)	$t_{\mathrm{PD}}=84.75\sqrt{{\epsilon \prime }_r}(\mathrm{ps}/\mathrm{in}.)$
		where ${\epsilon \prime }_r={\epsilon }_r\left[1+{\mathrm{e}}^{(\frac{-1.55H}{h_2})}\right]$
		OR	OR
		$Z_0=\frac{87}{\sqrt{{\epsilon }_r+1.41}}\ln \left(\frac{5.98h}{0.8w+t}\right)\left(1-\frac{h_1}{0.1}\right)(\mathrm{ohms})$ (IPC-2251, 2003, p. 32)	$t_{\mathrm{PD}}=84.75\sqrt{0.475{\epsilon }_r+0.67}(\mathrm{ps}/\mathrm{in}.)$ (IPC-2251, 2003, p. 32)
		Restrictions (IPC-2251, 2003, p. 33; Montrose, 2000, p. 103)
		0.1<wlh2<3.0
		1<εr<15
		Line widths: 0.127(5 mil)–0.381 mm (15 mil)
		Dielectric thickness: 0.127 (5 mil)–0.381 mm (15 mil)
		40<Z0<90 Ω
		Design equations
		Trace routing width to use in PCB Editor
		w=7.475h2×e−x−1.25t
		where
		$x=\frac{-Z_0\sqrt{{\epsilon \prime }_r+1.41}}{87}\mathrm{for}{Z}_0$ from (IPC-2141A, 2004; Montrose, 1999, p. 177; Montrose, 2000, p. 103)
		OR
		$x=\frac{-Z_0\sqrt{{\epsilon }_r+1.41}}{87\left(1-\left(h_1/0.1\right)\right)}\mathrm{for}{Z}_0$ from (IPC-2251, 2003, p. 32)
Embedded differential	Topology	Characteristic impedance
		$Z_0=\frac{87}{\sqrt{{\epsilon }_r+1.41}}\ln \left(\frac{5.98h}{0.8w+t}\right)\left(1-\frac{h_1}{0.1}\right)(\mathrm{ohms})$ (IPC-2251, 2003, p. 36)	$t_{\mathrm{PD}}=84.75\sqrt{0.475{\epsilon }_r+0.67}(\mathrm{ps}/\mathrm{in}.)$ (IPC-2251, 2003, p. 36)
		Differential impedance
		$Z_{\mathrm{diff}}=2Z_0[1-0.48{\mathrm{e}}^{\left(-0.96\left(d/\left(h_1+h_2+t\right)\right)\right)}](\mathrm{ohms})$
		Restrictions (IPC-2251, 2003, p. 36)
		Same as embedded microstrip
		Design equations
		Trace routing width to use in PCB Editor
		w=7.475h2×e−x−1.25t
		where
		$x=\frac{-Z_0\sqrt{{\epsilon \prime }_r+1.41}}{87\left(1-\left(h_1/0.1\right)\right)}$ (IPC-2251, 2003, p. 32)
		Trace separation of pair:
		$d=\ln \left(2.08-\frac{1.04Z_{\mathrm{diff}}}{Z_0}\right)\left[\frac{-(h_1+h_2+t)}{0.96}\right]$

Table 6.7

Stripline transmission line configurations.

Stripline transmission lines		Characteristics	Intrinsic propagation delay
Balanced (symmetric)	Topology	Characteristic impedance
		$Z_0=\frac{60}{\sqrt{{\epsilon }_r}}\ln \left(\frac{1.9H}{0.8w+t}\right)(\mathrm{ohms})[10,11]$	$t_{\mathrm{PD}}=84.75\sqrt{{\epsilon }_r}(\mathrm{ps}/\mathrm{in}.)$
		Restrictions
		Line widths: 0.127 (5 mil)–0.381 mm (15 mil)
		Dielectric thickness: 0.127 (5 mil)–0.381 mm (15 mil) 40<Z0<90 Ω
		Design equation
		Trace routing width in PCB Editor:
		$w=1.25\left[1.9H\times {\mathrm{e}}^{\left(-Z_0\sqrt{{\epsilon }_r}/60\right)}-t\right]$
Unbalanced (asymmetric)	Topology	Characteristic impedance
		$Z_0=\frac{80}{\sqrt{{\epsilon }_r}}\ln \left[\frac{1.9(2h_2+t)}{0.8w+t}\right]\left(1-\frac{h_2}{4(H)}\right)(\mathrm{ohms})$ (IPC-2251, 2003, p. 33; Montrose, 2000, p. 105)	$t_{\mathrm{PD}}=84.75\sqrt{{\epsilon }_r}(\mathrm{ps}/\mathrm{in}.)$
		Restrictions
		$\frac{w}{h_2-t}<0.35$
		$\frac{t}{h_2}<0.25$
		Design equation
		Trace routing width in PCB Editor
		w=2.375(2h2+t)e−x−1.25t
		where
		$x=\frac{Z_0\sqrt{{\epsilon }_r}}{80\left(1-h_2/4H\right)}$
Broadside coupled differential stripline (symmetric) (IPC-2251, 2003, p. 35)	Topology	Characteristic (between conductors) impedance
		$Z_0=\frac{82.2}{\sqrt{{\epsilon }_r}}\ln \left(\frac{5.98d}{0.8w+t}\right)(1-e^{(-0.6h)})\mathrm{ohms}$	$t_{\mathrm{PD}}=84.75\sqrt{{\epsilon }_r}(\mathrm{ps}/\mathrm{in}.)$
		Restrictions
		None given in the references
		Design equations
		Trace routing width to use in PCB Editor
		w=7.475d×e−x−1.25t
		Where
		$x=\frac{Z_0\sqrt{{\epsilon }_r}}{82.4(1-{\mathrm{e}}^{-0.6h})}$
Edge coupled differential stripline (symmetric) (IPC-2251, 2003, p. 35)	Topology	Characteristic impedance
For symmetric (h1=h2) or asymmetric (h1≠h2)		For symmetric (h1=h2)	$t_{\mathrm{PD}}=84.75\sqrt{{\epsilon }_r}(\mathrm{ps}/\mathrm{in}.)$
		$Z_0=\frac{60}{\sqrt{{\epsilon }_r}}\ln \left(\frac{1.9H}{0.8w+t}\right)(\mathrm{ohms})$
		For asymmetric (h1 ≠ h2)
		$Z_0=\frac{80}{\sqrt{{\epsilon }_r}}\ln \left[\frac{1.9(2h_2+t)}{0.8w+t}\right]\left(1-\frac{h_2}{4(H)}\right)(\mathrm{ohms})$ (IPC-2251, 2003, p. 33; Montrose, 2000, p. 105)
		Differential impedance (both)
		$Z_{\mathrm{diff}}=2Z_0\left[1-0.374{\mathrm{e}}^{\left(-2.9\left(d/H\right)\right)}\right]$
		Design equations
		Trace routing width to use in PCB Editor
		For symmetric (h1=h2)
		$w=1.25\left[1.9H\times {\mathrm{e}}^{\left(-Z_0\sqrt{{\epsilon }_r}/60\right)}-t\right]$
		For asymmetric (h1 ≠ h2)
		w=2.375(2h2+t)×e−x−1.25t
		where
		$x=\frac{Z_0\sqrt{{\epsilon }_r}}{80\left(1-h_2/4H\right)}$
		Trace separation in layer stack-up (for symmetric or asymmetric)
		$d=-0.347\ln \left[2.67\left(1-\frac{Z_{\mathrm{diff}}}{2Z_0}\right)\right]$

Reflections

So the next question is, What happens when the voltage “wave front,” V_line, reaches the termination impedance, Z_T? The answer is that it depends on what Z_T is.

Let’s assume for a minute that Z_T is an open circuit. When the last capacitor, C₅, in Fig. 6.18 is charged and V_line reaches Z_T (which equals infinity), then all capacitors are charged along the line (and their impedance equals infinity), so all current stops—or at least it would like to. But it cannot, because all of the inductors have current, I_line, through them and they will not allow I_line to stop instantly. As the magnetic fields of L₇ and L₈ begin to collapse to try to maintain their current (remember that they are mutually coupled and influence each other), they continue to shove current into C₅, raising its voltage a bit more (we will see later what a bit more means).

The magnetic fields of each inductor pair (L₃ and L₄, L₁ and L₂, etc.) will collapse, one after the next, back toward the source and raise the voltage of its nearest capacitor, all the way down the line. This new voltage front (V_line+a bit more) propagates back from Z_T toward the source with the collapsing magnetic fields until all of the magnetic fields have collapsed and all of the capacitors have this new charge on them. An analogy of a reflection from a high-impedance termination is shown in Fig. 6.22, which shows a person launching a wave into a rope. If the rope experiences little or no friction, the wave will propagate down the rope unattenuated. If the end of the rope is loose (a high impedance), the wave will be reflected back toward the person, who will feel an identical wave returned.

In the example above the reflected wave has the same polarity and amplitude of the transmitted (incident) wave. In reality the rope would not be in a frictionless environment (and Z_T would not be infinitely high). In that case the reflected wave would still have the same polarity as the incident wave but the amplitude would be less.

The magnitude and polarity of the reflected wave are described by the reflection coefficient, ρ (Greek letter r), as shown in Eq. (6.14):

$\rho =\frac{Z_T-Z_{\mathrm{line}}}{Z_T+Z_{\mathrm{line}}}.$ (6.14)

(6.14)

The reflection coefficient can have values between −1 and +1. If Z_T>Z_line (i.e., as Z_T approaches ∞, as in the example above), then

$\rho \cong \frac{Z_T}{Z_T}=1,$

which means that the reflected wave will be exactly the same amplitude and have the same polarity as the incident wave.

Next we consider what happens if Z_T (in Fig. 6.18) is a short circuit instead of an open circuit. At first the exact same thing occurs as described above when the switch is shut. That is (assuming the same initial conditions as above, all caps are discharged, etc.), the capacitors and inductors take their turn charging up and building up magnetic fields, V_line is applied to the line, current I_line. flows, and Z_Cn=V_line/I_Cn. So the instantaneous line impedance is equivalent to Z_Cn. A different result occurs at the end of the transmission line. Since Z_T=0 Ω and inductors L₇ and L₈ again want to maintain their current flow, I_line flows straight through the short, Z_T.

Since the current through L₇ and L₈ is maintained (even for just an instant) and since the voltage drop across an inductor with a constant current flow is zero, capacitor C₄ sees the short and begins to discharge through L₇ and L₈ (helping to maintain their current flow) and on through the short, Z_T. A short moment later C₄ is at the same potential as C₅ and Z_T (0 V), while L₇ and L₈ have managed to maintain their current. The capacitors continue to discharge one after the other (C₃ then C₂, etc.) and each inductor pair maintains its current until finally all capacitors are shorted (and all the inductors look like a short if they have the same constant current). In the final analysis, V_line=V_ZT=0 V and therefore Z_line=0/I_line=0 Ω and I_line=V_s/R_s.

A mechanical analogy of a wave reflected negatively from a “dead short” is shown in Fig. 6.23. If a positive wave is launched into a rope that is rigidly fixed at the end, the wave will be negatively reflected. In a perfectly lossless environment, the reflected wave will be of the same magnitude but opposite polarity as the incident wave.

In the electrical example above, the negatively reflected wave has the same magnitude as but opposite polarity to the voltage stored on the capacitors. As the negative wave hits each capacitor, it is forced to give up its charge (as current), which helps maintain the current flow through the nearest inductors and all the way down the line through the short at the end of the line. This negatively reflected wave is again represented mathematically by the reflection coefficient [Eq. (6.14)], but in this case since Z_T<Z_line (i.e., as Z_T approaches 0), ρ=−1, as shown in Eq. (6.15) the following equation:

$\rho =\frac{-Z_{\mathrm{line}}}{Z_{\mathrm{line}}}=-1.$ (6.15)

(6.15)

Now let’s say for argument that the characteristics of our transmission line are such that when we calculate Z_Cn=V_line/I_Cn at each capacitor/inductor section, Z_Cn=50 Ω. Let us also set R_s to 50 Ω. Now what happens when Z_T=50 Ω? As you can suppose by this time, at the moment the switch is shut, the capacitors take their turn getting charged (and the inductors are building their fields). Since each Z_Cn=50 Ω, then Z_line is also 50 Ω. Since R_s and Z_line are equal (and act as a voltage divider), V_line=1/2V_s. Once the wave front has propagated down the line and reaches Z_T, which is also 50 Ω, I_line continues to flow into Z_T as if nothing different has occurred and V_ZT=V_line=1/2V_s. As long as Z_T is purely resistive, then everything is at steady state and Z_line=Z_T=50 Ω. Also no voltage is reflected back toward the source because no change in voltage occurred on the capacitors and no current change occurred in the inductors.

In this case, since Z_T=Z_line the reflection coefficient is 0 (ρ=0) as shown in Eq. (6.16):

$\rho =\frac{0}{Z_T+Z_{\mathrm{line}}}=0.$ (6.16)

(6.16)

The mechanical analogy is shown in Fig. 6.24, in which none of the wave energy is reflected but is perfectly absorbed into the load at the end of the line.

From these examples we can conclude that Z_line is in effect only during voltage transitions and is the result of the voltage and the current transients that flow to charge the line capacitance to the new voltage and to build the magnetic fields in the inductors. We can also see that, if the impedance Z_T is not the same as Z₀, then a reflection will occur, but if the impedance Z_T is the same as Z₀, then no reflection will occur. Furthermore it takes a finite amount of time for a wave front to propagate from one end of a transmission line to the other, and if a reflection does occur it takes another finite amount of time for the reflection to propagate back to the source. What happens at the source is the next topic.

Ringing

When ρ≠0 between any adjacent impedances, reflections will occur. This is true both from driver to transmission line and from transmission line to load (and back). If there is little or no loss along the transmission line, the reflected waves will bounce back and forth between the driver and the load if they are not matched to the transmission line (or if the transmission line is not matched to them). When viewing a particular point along the path, for example at the output pin of a gate or amplifier, the repeated reflections will be evident as ringing. Ringing is a direct result of reflections, which in turn are due to impedance mismatches.

One of the problems with ringing is that the voltage at any point along the line is effectively out of control, since ringing causes voltage overshoots and undershoots (see Fig. 6.26). Overshoots can actually damage active devices that have input voltage limitations and will radiate greater EMI than normal signals. Overshoots and undershoots can cause digital circuits to be falsely triggered if the reflected voltage swings across switching thresholds. In analog circuits the interactions between a continuous wave signal and its reflections creates standing and/or traveling waves that can degrade the signal of interest.

The magnitude and frequency of the ringing depend on the speed of the wave through the transmission line, the length of the line, and the reflection coefficient at each impedance discontinuity. We take a detailed look at ringing using the circuit shown in Fig. 6.25.

The circuit consists of a driver that is powered by V_CC and has a low output impedance, R_S (10 Ω); a transmission line with a characteristic impedance, Z₀ (50 Ω); and a receiver with a high input impedance, R_L (usually 1 kΩ or higher). The dashed lines indicate the interfaces of the mismatched impedances and are labeled as ZX₁, and ZX₂. The dimensions in green represent length, and the dimensions in blue represent time. The circuit in the figure can be used to represent an analog or digital circuit, but we will consider the digital application.

Consider the following:

Electrically long traces

The goal is to design PCB traces such that they do not allow conditions to exist under which PTs are too slow (compared to signal RTs) or a trace’s length is too long (compared to a signal’s spatial extent). When these conditions cannot be met, the trace is considered to be “electrically long” and must be treated as a transmission line. Proper treatment of a transmission line means controlling the impedance of the line over the entire length of the line and matching the impedance of the line with the source and load impedances so that reflections do not occur.

The obvious question is, when is a trace too long (or when is the RT too fast)? The magnitude of reflections and the ringing frequency are governed by the down and back (round trip) time of the reflections. Much of the literature states that the PT, should be less than one-half of the rise time (i.e., PT<1/2RT) or that the length of the trace should be less than one-half of the special extent of a rising edge (i.e., L_trace<1/2L_SE). These relationships define the limits, not the goal. The shorter trace lengths are or the slower the RT is, the better off you will be. The examples below illustrate this in greater detail. After the examples general design recommendations are provided.

Fig. 6.26 shows what happens when PT is too long compared to RT. The data in the figure were generated using the transmission line model found in PSpice, and the PT was set four times longer than the RT (instead of being <1/2RT). Refer to Figs. 6.25 and 6.26 during the discussion.

The reflections continue back and forth but decrease in value each trip. The losses occur because the energy that is not reflected at each impedance interface is absorbed into the source and load resistors. Eventually, the reflections become too small to notice and we say that it has reached steady state. The time to reach steady state is called the settling time and the shorter the settling time, the better.

If the length of the trace, L_trace, is much shorter than the special extent of L_SE (as represented in Fig. 6.27), then the rising edge will not fit within the length of the trace and will reach the driver before the driver has even completely reached is steady-state value. If the trace is very short, the reflection voltage will be reflected many times and repeatedly fold back onto itself as the driver output climbs to its steady-state value. Since the voltage at an interface is the sum of its existing voltage, the incoming reflection, and the reflected reflection, the effects of the reflections become “smeared” into each other. By the time the driver has fully reached its final value most of the reflections have come and gone and only the last, smaller overshoots and undershoots are evident.

Fig. 6.28 shows what happens when PT is much shorter than RT on an electrically short trace. The reflections occur as previously described, but as shown in the graph many of the reflections have occurred by the time the driver reaches its full output level. Recall that the voltage at each impedance interface is the sum of its previous voltage plus the incoming voltage plus the reflected voltage, but since the reflections happen fast (relative to the rise time), each reflection never has a chance to reach its full voltage level (only a fraction of the rising edge at that time), so the reflections are much smaller and therefore the peaks (overshoots) and valleys (undershoots) are also much smaller (hardly noticeable), while the driver output is still rising. Also the ring frequency is higher with the shorter trace.

Critical length

As mentioned above an electrically short trace is one for which the PT is less than one-half of the rise time (i.e., PT<1/2RT) or the length of the trace is less than one-half of the special extent of a rising edge (i.e., L_trace<1/2L_SE). The length of a trace or transmission line for which these conditions are just barely met is called the critical length. Fig. 6.29 shows the voltage levels at critical length. Ringing still occurs, but the peaks never level off and the reflections settle sooner. But again the one-half rule is a limit and not a goal. Examples of determining critical length and designing transmission lines are given in the design section below and in Example 4 in the PCB Design Examples.

Transmission line terminations

If we cannot make the rise time slower and/or the length of the trace shorter, then we will have noticeable reflections and ringing. The only other way to stop the reflections and ringing is to eliminate the impedance mismatches that are causing them by properly terminating the ends of the transmission line with the proper source and/or load resistors.

We can make R_s=Z₀=R_L by using a resistor in series with the source and a resistor in parallel with the load.

If the impedances are all matched then there will be no reflections, as shown in Fig. 6.30. However, only half the voltage will reach the load because a voltage divider results with R_S equal to R_L so V_load=1/2V_source. This lower voltage at the load may not reach required logic thresholds, preventing affected digital circuits from functioning.

An alternative is to put a resistor in series with the driver such that the impedance that the transmission line sees looking at the driver and series resistor is equal to Z₀. So if Z₀ is 50 Ω and the driver output resistance is 10 Ω, then the transmission line will be matched to the driver by putting a 40-Ω resistor in series with R_s. An example of the result is shown in Fig. 6.31. Even when PT is>1/2RT, only one reflection occurs (the fiat section on V_drive between 10 and 20 ns), and it is absorbed into the 40-Ω resistor and R_s, so the reflection dies there. An advantage of this type of termination technique is that the voltage at the load is also much closer to the ideal voltage. The momentary hold on V_drive is usually not a problem, but it can be a problem in high-speed clock circuits for which the steady-state on (off) time is about the same duration as the rise time.

To match impedances between the source and the transmission line, place a resistor in series with the driver such that R_series=Z₀−R_s.

To match impedances between the transmission line and the load, place a resistor in parallel with the load such that R_parallel=(R_LZ₀)/(R_L−Z₀).

Parts placement for electrical considerations

Chapter 5, Introduction to design for manufacturing, addressed parts placement with manufacturability in mind. Here we consider parts placement with electrical performance in mind. Usually the two goals complement each other, but occasionally they conflict. When conflicts do occur, an attempt should be made to resolve the conflict in a way that is mutually beneficial. If that is not possible, electrical considerations usually have priority over mechanical considerations unless doing so will result in a mechanical failure of the board. For example, it may be necessary to manipulate the assembly or soldering processes or place parts on both sides of the board in order to meet manufacturability requirements and meet electrical performance requirements. Whatever solution is chosen, the PCB needs to be manufacturable and operational.

Aside from manufacturability goals the first approach to placing parts for electrical considerations is usually determined by the function of the circuit. This is especially true for analog circuits where a signal enters the PCB, flows through the circuitry in more or less a single path (including feedback networks), and then leaves the board. Since analog circuits are susceptible to noise the goal is usually to place the parts to minimize the possibility of degrading the signals. This usually means keeping the parts as close together as possible so that the traces can be as short as possible and keeping the signal path as straight as possible (not zigzagging back and forth or from one side of the board to the other). This approach may increase the size of the board, however, and is not always possible.

With digital circuits it is also desirable to keep related parts close together and lines short, but because digital circuits often contain many parallel paths and branches and may contain wide data busses it may be nearly impossible to do so. Sometimes the best that can be accomplished is to keep parts that are functionally related closer together or place parts together that have the highest speed clocks and rising edges in order to minimize the length of related signal lines.

Mixed signal boards are even more challenging, in that both analog and digital circuits and high-power circuits (such as switching regulators) exist on the same board. In these cases the PCB should be segregated into different areas as shown in Fig. 6.32. The topology may vary, but the idea is to keep the higher power and other noisy circuitry closer to the connector if possible. This limits the amount of return plane that is utilized by these circuits and therefore minimizes the amount of return plane that is common between them and the rest of the circuitry. Digital and analog circuits should also be kept apart from each other to minimize the effects of switching noise on analog circuitry. When dividing the PCB in this way, it is usually necessary (and beneficial) to set up split and isolated plane layers as shown in Fig. 6.15.

PCB layer stack-up

Although PCB Editor’s Cross-section Editor dialog box allows you to define a stack-up, the PCB layer stack-up and thicknesses are really assigned when the board is ordered from the manufacturer. But the PCB layer stack-up and thickness need to be defined early in the design stage before working in PCB Editor, since the stack-up will determine how many layers to enable and how many power and ground planes to establish. The strategy for stacking up a PCB depends on a number of things such as the capabilities of your board manufacturer, the circuit density (both routing and parts), the frequency (analog) and rise/fall times (digital) of the signals, and the acceptable cost of the board.

As circuits become more dense, additional routing and plane layers are required. Digital circuits commonly require more layers than analog circuits because digital circuits typically consist of parts with greater numbers of pins per chip and because they have a higher number of parallel interconnections. High-speed circuits (whether analog or digital) may require a greater number of layers even if they are not very dense. This is because multilayer boards can provide better impedance control and shielding since they can have additional ground planes. The more layers a board has, the more it costs, but once a PCB stack-up exceeds four layers, the cost increase per layer usually becomes less for additional layers (to a point). Additionally the benefits of shielding and impedance control can considerably outweigh the increased cost of extra layers.

There are many possible ways to design the stack-up. If the board will be operated at low speeds and in an isolated environment almost anything you can dream up will work. However, as signal speeds increase the layer stack-up and trace routing become increasingly important because a poorly designed stack-up can lead to reflections and excessive EMI radiation (affecting external circuits as well as causing self-inflicted cross talk). A well-designed layer stack-up (and proper routing) not only minimizes the energy it radiates, but also can make your circuit relatively immune from external sources of radiation. In designing a layer stack-up there are only a few guidelines to follow, but they are important. The following few paragraphs and the examples demonstrate the guidelines.

Since PCBs are constructed of double-sided cores bonded together with prepreg, multilayer PCBs usually contain an even number of layers. Odd-layered boards can be made, but in most cases there is no cost benefit to adding only one layer instead of a layer pair (e.g., if you need five layers you may as well go with six). The extra layer can be an extra return/ground plane and the symmetry of an even number of layers helps minimize board warpage.

A signal layer should always be adjacent (and close) to a plane layer (preferably a return/GND plane) to minimize loop inductance, which minimizes electromagnetic radiation and cross talk. Power planes should also be adjacent (and close) to a return plane as this adds interplane capacitance, which helps minimize power supply noise and radiation. If you have to choose between a signal layer being adjacent to the return plane and a power plane being adjacent to the return plane, choose the signal layer. You can add more bypass and bulk capacitors between the power planes to make up for the loss in interplane capacitance.

The following stack-up examples are offered as a reference only. There are many more combinations possible, but only a few are shown here (please see the references for additional examples and details). The final board thickness in the examples is 0.093 in. and the copper is 1 oz (1.35 mil) thick. The availability of certain dimensions will depend on the manufacturer’s capabilities and specific processes.

The thicknesses listed in the figures are given to provide perspective. You can use Tables 4.3–4.5 to get an idea of the different combinations of cores and prepreg types used to make up different layer thicknesses, but remember that the thicknesses from the tables are preassembly thicknesses, and finished thicknesses may vary since traces sink into the soft prepreg, while plane layers do not (see the Advanced Circuits Web site, www.4pcb.com, the ELLWEST Printed Circuit Boards Web site, www.ellwest-pcb.com, or other PCB suppliers websites, for examples of layer thicknesses).

A signal’s return current will be on the ground or power plane that is closest to the signal line (if possible), and the relative dimensions determine the trace/plane routing pairs. Ideally all return currents will need to end up at the ground/return pin on the PCB’s power connector. It may be beneficial to stack up and route your PCB to try to make it easier for the return currents of critical high-speed traces to be paired up with certain ground planes (so that they are not forced to go through capacitor leads or vias to get back to the ultimate return point), but there is no guarantee they will follow it. But remember that to an AC signal there is no real difference between the power plane and the ground plane because they are shorted together with bulk and bypass capacitors. So when signal traces transition from one layer to another, the return currents may not have an easy path from one ground plane to another and may choose to return to the source on a power plane until they find a convenient path back to the preferred ground plane through a bypass capacitor. While the return current is not flowing on the preferred plane, the impedance of a transmission line can be significantly different from what is expected. To assist the return current in staying with the signal line when it changes layers, return current bridges can be installed by using free vias connected to the ground planes or capacitors with fan-out vias near vias used to transition signals from one layer to another.

There are several symbols that need to be defined with regard to the stack-up figures. The H in the figures implies horizontal routing and the V implies vertical routing. In some of the figures, an R is used to imply nonspecific routing direction. Concentrating the routing strategies in horizontal or vertical directions makes the routing process more efficient in high-density designs and reduces the number of vias required to complete the connections. The symbol HS is used to imply high-speed signals that are usually buried between plane layers for extra shielding. The GND symbol is used to represent any ground or return plane (for signal or power). The symbols PWR or ±PWR represent any power plane, such as +5 V V_CC for digital circuits or +V and −V for analog circuits.

There are three basic types of transmission lines: microstrip, stripline, and coplanar. You may not always need a transmission line, but no matter how you route your board one of these types will be represented (even if it is not a close resemblance). Other types of transmission line configurations can be realized by other types of stack-ups, which are not shown here as they will depend on the capabilities and processes of your board manufacturer.

Fig. 6.33 shows three different four-layer stack-ups. Indicated thickness is in mils.

Fig. 6.33A is one of the most common four-layer stack-ups for simple digital or analog PCBs. The land patterns and traces are placed on the outside (top and bottom) of the board and the power and return planes are inside. Placing the traces on the outside enables postfabrication inspection and troubleshooting.

Fig. 6.33B and C places the power and return planes on the outside of the board and the traces on the inside. This arrangement helps shield the traces from outside EMI and helps contain self-generated radiation between the planes and consequently minimizes radiated EMI. The configuration in Fig. 6.33C can be used to route low-density analog circuits that require ±V for dual-supply op amps. Power is routed to the amplifiers with wide traces or copper pours and shares the layers used for routing signals.

Fig. 6.34 shows examples of six-layer PCB stack-ups. Fig. 6.34A is a typical stack-up for digital circuits or analog circuits that do not require dual-power supplies. This arrangement provides four routing layers and two plane layers. The inner routing layers can be used for the higher speed signals since they are shielded by the ground and power planes. For analog circuits that require dual-power planes, the stack-up in Fig. 6.34B provides a highly functional stack-up with two full routing layers, two partial routing layers (which share layers with the +PWR and −PWR layers), and ground planes that are adjacent to all signal and power layers and provide shielding for the inner signal traces. Alternatively the shared power and routing layers can be dedicated to power only, but this limits the board to two routing layers. The stack-up in Fig. 6.34C provides two well-shielded, balanced stripline routing layers for high-speed digital circuits and adjacent ground planes for each of the signal and power layers. A limitation of this stack-up is that there are only two routing layers.

Figs. 6.35 and 6.36 show examples of 8- and 10-layer stack-ups, respectively. Only a few examples are shown, but by using the different stack-up strategies of the previous examples and capitalizing on the various finished board thicknesses available from most board manufacturers, it can be seen that the higher layer stack-ups can provide a multitude of routing possibilities.

Bypass capacitors and fan-out

Bypass capacitors serve two main functions, namely to short high-frequency noise to ground and to act as current reservoirs. Consequently there are three basic methods to fan-out power pins. The first method usually occurs when the autorouter is used to create the fan-outs automatically. The autorouter creates individual fan-out vias for the IC’s power and ground pins, and it creates individual fan-out vias for each pin on the bypass capacitor (resulting in no direct trace connection between the IC and its capacitor). In general this is acceptable. The second method is to deliberately route the power pin to the bypass capacitor before the fan-out via and to the power plane as Fig. 6.37A shows, and the third method is to route the power pin to the power plane first by placing the fan-out via between the power pin and the bypass capacitor as shown in Fig. 6.37B.

At first glance there may appear to be no difference electrically speaking, but the differences can be significant at high frequencies and fast rise times. Additionally, other issues such as the method of assembly (wave vs reflow soldering) and the available board real estate often influence orientation and routing of bypass capacitors. Sources in the literature do not all agree with which method is best, but more often Fig. 6.37A is recommended for analog circuits and Fig. 6.37B for digital circuits.

Trace width for current-carrying capability

When current flows through a conductor, it will heat up due to I²R losses. Wider traces exhibit less resistance and therefore less heating. To determine the minimum trace width required to minimize heating, determine the maximum current a trace will carry and the thickness of the copper you will use on your board. Use Eq. (6.17) to calculate the minimum trace width,

$w=\left(\frac{1}{1.4\times h}\right)\times {\left(\frac{I}{k\times \mathrm{\Delta }{T}^{0.421}}\right)}^{1.379}$ (6.17)

(6.17)

where w is the minimum trace width (in mils), h is the thickness of the copper cladding (in oz/ft²), I is the current load of the trace (in A), k=0.024 is used for inner layers and k=0.048 is used for outer (top or bottom) layers, and ΔT is the maximum permissible rise in temperature (°C) of the conductor above ambient temperature. You can also use the graph shown in Fig. 6.38, which was derived from curves in IPC-2221B.

Note: The glass transition temperature for FR4 is 125°C–135°C, so as ambient temperature increases, the allowed ΔT decreases and minimum trace width increases. Even if the board will be at room temperature, giving you a ΔT=108°C, it does not hurt to restrict the temperature rise intentionally just to be safe (e.g., specify ΔT=20°C even if it could be much higher).

Note: Eq. (6.17) was derived from the IPC-2221B standard. Please refer to the standard for the actual equation and additional details.

You can usually use any of the standard technology files for most small signal applications. Fig. 6.38 shows the minimum trace widths for l-oz inner and outer layer copper with ΔT=10°C. With 6-mil traces you can run up to about 300 mA on inner traces and about 600 mA on the outer traces, but for manufacturability and reliability considerations, they should be as wide as practical. Usually the applications of concern are power supply lines for large circuits and power supply boards in general.

Trace width for controlled impedance

Controlled impedance PCB can be significantly more expensive than standard process PCBs. Before going through the effort and expense of designing controlled impedance transmission lines on the PCB, it is a good idea to determine if they are needed by determining if traces are electrically long (and whether controlled impedance is required).

For digital systems, at a minimum, we want the PT, to be less than the rise time of the driver (i.e., PT<1/2RT or RT>2PT). From the discussion under Reflections another way to look at it is that the length of the trace, L_trace, should be less than one-half of the special extent (edge distance) of the rising edge (i.e., L_trace<1/2L_SE or L_SE>2L_trace). To determine if this condition is met we need to determine RT and PT. RT (or fall time—FT) can be obtained from the data sheet for the device that is driving the trace and will have units of time (e.g., nanoseconds). Note that, since both the rise and the fall times must fall within limits, the smaller value should be used in the calculations. The RT and FT of several logic families are listed in Appendix C.

To calculate PT, we need to know the intrinsic propagation delay (t_PD), which has units of time/distance. The intrinsic propagation delay for various transmission line configurations is given in Tables 6.6 and 6.7. Bracketed numbers (IPC-2141A, 2004; IPC-2251, 2003, pp. 32, 33, 35, 36; Montrose, 1999, pp. 172, 177, Montrose, 2000, pp. 101, 103, 105, 107) refer to the numbered references at the end of the chapter.

Trace spacing for voltage withstanding

There are two reasons for controlling the spacing between traces: (1) to ensure adequate voltage-withstanding capability (insulation resistance) between high voltage lines and (2) to minimize cross talk between signal lines. Table 6.8, which is an abridged version of a similar table given in IPC-2221B (Table 6-1), shows the required trace spacing for various voltage ranges on internal and external layers. The spacing on external traces depends on both the voltage and the external coating of the board.

Trace spacing to minimize cross talk (3w rule)

The default trace spacing used in PCB Editor’s Constraint Manager is shown in Fig. 6.40A, in which the edge-to-edge spacing between traces is typically one conductor width. If a trace is susceptible to cross talk from adjacent traces then it should be kept a minimum of two trace widths (edge to edge) from the other traces, as shown in Fig. 6.40B. This is referred to in the references as the 3w rule because the center-to-center spacing is 3w, as indicated in Fig. 6.40B. At 3w, the traces are out of reach of about 70% of each other’s magnetic field if the traces are controlled impedance transmission lines (or reasonable approximations). Keeping the traces 10w apart at the centers will keep the traces out of about 98% of each other’s field (Montrose, 1999, p. 210).

To adjust the trace-to-trace spacing in PCB Editor select the Constraint Manager button on the tool bar to display the Constraint Manager as shown in Fig. 6.41. Select the Spacing tab and the Line icon as shown. Enter the edge-to-edge spacing in the Default row or click the “+” box and enter edge-to-edge values for specific nets.

Traces with acute and 90 degree angles

Routing high-frequency analog or high-speed digital traces with acute or 90 degree angles has long been discouraged, but not everyone agrees anymore as to how much of a problem it really is (see Bogatin, 2004, p. 317; Brooks, 2003, p. 383; Johnson & Graham, 1993, p. 174; Montrose, 2000, p. 220). The argument is that the trace width increases by a factor of 1.414 at the corner of the trace (as shown in Fig. 6.42) and causes a change in the characteristic impedance (due to an increase in capacitance) of the trace. As discussed above impedance mismatches cause reflections. The reflections in turn cause ringing in digital circuits with fast rise times and standing or traveling waves in high-frequency analog circuits. In theory then, 90 degree corners should be avoided—at least when routing controlled impedance transmission lines.

A look through the references shows that, when using high-end network analyzers and time domain reflectometers to measure the reflection from a 90 degree corner, the effects are evident (Bogatin, 2004, p. 318). However, the frequencies at which the reflections occur are high (into the upper gigahertz for traces greater than 50 mil wide and tetrahertz for traces less than 10 mil), and compared to other sources of impedance discontinuities (such as vias), the effects are insignificant.

Another thing to consider is that (with PCB Editor anyway) the corners are not as sharp as shown in Fig. 6.42. Recall from Chapter 1, Introduction to PCB design and computer-aided design, that pads and traces are drawn as flashes or draws, respectively, by photoplotters with apertures of a given diameter. While square apertures can be used (and are for square pads), PCB Editor uses round apertures for traces in the Gerber codes. A 90 degree corner produced by PCB Editor is shown in Fig. 6.43A. Although the corner may look fairly sharp, a close-up of the corner shown in Fig. 6.43B shows that the outer edge is rounded and only the inner corner is square. This results in a smaller increase in width than with a square corner.

The difference between a 12-mil trace and a 17-mil trace (at the sharp corner in Fig. 6.42) is about 11.5 Ω for a dielectric constant of 4.2 and a core thickness of 10 mil, and the difference between the 12-mil trace and a 14.5-mil trace (at the rounded corner in Fig. 6.43) is about 6.2 Ω. However, the effect of extra width (and change in impedance) is very small. The excess area shown in Fig. 6.43B is 7.73 mil² for a 12-mil trace. If the equivalent area is divided by 2 and each piece is placed on either side of a straight segment of a 12-mil trace (as indicated by the arrow in Fig. 6.44) it is clear that the excess area created by the 90 degree corner is insignificant compared to other factors such as vias and land patterns. The literature (Brooks, 2003, p. 385) suggests that even acute angles of 135 degrees can be used up to about 1 GHz.

Simulating digital transmission lines

The value TD is the same as PT from the earlier discussion and is calculated by

$\mathrm{TD}=t_{\mathrm{PD}}\times {\mathrm{Length}}_{\mathrm{trace}}$

where t_PD is found from Tables 6.6 and 6.7. For the surface microstrip t_PD is

$t_{\mathrm{PD}}=85\sqrt{0.475{\epsilon }_{\mathrm{r}}+0.67}.$

In laying out a digital circuit (for instance the digital design example in the PCB Design Examples in Chapter 9), it is important to know the critical trace length so that traces can be kept short enough and parts can be placed accordingly. The critical trace length is calculated by

${\mathrm{Length}}_{\mathrm{trace}}<\frac{\mathrm{RT}}{k\times t_{\mathrm{PD}}},$

where k is a safety factor and is essentially the ratio PT/RT. The maximum trace length recommended is k=2; larger values of k (shorter traces) are better.

For ALS family logic RT is approximately 2 ns. Using ε_r=4.2 the critical trace length is then 7.3 in. Table 6.9 shows the effective k value and TD for various transmission line lengths.

Knowing RT (2 ns) and TD (from Table 6.9), we can use PSpice to simulate the various transmission line lengths. Set up the PSpice simulation as shown in Fig. 6.46. To display the Simulation Settings dialog box select Edit Simulation Profile from the PSpice menu. Note: If the step time is too large, the simulation may become unstable and you will not get good results. A maximum step size of 1/1000 of the total run time usually produces satisfactory results. Click OK.

To start the simulation, press the blue triangle on the menu bar, or press F11 on the keyboard, or select Run from the PSpice menu. The results are shown in Figs. 6.47–6.49.

Simulating analog signals

For analog signals f is the frequency on the trace and NL is the length of the trace in relative wavelengths (e.g., NL would be 0.25 for a quarter wavelength trace at frequency f). To determine NL you need to know the wavelength, λ. You can calculate the wavelength using Eq. (6.21):

$\lambda =\frac{v_{\mathrm{PD}}}{f}=\frac{1}{f\times t_{\mathrm{PD}}}$ (6.21)

(6.21)

where v_PD is the propagation velocity (distance/time) of a wave through a dielectric; f is the frequency of the wave; t_PD is the PT (time/distance) as described above.

So for a 66-MHz signal traveling through the same surface microstrip from the above example (ε_r=4.2), λ=110.8 in. The critical length for traces carrying analog signals varies depending on which book you read but is often cited as being λ/6, λ/15, or λ/20 (or somewhere in between). As with the digital signals, the shorter the trace, the better.