Characteristic Impedance
It was stated earlier that to minimize cross talk we want to minimize trace (loop) inductance and maximize the capacitance to the return plane. What does this do to the characteristic impedance,
Z0, of a trace?
Perhaps the first thing to do is to look at what characteristic impedance really is. For example RG58 is a coaxial cable that is often used as a shielded transmission
line in 50-Ω systems. Actually, RG58 is about 52
Ω, not 50
Ω. But even so, what does that mean? If you use an ohmmeter to measure the resistance from the center conductor to the shield you will see that it is neither 52 nor 50
Ω. So how is its characteristic impedance 52
Ω?
Figure 6-18 shows a model of a transmission line, which consists of series inductors and parallel capacitors. This is called the
lumped-element model, which assumes that the series resistance is negligibly small and that the transmission line is infinitely long (or at least long enough to watch what happens). Each
LC“lump” represents a finite section of the transmission line, and the sum total of the elements is representative of the total inductance and capacitance of the transmission line.
We begin the analysis with all of the capacitors discharged and all currents at zero. At time
t = 0
s the switch is shut, which applies the source voltage,
VS, to the transmission line through the source resistance
R
s as shown in
Figure 6-19. Initially
C1 acts as a short circuit so
I =
V
S/R
S. Current,
I, begins to charge capacitor
C1, and a return current will also flow out of the bottom of
C1 back to the source (note that this is a
displacement current as postulated by Maxwell
rather than a
conduction current as defined by Ampere). The instantaneous impedance is
Z
C1=
Vline/
I.
As
C1 charges (no longer acting like a short), current begins to flow into
L1. Each inductor pair (
L1 and
L2,
L3 and
L4, etc.) is mutually coupled, so the magnetic field of
L1 induces the return current in
L2.
As current flows past
L1,
C2 begins charging positively on the top side; and as
L2 forces return current to flow back to the source (due to mutual inductance),
C2 begins charging negatively on the bottom side (relative to its top lead).
At some point
C1 becomes fully charged to a value of
V
C1 =
Vline =
V
S−
I×
RS and then the displacement current no longer flows through
C1, so the instantaneous impedance at
C1 is
Z
C1 = ∞ and
Z
C2 = V
line/
I. Current continues down the line, charging up each capacitor in turn to a value of
V
Cn =
Vline.
As each capacitor along the way is charging, the instantaneous impedance across the line is
Z
Cn =
Vline/I
Cn as shown in
Figure 6-20. As each capacitor becomes fully charged, its impedance goes to infinity because the displacement current through it goes to zero. As seen from the source (
V
S) the impedance of the line is
Zline =
Vline/
I =
Vline/
I
Cn and is dynamic since it travels along the line. Furthermore, the impedance farther down the line is unknown.
The speed at which the instantaneous impedance travels along the line is dependent on the inductance and the capacitance of each section. It was said above it is desirable to have as little loop inductance as possible (which will never be zero) and as much capacitance as possible (which will never be infinite). Thus there will always be finite inductive reactance (
X1) and capacitive reactance (
X
C) during any transient. However, the capacitors that are charged have nothing to do with the impedance (since they look like open circuits) and the inductors that have steady-state current flowing through them have nothing to do with the impedance (since they look like shorts). The capacitors and inductors farther down the line have nothing to do with the impedance either, since they do not see any action until the capacitors and inductors before them have approached a steady-state condition. Until the voltage (
Vline) reaches the load,
Z
T, the source actually has no idea the load,
Z
T, even exists; neither does it know how many sections of
L and
C there are until all of the previous sections have reached steady state. If the impedance of each section is the same all along the line, then we call the instantaneous impedance the characteristic impedance of the transmission line and give it the special symbol
Z0.
Before we consider what happens to the current flow and line voltage in
Figure 6-20 once all of the capacitors are charged and the line voltage and current reach
Z
T, we need to take a closer look at the behavior of the transmission line. From the above discussion we see that it takes a finite amount of time for the applied voltage (minus the voltage drop,
V
Rs) to propagate down the line, and, as the applied voltage propagates, it essentially behaves as a wave. In fact the effects described here are due to wave properties and not directly due to electrons flowing (at least not like we normally think of them). The key to understanding
Z0 (and reflections and ringing, as we will see shortly) is in understanding how and at what speed the waves travel.
If you ask an average person how fast electricity travels, you will usually get the answer that it travels at the speed of light. Except in one particular case, that answer is not correct. If we think of electricity as flowing electrons, then electricity actually travels at only about 1
cm/s (
Bogatin 2004, p. 211), pretty slow really. This seems counterintuitive since when we turn on a light switch the lights come on seemingly immediately, as if the “electricity” traveled at the speed of light from the switch to the light bulb. But what does travel at (almost) the speed of light is the electromagnetic wave that is launched into the wiring by the switch closing.
Figure 6-21 can be used to explain the difference between the speed of electrons and the electromagnetic wave velocity. The figure shows a copper tube, which contains marbles that are separated by small springs. If an additional marble (No. 5) is shoved into the tube, marble 4 is shoved further into the tube, compressing the spring between it and marble 3. Note that in this early stage marbles 2 and 1 have no idea what is going on yet. As No. 5 is shoved into No. 4’s place the rest of the marbles must “do the wave” to make room for it. Eventually all of the marbles have slid over by one marble space and marble 1 pops out the other end.
Notice now that all of the marbles have moved a distance of only one marble space, but the effect of this movement (a wave) is felt at the end of the tube in about the same amount of time. The speed of the wave is determined for the most part by the value of the spring constants and partly by the momentum of the marbles.
So in a transmission line the electrons travel slowly, but the electromagnetic (EM) waves travel fast. The speed of the EM wave is determined by how quickly the magnetic fields in the inductors and the electric fields in the capacitors can be built up or dissipated, which is influenced by the material properties and geometry of the PCB through which the wave travels.
The velocity of an EM wave through a medium is described by
Eq. (6.10),
where
vEM is the velocity of the EM wave in a given material, ε
0 is the permittivity of free space (8.89×10
−12 F/m), ε
r is the relative permittivity (dielectric constant) of the material (a unitless constant relative to ε
0), μ
0 is the permeability of free space
(4Π×10
−7 H/m), and μ
r is the relative permeability of the material (a unitless constant relative to μ
0).
You may recall that the speed of light,
c (a special EM wave), in free space is
As stated, the terms ε
r (relative permittivity) and μ
r (relative permeability) are unitless. Furthermore μ
r is equal to 1 in free space and in most polymers (including FR4 laminate), so we can further simplify
Eq. (6.12) as shown in
Eq. (6.13):
From
Eq. (6.13) we see that the velocity of an EM wave (which comprises both electric and magnetic fields) in a PCB varies inversely with the relative permittivity, ε
r.
Relating this observation with
Eq. (6.7), we can state (without rigorous proof) that the capacitance of a transmission line is determined by the geometry of the transmission line and the relative dielectric constant (ε
r) within the transmission line. And the inductance of a transmission line (specifically the loop inductance) is determined by the geometry, but μ
r falls out since it is equal to 1 (see
Eq. [6.5] and
Figure 6-4 and
Figure 6-5).
In practice, calculating the characteristic impedance, capacitance, and inductance can be fairly complex, depending on the geometry of the circuit, but fortunately that has been done for us for the most common transmission line configurations. The equations are shown in
Table 6-2Table 6-3Table 6-4 and
Table 6-5. The PCB designer has full control over the trace width (
w) and partial control over the trace thickness (
t) by selecting the ounces per square foot but may have little or no control over the thickness of the laminate (
h). These equations are solved for
w and presented later in this chapter (in
Table 6-6 and
Table 6-7).
Table 6-2 Surface Microstrip Transmission Lines
in nH/in, where
k = 87 for 15 <
w < 25 mils and
k = 79 for 5 <
w < 15 mils. Restrictions: 0.1 <
w/h < 3.0 and 1 < ε
r < 15 (typically 4.0 to 4.5 for FR4). |
Microstrip transmission lines | Z0(Ω) | C0 (pF/in.) |
---|
Surface | | | |
Surface differential | | | |
| | Z0 same as surface microstrip | |
Table 6-3 Embedded Microstrip Transmission Lines
k=87. Restrictions: 0.1
w/h<3.0, 1 ε
r<15, and Z
0<Z
diff<2Z
0. |
Microstrip transmission lines | Z0(Ω) | C0 (pF/in.) |
---|
Embedded | | | |
| | OR | |
| |
| |
Embedded edge coupled differential | | | |
| | h=h
1=h
2 | |
| | Z
0 same as embedded microstrip | |
Table 6-4 Balanced Stripline
Restrictions:
w/(
h −
t) < 0.35 and
w/
h < 2.0,
t/
h < 0.25, and 0.005 <
w < 0.015 in. |
Stripline transmission lines | z0(Ω) | C0 (pF/in.) |
---|
Balanced (symmetric) | | | |
| | OR | |
| | | |
Differential (edge coupled) | | | |
| | Z0 same as symmetric stripline | |
Table 6-5 Unbalanced Stripline
References: IPC-2141, p. 12; IPC-2221A, p. 44; IPC-D-330, Section 2, Table 2-1 2; Brooks 2003, p. 203; Montrose 1999, pp. 171–177. |
Note: Unless otherwise noted,
in nH/in. |
Stripline transmission lines | Z0(Ω) | C0 (pF/in.) |
---|
Unbalanced (asymmetric) | | | |
Differential (broadside compled) | | | |
| | Z0 same as unbalanced stripline | |
Table 6-6 Microstrip Transmission Line Configurations
Microstrip transmission lines | Characteristics | Intrinsic propagation delay |
---|
Surface | Topology | Characteristic impedance | |
| | |
| | k=87 for 15<
w<25 mils [1][2][3] and [4] | |
| | k=79 for 5<
w<15 mils [3] and [4] | |
| | Restrictions | |
| | 0.1<
w/
h<3.0 [1] | |
| | 1<ε
r<15 [1] | |
| | Design equations | |
| | Trace routing width to use in PCB Editor | |
| | | |
| | (use
k=87, then check against width rules, use
k=79 if necessary) | |
Surface differential | Topology | Characteristic impedance | |
| | | |
| | (same as surface microstrip) [5][6] and [7] | |
| | Differential impedance | |
| | | |
| | Restrictions | |
| | None specifically noted except as applies to the surface microstrip. | |
| | Design equations | |
| | Trace routing width to use in PCB Editor | |
| | | |
| | Trace separation: | |
| | | |
Embedded | Topology | Characteristic impedance | |
| | [2][8] and [9] | |
| | where
|
| | OR | OR |
| | [1] | [1] |
| | Restrictions[8] and [10] | |
| | 0.1<
wlh2<3.0 | |
| | 1<ε
r<15 | |
| | Line widths: 0.127(5 mils) to 0.381
mm (15 mils)
Dielectric thickness: 0.127 (5 mils) to 0.381
mm (15 mils)40<
Z0<90
Ω |
|
| |
| | Design equations | |
| | Trace routing width to use in PCB Editor | |
| | w=7.475
h
2×e
−x−1.25
t | |
| | where | |
| | | |
| | OR | |
| | | |
Embedded differential | Topology | Characteristic impedance | |
| | [5] | [5] |
| | Differential impedance | |
| | | |
| | Restrictions[5] | |
| | Same as embedded microstrip | |
| | Design equations | |
| | Trace routing width to use in PCB Editor | |
| | w=7.475
h2×e
−x−1.25
t | |
| | where | |
| | [1] | |
| | Trace separation of pair: | |
| | | |
Table 6-7 Stripline Transmission Line Configurations
Stripline transmission lines | Characteristics | Intrinsic propagation delay |
---|
Balanced (symmetric) | Topology | Characteristic impedance | |
| | | |
| | Restrictions Line widths: 0.127 (5 mils) to 0.381
mm (15 mils)Dielectric thickness: 0.127 (5 mils) to 0.381
mm (15 mils) 40<
Z0<90
Ω
Design equation | |
| | |
| | |
| | |
| | Trace routing width in PCB Editor: | |
| | | |
Unbalanced (asymmetric) | Topology | Characteristic impedance | |
| | [10] and [11] | |
| | Restrictions | |
| | | |
| | | |
| | Design equation | |
| | Trace routing width in PCB Editor | |
| | w=2.375(2h
2 +
t)
e−x−1.25
t | |
| | where | |
| | | |
Stripline transmission lines | Required trace width (in) for desiredZ0 and/orZdiff. | Intrinsic propagation delay |
Broadside coupled differential stripline (symmetric)[12] | Topology | Characteristic (between conductors) impedance | |
| | Restrictions None given in the references
Design equations Trace routing width to use in PCB Editor
w=7.475
d×e
−x−1.25
t where | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Edge coupled differential stripline (symmetric)[12] | Topology | Characteristic impedance | |
For symmetric (
h1=
h2) or asymmetric (
h1 ≠
h
2) | | For symmetric (
h1=h
2) | |
| | | |
| | For asymmetric (h
1≠
h2) | |
| | | |
| | Differential impedance (both) | |
| | | |
| | Design equations | |
| | Trace routing width to use in PCB Editor | |
| | For symmetric (h
1=h
2) | |
| | | |
| | For asymmetric (
h1≠
h2) | |
| | w=2.375(2
h2 +
t)×e
−x−1.25
t | |
| | where | |
| | | |
| | Trace separation in layer stack-up (for symmetric or asymmetric) | |
| | | |
Reflections
So the next question is, What happens when the voltage “wave front,”
Vline, reaches the termination impedance,
Z
T? The answer is that it depends on what
Z
T is.
Let’s assume for a minute that
Z
T is an open circuit. When the last capacitor,
C5, in
Figure 6-18 is charged and
Vline reaches
Z
T (which equals infinity), then all capacitors are charged along the line (and their impedance equals infinity), so all current stops—or at least it would like to. But it cannot, because all of
the inductors have current,
Iline, through them and they will not allow
Iline to stop instantly. As the magnetic fields of
L7 and
L8 begin to collapse to try to maintain their current (remember that they are mutually coupled and influence each other), they continue to shove current into
C5, raising its voltage a bit more (we will see later what
a bit more means).
The magnetic fields of each inductor pair (
L3 and
L4,
L1 and
L2, etc.) will collapse, one after the next, back toward the source and raise the voltage of its nearest capacitor, all the way down the line. This new voltage front (
Vline + a bit more) propagates back from
Z
T toward the source with the collapsing magnetic fields until all of the magnetic fields have collapsed and all of the capacitors have this new charge on them. An analogy of a reflection from a high impedance termination is shown in
Figure 6-22, which shows a person launching a wave into a rope. If the rope experiences little or no friction, the wave will propagate down the rope unattenuated. If the end of the rope is loose (a high impedance), the wave will be reflected back toward the person, who will feel an identical wave returned.
In the example above the reflected wave has the same polarity and amplitude of the transmitted (incident) wave. In reality the rope would not be in a frictionless environment (and
Z
T would not be infinitely high). In that case the reflected wave would still have the same polarity as the incident wave but the amplitude would be less.
The magnitude and polarity of the reflected wave are described by the reflection coefficient, ρ (Greek letter
r), as shown in
Eq. (6.14):
The reflection coefficient can have values between −1 and +1. If
Z
T>
Zline (i.e., as
Z
T approaches ∞
, as in the example above), then
which means that the reflected wave will be exactly the same amplitude and have the same polarity as the incident wave.
Next we consider what happens if
Z
T (in
Figure 6-18) is a short circuit instead of an open circuit. At first the exact same thing occurs as described above when the switch is shut. That is (assuming the same initial conditions as above, all caps are discharged, etc.), the capacitors and inductors take their turn charging up and building up magnetic fields,
Vline is applied to the line, current
Iline. flows, and
Z
Cn =
Vline/
I
Cn. So the instantaneous line impedance is equivalent to
Z
Cn. A different result occurs at the end of the transmission line. Since
Z
T = 0
Ω and inductors
L7 and
L8 again want to maintain their current flow,
Iline flows straight through the short, Z
T.
Since the current through
L7 and
L8 is maintained (even for just an instant) and since the voltage drop across an inductor with a constant current flow is zero, capacitor
C4 sees the short and begins to discharge through
L7 and
L8 (helping to maintain their current flow) and on through the short,
Z
T. A short moment later
C4 is at the same potential as
C5 and
Z
T (0
V), while
L7 and
L8 have managed to maintain their current. The capacitors continue to discharge one after the other (
C3 then
C2, etc.) and each inductor pair maintains its current until finally all capacitors are shorted (and all the inductors look like a short if they have the same constant current). In the final analysis,
Vline =
V
ZT = 0
V and therefore
Zline = 0/
Iline = 0
Ω and
Iline =
V
s/
R
s.
A mechanical analogy of a wave reflected negatively from a “dead short” is shown in
Figure 6-23. If a positive wave is launched into a rope that is rigidly fixed at the end, the wave will be negatively reflected. In a perfectly lossless environment, the reflected wave will be of the same magnitude but opposite polarity as the incident wave.
In the electrical example above, the negatively reflected wave has the same magnitude as but opposite polarity to the voltage stored on the capacitors. As the negative wave hits each capacitor, it is forced to give up its charge (as current), which helps maintain the current flow through the nearest inductors and all the way down the line through the short at the end of the line. This
negatively reflected wave is again represented mathematically by the reflection coefficient (
Eq. [6.14]), but in this case since Z
T<
Zline (i.e., as Z
T approaches 0), ρ = −1, as shown in
Eq. (6.15):
Now let’s say for argument that the characteristics of our transmission line are such that when we calculate
Z
Cn =
Vline/
I
Cn at each capacitor/inductor section, Z
Cn = 50
Ω. Let us also set
R
s = to 50
Ω. Now what happens when
Z
T = 50
Ω? As you can suppose by this time, at the moment the switch is shut, the capacitors take their turn getting charged (and the inductors are building their fields). Since each
Z
Cn = 50
Ω, then
Zline is also 50
Ω. Since
R
s and
Zline are equal (and act as a voltage divider),
Vline = 1⁄2
V
s. Once the wave front has propagated down the line and reaches
Z
T, which is also 50
Ω,
Iline continues to flow into
Z
T as if nothing different has occurred and
V
ZT =
Vline = 1⁄2
V
s. As long as Z
T is purely resistive, then everything is at steady state and
Zline =
Z
T = 50
Ω. Also no voltage is reflected back toward the source because no change in voltage occurred on the capacitors and no current change occurred in the inductors.
In this case, since
Z
T =
Zline the reflection coefficient is 0 (ρ = 0) as shown in
Eq. (6.16):
The mechanical analogy is shown in
Figure 6-24, in which none of the wave energy is reflected but is perfectly absorbed into the load at the end of the line.
From these examples we can conclude that
Zline is in effect only during voltage transitions and is the result of the voltage and the current transients that flow to charge the line capacitance to the new voltage and to build the magnetic fields in the inductors. We can also see that, if the impedance
Z
T is not the same as
Z0, then a reflection will occur, but if the impedance
Z
T is the same as
Z0, then no reflection will occur. Furthermore it takes a finite amount of time for a wave front to propagate from one end of a transmission line to the other, and if a reflection does occur it takes another
finite amount of time for the reflection to propagate back to the source. What happens at the source is the next topic.
Ringing
When ρ ≠ 0 between any adjacent impedances, reflections will occur. This is true both from driver to transmission line and from transmission line to load (and back). If there is little or no loss along the transmission line, the reflected waves will bounce back and forth between the driver and the load if they are not matched to the transmission line (or if the transmission line is not matched to them). When viewing a particular point along the path, for example at the output pin of a gate or amplifier, the repeated reflections will be evident as ringing. Ringing is a direct result of reflections, which in turn are due to impedance mismatches.
One of the problems with ringing is that the voltage at any point along the line is effectively out of control, since ringing causes voltage overshoots and undershoots (see
Figure 6-26 later). Overshoots can actually damage active devices that have input voltage limitations and will radiate greater EMI than normal signals. Overshoots and undershoots can cause digital circuits to be falsely triggered if the reflected voltage swings across switching thresholds. In analog circuits the interactions between a continuous wave signal and its reflections creates standing and/or traveling waves that can degrade the signal of interest.
The magnitude and frequency of the ringing depend on the speed of the wave through the transmission line, the length of the line, and the reflection coefficient at each impedance discontinuity. We take a detailed look at ringing using the circuit shown in
Figure 6-25.
The circuit consists of a driver that is powered by
VCC and has a low output impedance,
R
S (10
Ω); a transmission line with a characteristic impedance,
Z0 (50
Ω); and a receiver with a high input impedance,
R
L (usually 1
kΩ or higher).
The dashed lines indicate the interfaces of the mismatched impedances and are labeled as ZX
1, and ZX
2. The dimensions in green represent length, and the dimensions in blue represent time. The circuit in the figure can be used to represent an analog or digital circuit, but we will consider the digital application.
Consider the following:
▪ RT is the rise time, the time it takes for the output of a driver to transition from a minimum value to a maximum value. RT is specific to individual devices and is given in the data sheets.
▪
Ltrace is the length of a trace (transmission line) on the PCB.
▪
v
P is the propagation velocity of a wave and is determined by
Z0 which is determined by ε
r and the transmission line dimensions (trace width and distance to the ground plane).
• PT is the propagation time, the time it takes for the transition to propagate from one end of the transmission line to the other.
▪
LSE is the effective length of the rising edge (also called
transition distance or the
spatial extent of the transition [
Bogatin 2004, p. 215] or
edge length [Johnson and Graham 1993, p. 7]).
▪ Length and time are related by the propagation velocity of the wave,
v
p (units of distance/time), where PT =
Ltrace/
v
p (units of time) and
LSE =
v
P× RT (units in distance).
• If length of the trace,
Ltrace, is longer than the spatial extent of the rising edge,
LSE, then the rising edge will fit entirely within the length of the trace and the reflection voltage will be an amplitude-scaled copy of the entire rising edge, for which the scaling is determined by the reflection coefficient, ρ. Another way of looking at the same thing is if the RT (rise time) is faster than the PT (propagation time), then the rising edge will have time to be fully reflected.
Electrically Long Traces
The goal is to design PCB traces such that they do not allow conditions to exist under which propagation times are too slow (compared to signal RTs) or a trace’s length is too long (compared to a signal’s spatial extent). When these conditions cannot be met, the trace is considered to be “electrically long” and must be treated as a transmission line. Proper treatment of a transmission line means controlling the impedance of the line over the entire length of the line and matching the impedance of the line with the source and load impedances so that reflections do not occur.
The obvious question is, when is a trace too long (or when is the RT too fast)? The magnitude of reflections and the ringing frequency are governed by the down and back (round trip) time of the reflections. Much of the literature states that the propagation time, PT, should be less than one half of the rise time (i.e., PT <½RT) or that the length of the trace should be less than one half of the special extent of a rising edge (i.e.,
Ltrace < ½
LSE). These relationships define the limits, not the goal. The shorter trace lengths are or the slower
the RT is, the better off you will be. The examples below illustrate this in greater detail. After the examples general design recommendations are provided.
Figure 6-26 shows what happens when PT is too long compared to RT. The data in the figure were generated using the transmission line model found in PSpice and the PT was set four times longer than the RT (instead of being<1⁄2RT).Refer to
Figure 6-25 and
Figure 6-26 during the discussion.
0. At time
t = 0
ns the logic gate output (
Vsource) switches to
VCC = 5 V
DC and begins to increase in voltage at the output (
Vdrive) (start of rising edge). The first capacitor in the transmission line is uncharged and acts like a short to GND.
1. At
t = 10
ns the gate has finished switching and the voltage at the output of the driver,
V
D, is
because of the voltage divider established by
R
s and
Z0. At this point the beginning of the rising edge is halfway to the load, and the tail end of the rising edge is just leaving the load side of
R
s.
2. At
t = 20
ns the beginning of the rising edge reaches the load resistor,
R
L. Since there is an impedance mismatch between
Z0 (50
Ω) and
R
L (1
kΩ), there is a positive reflection that begins immediately
to head back to
R
S. The reflected voltage is added to the rest of the rising edge as it continues to arrive at
R
L. The reflection coefficient looking into the load from the transmission line is ρ = (1000−50)/(1000 + 50) = 0.90.
3. By
t = 30
ns the trailing end of the rising edge reaches the load. The voltage at the load (
Vload) is now the sum of its previous voltage (0
V) plus the value of the incoming voltage (4.17
V) plus the reflected voltage (4.17×0.90 = 3.75
V) for a total of 4.17 + 3.75 = 7.92
V. The reflected voltage (3.75
V) is well on its way back toward the source.
4. At
t = 40
ns the rising edge that was positively reflected from the load begins to arrive at the source,
R
S. The voltage at the source begins to rise (pts 4 to 5). However, since the impedance of the transmission line is greater than that of the source resistor, a negative reflection immediately begins to head back to the load. The reflection coefficient from the transmission line looking into
R
S is
5. At
t = 50
ns the 3.75
V reflected off from the load has completely reached
R
s. The voltage at the load side of
R
s is the sum of its original value (4.17
V) and the incoming reflected voltage (3.75
V) plus the voltage being rereflected back to the load (−0.667×3.75
V = −2.50
V) for a total of 4.17 + 3.75 + −2.5 = 5.42
V. And the −2.50
V is on its way to the load.
6. At
t = 60
ns the −2.50
V reaches the load and begins to lower the load voltage from its previous value of 7.92
V. Because of the impedance mismatch between the transmission line and the load, a reflection is immediately launched again. The reflection coefficient is still + 0.90, so the reflection will have the same polarity as the incident wave. Since the incident wave is the −2.50
V reflected off from
R
S, the load will reflect back a negative voltage. As the incoming −2.50
V runs into a positively reflected negative voltage, the overall voltage at the load (pts 6 to 7) drops significantly since ρ is high (0.90).
7. At
t = 70
ns the −2.50
V reflected off from the source has completely reached
R
L where the voltage is the sum of its original value (7.92
V) and the incoming reflected voltage (−2.50
V) plus the voltage being rereflected back to the load (−2.50
V×0.90 = −2.25
V) for a total of 7.92 + −2.50 + −2.25 = 3.16
V). And of course the −2.25
V is on its way to the source.
8. At
t = 80
ns the negative voltage that was reflected (positively, i.e., leaving the sign intact) from the load begins to arrive at
R
s. Since the incoming voltage is negative, the voltage at
R
s begins to fall. But since there is still a negative reflection coefficient (−0.667) from the transmission line looking into
R
s, the wave that immediately begins to bounce off from
R
S is now positive and heads back to the load.
9.
At
t = 90
ns the −2.25
V reflected off from the load has completely reached
R
s. Again the voltage at
R
s is the sum of its previous value (5.42
V) and the incoming reflected voltage (−2.25
V) plus the voltage being rereflected back to the load (−0.667×−2.25
V = + 1.50
V) for a total of 5.42 + −2.25 + 1.50 = 4.67
V). And of course the + 1.50
V is on its way to the load.
The reflections continue back and forth but decrease in value each trip. The losses occur because the energy that is not reflected at each impedance interface is absorbed into the source and load resistors. Eventually, the reflections become too small to notice and we say that it has reached steady state. The time to reach steady state is called the
settling time and the shorter the settling time, the better.
If the length of the trace,
Ltrace, is much shorter than the special extent of
LSE (as represented in
Figure 6-27), then the rising edge will not fit within the length of the trace and will reach the driver before the driver has even completely reached is steady-state value. If the trace is very short, the reflection voltage will be reflected many times and repeatedly fold back onto itself as the driver output climbs to its steady-state value. Since the voltage at an interface is the sum of its existing voltage, the incoming reflection, and the reflected reflection, the effects of the reflections become “smeared” into each other. By the time the driver has fully reached its final value most of the reflections have come and gone and only the last, smaller overshoots and undershoots are evident.
Figure 6-28 shows what happens when PT is much shorter than RT on an electrically short trace. The reflections occur as previously described, but as shown in the graph many of the reflections have occurred by the time the driver reaches its full output level. Recall that the voltage at each impedance interface is the sum of its previous voltage plus the incoming voltage plus the reflected voltage, but since the reflections happen fast (relative to the rise time), each reflection never has a chance to reach its full voltage level (only a fraction of the rising edge at that time), so the reflections are much smaller and therefore the peaks (overshoots) and valleys (undershoots) are also much smaller
(hardly noticeable), while the driver output is still rising. Also the ring frequency is higher with the shorter trace.
Transmission Line Terminations
If we cannot make the rise time slower and/or the length of the trace shorter, then we will have noticeable reflections and ringing. The only other way to stop the reflections and ringing is to eliminate the impedance mismatches that are causing them by properly terminating the ends of the transmission line with the proper source and/or load resistors.
We can make
R
s = Z
0 =
R
L by using a resistor in series with the source and a resistor in parallel with the load.
If the impedances are all matched then there will be no reflections, as shown in
Figure 6-30. However, only half the voltage will reach the load because a voltage divider results with
R
S equal to
R
L so
Vload = 1⁄2
Vsource. This lower voltage at the load may not reach required logic thresholds, preventing affected digital circuits from functioning.
An alternative is to put a resistor in series with the driver such that the impedance that the transmission line sees looking at the driver and series resistor is equal to
Z0. So if
Z0 is 50
Ω and the driver output resistance is 10
Ω, then the transmission line will be matched to the driver by putting a 40-Ω resistor in series with
R
s. An example of the result is shown in
Figure 6-31. Even when PT is >1⁄2RT, only one reflection occurs (the fiat section on
Vdrive between 10 and 20
ns) and it is absorbed into the 40-Ω resistor and
R
s, so the reflection dies there. An advantage of this type of termination technique is that the voltage at the load is also much closer to the ideal voltage. The momentary hold on
Vdrive is usually not a problem, but it can be a problem in high-speed clock circuits for which the steady-state on (off) time is about the same duration as the rise time.
To match impedances between the source and the transmission line, place a resistor in series with the driver such that
Rseries =
Z0−
Rs.
To match impedances between the transmission line and the load, place a resistor in parallel with the load such that
Rparallel =
(
RLZ0)/(
RL−
Z0).