Preface

The text ESD: Design and Synthesis is targeted at the semiconductor chip “architect”, team lead floorplan engineer, circuit designer, design layout support, ESD engineer, and computer aided design (CAD) integration team. In this text, a balance is established between design synthesis, design integration, layout engineering, and design checking and verification.

The first goal of the text ESD: Design and Synthesis is to teach the “art” of ESD chip design for a semiconductor chip.

The second goal is to demonstrate a step-by-step process to provide ESD protection to a semiconductor chip. The flow of the text addresses floorplanning, architecture, power rails, ESD networks for power rails, ESD signal pin solutions, guard rings, and examples of implementations. This flow is significantly different from the approach taken in most texts, but is the actual flow of how a design team proceeds through the ESD implementation.

The third goal is to expose the reader to the growing number of architectures and concepts being discussed today. Examples of DRAM, SRAM, image processing chips, microprocessors, mixed-voltage to mixed-signal applications, and floorplans will be shown.

The fourth goal is to address topics that are not discussed in other ESD textbooks. These topics include power bus architecture, guard rings, and floorplanning. For many ESD engineers and circuit designers, this is common knowledge; for others, it is not. A significant part of the ESD design and synthesis is spent on placement, floorplans, and integration.

This text, ESD: Design and Synthesis, contains the following:

• Chapter 1 introduces the reader to an overview of the language and fundamentals associated with ESD design. In this chapter, ESD concepts are introduced from layout, circuits, to design rule checking. A “sampler” of concepts is laid out to the reader, to begin viewing the ESD design synthesis from a broader perspective. ESD design synthesis extends from the smallest contact, to full-chip integration. With this awareness, it is possible to realize the extent of the ESD design discipline in semiconductor design.

  For the next chapters, the text is structured as primarily a “top-down” ESD approach. This starts with floorplanning, bus architecture, ESD power clamps, ESD input circuits, and guard rings. The text will close with more examples of floorplanning and design integration. Most previous ESD texts focus on a “bottom-up” approach to ESD design integration; in “real-life” semiconductor integration, it typically starts from the “top down”.

• Chapter 2 discusses chip architectures. In this chapter, the discussion focuses on ESD architecture and floorplan concepts. The chapter focuses on “peripheral I/O” and “array I/O” architectures, and how they influence the placement of the various elements for the whole-chip design integration. The chapter addresses native-voltage, mixed-voltage, and mixed-signal chip integration.
• Chapter 3 focuses on power grid design. In this chapter, the discussion continues to address issues associated with full-chip ESD design synthesis. The chapter focuses on the interconnects, power grid layout, and design itself. It addresses interconnect robustness, interconnect failure, and key metrics in the whole-chip ESD design synthesis. The chapter addresses the issue of integration with the ESD power clamps. This naturally flows into the next chapter.
• Chapter 4 addresses ESD power clamps on power domains and power pads. In this chapter, ESD power clamp circuits are discussed. ESD power clamp classification, key parameters, issues, and specific designs are discussed. How the ESD power clamps are integrated with the semiconductor chip will become more apparent.
• Chapter 5 focuses on ESD signal pad networks. In this chapter, ESD signal pin device layout and integration with bond pads are discussed. ESD signal pin classification, key parameters, issues, and specific designs are covered. The chapter focuses on ESD integration with the bond pad, from structures next to pads, adjacent to bond pad, partially-under, and under bond pads. All types of arrangements and orientation tradeoffs will be discussed. The chapter focuses on device layout and integration.
• Chapter 6 focuses on guard rings and guard ring integration. In this chapter, a “top-down” design synthesis approach for guard rings is shown for a semiconductor chip, starting with the seal ring, to domains, standard cell-to-standard cell, within-standard cell, and down to the individual devices. A “bottom-up” approach starts with the individual devices and works its way up to the full-chip implementation. Special structures and cases are shown as examples of how to further isolate both domains and devices. A small taste is given to show what is possible with the guard ring design synthesis and integration with both devices to full-chip implementations.
• Chapter 7 provides examples of different chip floorplans and architectures. In this chapter, the focus is on examples of design synthesis in full-chip implementations. Examples of DRAM, SRAM, microprocessors, mixed-voltage, mixed-signal, and RF applications will be shown. As part of the ESD design synthesis, the layout is key to a successful design implementation for both ESD and CMOS latchup. These examples will provide some understanding of the challenges in the ESD full-chip integration issues. By combining the knowledge of Chapters 1 through 6 with this chapter, the whole-chip design strategy should be better understood for any semiconductor chip architecture perspective.

This text is part of an ESD book series on electrostatic discharge protection. To establish a strong knowledge of ESD protection, it is advisable to read the other texts on ESD and latchup as well. For this text, ESD: Design and Synthesis, hopefully we have covered the trends and directions of ESD design synthesis.

Enjoy the text, and enjoy the subject of ESD design synthesis.

Baruch HaShem (B”H)
Dr Steven H. Voldman
IEEE Fellow