Memory nodes

Linux kernel is implemented to support multi-processor machine architectures for a long time now. Kernel implements various resources such as per-CPU data caches, mutual exclusion locks, and atomic operation macros, which are used across various SMP-aware subsystems, such as process scheduler and device management, among others. In particular, the role of memory management subsystem is crucial for kernel to tick on such architectures, since it needs to virtualize memory as viewed by each processor. Multi-processor machine architectures are broadly categorized into two types based on each processor's perception, and access latency to memory on the system.


Uniform Memory Access Architecture (UMA): These are multi-processor architecture machines, where processors are joined through an interconnect and share physical memory and I/O ports. They are named as UMA systems due to memory access latency, which is uniform and fixed irrespective of the processor from which they were initiated. Most symmetric multi-processor systems are UMA.

Non-Uniform Memory Access Architecture (NUMA): These are multi-processor machines with a contrasting design to that of UMA. These systems are designed with dedicated memory for each processor with fixed time access latencies. However, processors can initiate access operations on local memory of other processors through appropriate interconnects, and such operations render variable time access latencies.
Machines of this model are appropriately named NUMA due to non-uniform (non-contiguous) view of systems memory for each processor:


To extend support for NUMA machines, kernel views each non uniform memory partition (local memory) as a node. Each node is identified by a descriptor of type pg_data_t , which refers to pages under that node as per zoning policy, discussed earlier. Each zone is represented through an instance of struct zone. UMA machines would contain one node descriptor under which the entire memory is represented, and on NUMA machines, a list of node descriptors are enumerated, each representing a contiguous memory node. The following diagram illustrates the relationship between these data structures:


We shall follow on with node and zone descriptor data structure definitions. Note that we do not intend to describe every element of these structures as they are related to various aspects of memory management which are out of scope of this chapter.

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