Now let's focus on external interrupts and explore how processors identify the occurrence of an external hardware interrupt, and how they discover the vector number associated with the interrupt. CPUs are designed with a dedicated input pin (intr pin) used to signal external interrupts. Each external hardware device capable of issuing interrupt requests usually consists of one or more output pins called Interrupt Request lines (IRQ), used to signal an interrupt request on the CPU. All computing platforms use a hardware circuit called a programmable interrupt controller (PIC) to multiplex the CPU's interrupt pin across various interrupt request lines. All of the existing IRQ lines originating from on-board device controllers are routed to input pins of the interrupt controller, which monitors each IRQ line for an interrupt signal, and upon arrival of an interrupt, converts the request into a cpu-understandable vector number and relays the interrupt signal on to the CPU's interrupt pin. In simple words, a programmable interrupt controller multiplexes multiple device interrupt request lines into a single interrupt line of the processor:

Design and implementation of interrupt controllers is platform specific. Intel x86 multiprocessor platforms use Advanced Programmable Interrupt Controller (APIC). The APIC design splits interrupt controller functionality into two distinct chipsets: the first component is an I/O APIC that resides on the system bus. All shared peripheral hardware IRQ lines are routed to the I/O APIC; this chip translates an interrupt request into vector code. The second is a per-CPU controller called Local APIC (usually integrated into the processor core) which delivers hardware interrupts to specific CPU cores. I/O APIC routes the interrupt events to a Local APIC of the chosen CPU core. It is programmed with a redirection table, which is used for making interrupt routing decisions. CPU Local APICs manage all external interrupts for a specific CPU core; additionally, they deliver events from CPU local hardware such as timers and can also receive and generate inter-processor interrupts (IPIs) that can occur on an SMP platform.

The following diagram depicts the split architecture of APIC. The flow of events now begins with individual devices raising IRQ on the I/O APIC, which routes the request to a specific Local APIC, which in turn delivers the interrupt to a specific CPU core:

Similar to the APIC architecture, multicore ARM platforms split the generic interrupt controller (GIC) implementation into two. The first component is called a distributor, which is global to the system and has several peripheral hardware interrupt sources physically routed to it. The second component is replicated per-CPU and is called the cpu interface. The distributor component is programmed with distribution logic of shared peripheral interrupts(SPI) to known CPU interfaces.