When an interrupt originates from an external device, it is referred to as a hardware interrupt. These signals are generated by external hardware to seek the attention of the processor on occurrence of a significant external event, for instance a key hit on the keyboard, a click on a mouse button, or moving the mouse trigger hardware interrupts through which the processor is notified about the availability of data to be read. Hardware interrupts occur asynchronously with respect to the processor clock (meaning they can occur at random times), and hence are also termed as asynchronous interrupts.

Interrupts triggered from within the CPU due to events generated by program instructions currently in execution are referred to as software interrupts. A software interrupt is caused either by an exception triggered by program instructions currently in execution or on execution of a privileged instruction that raises an interrupt. For instance, when a program instruction attempts to divide a number by zero, the arithmetic logic unit of the processor raises an interrupt called a divide-by-zero exception. Similarly, when a program in execution intends to invoke a kernel service call, it executes a special instruction (sysenter) that raises an interrupt to shift the processor into privileged mode, which paves the path for the execution of the desired service call. These events occur synchronously with respect to the processor's clock and hence are also called synchronous interrupts.

In response to the occurrence of an interrupt event, CPUs are designed to preempt the current instruction sequence or thread of execution, and execute a special function called interrupt service routine (ISR). To locate the appropriate ISR that corresponds to an interrupt event, interrupt vector tables are used. An interrupt vector is an address in memory that contains a reference to a software-defined interrupt service to be executed in response to an interrupt. Processor architectures define the total count of interrupt vectors supported, and describe the layout of each interrupt vector in memory. In general, for most processor architectures, all supported vectors are set up in memory as a list called an interrupt vector table, whose address is programmed into a processor register by the platform software.

Let's consider specifics of the x86 architecture as an example for better understanding. The x86 family of processors supports a total of 256 interrupt vectors, of which the first 32 are reserved for processor exceptions and the rest used for software and hardware interrupts. Implementation of a vector table by x86 is referred to as an interrupt descriptor table (IDT), which is an array of descriptors of either 8 byte (for 32-bit machines) or 16 byte (for 64-bit x86 machines) sizes. During early boot, the architecture-specific branch of the kernel code sets up the IDT in memory and programs the IDTR register (special x86 register) of the processor with the physical start address and length of the IDT. When an interrupt occurs, the processor locates relevant vector descriptors by multiplying the reported vector number by the size of the vector descriptor (vector number x 8 on x86_32 machines, and vector no x 16 on x86_64 machines) and adding the result to the base address of the IDT. Once a valid vector descriptor is reached, the processor continues with the execution of actions specified within the descriptor.