Chapter 5. Introduction to Microwave Active Devices

A Schottky diode has, for a long time, been used in detectors and mixers due to its rectifying property. The Schottky diode uses majority carrier diffusion while the pn diode uses minority carrier diffusion. Consequently, the Schottky diode has no diffusion capacitance that is associated with minority carriers. Thus, the Schottky diode provides a number of benefits when used in mixers at high frequencies.

Until the 1970s, Gunn diodes and IMPATT diodes were primarily used as active components in oscillators and amplifiers. In those days, it was difficult to utilize transistors at frequencies higher than 4 GHz. The DC characteristics of these diodes showed a negative resistance when they were biased appropriately. By using negative resistance, it was much easier to design oscillators and they could also be used as amplifiers. Since the reflection coefficient of devices with a negative resistance is greater than 1, the Gunn and IMPATT diodes could be configured as reflection amplifiers in combination with a circulator. However, one problem with these diodes was that they were not very efficient. As a result, heat dissipation always had to be considered. Therefore, they were used in the construction of circuits with waveguides that easily adapted to thermal design. These heat problems become important limiting factors in circuit integration. Another disadvantage was that these diodes could not be integrated with other devices in a single process, making it intrinsically difficult to build up complex-functioning integrated circuits that need other devices such as Schottky or varactor diodes used for mixer or frequency control.

Based on their operation, transistors can be generally categorized into two types: the bipolar junction transistor (BJT) and the field effect transistor (FET). BJTs use two carriers, holes and electrons, and they use a diffusion mechanism in current flow. BJTs control current flow by raising or lowering the barrier height formed at junctions. The number of diffusing carriers depends on the barrier height, which is altered by the voltage across the base-emitter junction. In contrast, FETs use one majority carrier, an electron, and they use a drift mechanism in current flow. An FET forms a channel through which electrons can flow. The number of electrons flowing through the channel can be controlled by narrowing or widening the channel’s thickness, which is achieved by controlling the gate voltage. FETs are also classified according to their channel formation. There are two kinds of channel formation: enhancement type and depletion type. In the enhancement type, the channel is not formed under the gate when the applied gate voltage is below a threshold voltage. The channel under the gate is formed by applying the adequate gate voltage. The gate voltage collects the carriers with opposite polarity and the accumulated carriers under the gate form the channel. In contrast, in the depletion type, the channel with carriers is formed in advance and the gate voltage is used to deplete the channel by repelling the carriers in the channel with the same polarity. Thus, the gate voltage is used to control the channel conductivity in both types of FETs.

The silicon process was the only available process technology for the fabrication of transistors until the 1970s. Microwave Si BJTs, which improved low-frequency BJTs in many ways, were exclusively used up to the range of microwave frequencies. However, these Si BJTs were not suitable for applications at frequencies higher than 4 GHz. In the early 1970s, the GaAs (gallium arsenide) MESFET (MEtal Semiconductor FET) or simply GaAs FET was developed as a result of the advance of the GaAs compound semiconductor process technology. The electron mobility in the GaAs is six times faster than in the Si. With this electron mobility advantage, GaAs FET has far better performance than the Si transistor. When GaAs FETs are fabricated using similar technology to the Si process, their performance is also as much as six times better. With the emergence of GaAs FETs, Gunn diodes, which had been popular until that time, became obsolete for amplifiers and oscillators in microwave frequencies up to the Ku band, and their application is now limited to the millimeter-wave frequencies. However, a further improvement in the characteristics of GaAs FETs led to the emergence of the HEMT (high-electron-mobility transistor) and the pHEMT (pseudomorphic HEMT). It is now possible to construct an integrated circuit up to a frequency of 200 GHz with these HEMTs. Thus, the future use of Gunn or IMPATT diodes in the millimeter wave remains unclear.

Three-terminal devices such as BJTs and GaAs MESFETs have several advantages when compared to diodes. They provide a flexibility in circuit design that can be applied to various components such as amplifiers, oscillators, and so on. In terms of efficiency, they are superior to the Gunn or other diodes. They do not require heat dissipation structures if they are not operated at significantly high power. They can also be used as switches by controlling the gate or base voltage. In addition, the characteristics of the varactor diode are inherently included in these devices, and they can be utilized in planar circuits as well, making them superior to other active components in terms of their advantages for integration. Every year, the high-frequency characteristics and performance of BJTs and GaAs MESFETs have been steadily improved by many researchers and even to date, their performance has been improved every year by applying new materials or new operating principles.

In this chapter, we will briefly investigate the operation and characteristics of these transistors used in microwave applications. Among diodes, we will also look at the varactor diode in oscillator design. The varactor diode is discussed further in Chapter 10. The operating principles and performance of Schottky diodes will also be discussed in the mixer design found in Chapter 12.

The performance of GaAs MESFETs has been further improved with recent advances in process technologies that have made the fabrication of complicated epi-layer structures possible. As a result, GaAs pHEMTs can now be used at frequencies reaching several hundred GHz. In addition, the Si complementary MOS (CMOS) fabrication technology has demonstrated remarkable advances in various mobile-communication services. Recently, many CMOS circuits operating at millimeter wave frequencies have been reported. However, the basic operation of CMOS circuits is the same as it was in the past, a subject that is extensively covered in many textbooks related to electronic circuits. Thus, in this section, we will consider the operation and equivalent circuits of FETs based on GaAs MESFETs among the many other types of FETs.

The equivalent circuit of a GaAs FET is shown in Figure 5.2. Resistors R_s and R_d represent the ohmic resistances that occur from the source and drain ohmic contacts. Resistor R_g represents the gate metallization resistance deposited to form the Schottky diode. The dependence of the drain current on the gate voltage is represented by the transconductance g_m, and that of the drain current on v_DS is represented by the resistance R_ds. In contrast with the R_g, R_s, and R_d shown in the figure, g_m and R_ds are nonlinear components and they represent the FET’s DC characteristics. Resistor R_i is called channel resistance and represents the resistance between the depletion region and source terminals. The depletion region that occurs in the gate region is not directly connected to the source terminal but is connected to the source through a channel region. R_i represents the resistance of such a channel resistance to the source terminal.

Capacitors C_gs and C_gd represent the capacitances caused by the depletion region between the gate and the source, and between the gate and the drain terminals. The DC-bias dependence of these capacitors has characteristics similar to those of a depletion capacitance. On the other hand, C_ds represents the capacitance occurring between the terminals of the source drain. Capacitor C_ds between the drain and source terminals results from the capacitances through the channel and air regions. Capacitor C_ds is also considered to be nonlinear and its characteristics are different from those of the depletion capacitance. The equivalent circuit in Figure 5.2 is redrawn in Figure 5.3. The transconductance is expressed as y_m = g_me^–jωτ because the drain current flows with a time delay of τ compared to the gate-source control voltage.

By measuring the forward DC current characteristics of the Schottky diode, the parameters such as ideality factor η and saturation current I_s can be determined. Also, since C_gs and C_gd originate from the depletion capacitance, they can be determined by measuring the C–V characteristics given by Equations (5.3) and (5.4).

In contrast, the nonlinear characteristics of C_ds and R_i are not so significant, and the small-signal values of C_ds and R_i can be used in the large-signal model.

However, the I_DS–V_DS characteristics of the GaAs FET are significantly different from those of the low-frequency FET devices. Therefore, a new mathematical model is required to represent its I_DS–V_DS characteristics, which are shown in Figure 5.5. There can be various mathematical models representing the I_DS–V_DS characteristics, but of these, there are three that are well known.

The Curtice model describes the characteristics shown in Figure 5.5 using the equation (1 + λV_DS)tanh(αV_DS). The function tanh(x) can be approximated by x for small x, and approaches 1 as x → ± ∞. Thus, for a small V_DS, (1 + λV_DS)tanh(αV_DS) behaves as a straight line for V_DS because (1 + λV_DS)tanh(αV_DS) ≅ αV_DS, which steeply increases for V_DS. In contrast, for a sufficiently large V_DS, the equation can be approximated as (1 + λV_DS), which increases slightly for V_DS. Thus, the I_DS–V_DS curves can be qualitatively represented by (1 + λV_DS)tanh(αV_DS). Now, we can determine the given equation through curve fitting of the measured I_DS–V_DS characteristics with constants α and λ.

However, since the dependence of the drain current on V_GS is close to the parabola shown in Figure 5.6, the I_DS–V_GS characteristics can be modeled using a quadratic equation. In reality, the use of the quadratic equation does not closely approximate the measured results. The cubic equation given in Equation (5.5) may be a better way to describe the I_DS–V_GS characteristics in Figure 5.6 because this equation has three degrees of freedom. In addition, the I_DS–V_GS characteristics depend to some degree on V_DS. In order to describe this, V₁ is used instead of V_GS, which depends linearly on V_DS as in Equation (5.5b). Thus, the I_DS–V_DS characteristics shown in Figure 5.5 are expressed mathematically in Equations (5.5a) and (5.5b).

For the Materka model, the relationship between the drain current and V_GS is described in a well-known parabolic relationship, and the slope for V_DS is expressed by modifying tanhx in the I_DS–V_DS characteristics as shown in Equations (5.6a) and (5.6b).

Note that the pinch-off voltage V_p also depends linearly on V_DS.

The Raytheon model is a mathematical model developed by the Raytheon Corporation and is expressed in Equation (5.7).

In addition, there are various other mathematical models that are difficult to distinguish in terms of their pros and cons, but they all describe the DC drain-current dependences on V_GS and V_DS, and all of them can be used in performing large-signal simulations. In addition, it is worth noting that all the equations from (5.5) to (5.7) represent a mathematical relationship for DC characteristics. Since the RF drain-current i_DS depends on RF gate voltage v_GS with a time delay of τ, the large-signal microwave operations of i_DS can be modeled by replacing V_GS by v_GS(t-τ) in the equations from (5.5) to (5.7) using Equation (5.8):

This equation can be used as a mathematical model for microwave operation.

For increased simplification, further approximation is possible because the depletion capacitance C_gd is generally small compared to C_gs and sometimes it is also assumed to be 0. Thus, the FET’s input and output are isolated. Such an approximation is called a unilateral approximation.

Figure 5.8 shows the measured S-parameters of a typical chip-state GaAs FET. After the GaAs FET chip was assembled by wire bonding on the carrier, as shown in Figures 5.9(b) and 5.9(c), the carrier assembly was mounted on a jig, as shown in Figure 5.9(a). In Figure 5.9(b), the reference planes are shown. Thus, the measured S-parameters usually include the inductance of bonding wires.

1. Agilent Technologies, High-Frequency Transistor Primer Part IV, GaAs FET Characteristics, 1999. Available at http://paginas.fe.up.pt/~hmiranda/etele/trans_primer4.pdf.

In Figure 5.8, S₁₁ and S₂₂ are related to input and output impedances. Thus, they are usually plotted on the Smith chart, as shown on the left side of Figure 5.8. In contrast, S₁₂ and S₂₁ are the transfer functions and so they are plotted on the polar chart on the right side of Figure 5.8 to show their magnitude and phase. On the polar chart, the radius is set to 5.0 for S₂₁ and the radial division scale is found to be 1.0. However, as S₁₂ is small, the radius is set to 1.0 and the radial division scale becomes 0.2. The frequency responses of the S-parameters can be explained using the simplified equivalent circuit shown in Figure 5.7.

From Figure 5.9, the measured S₁₁ includes the bonding-wire inductance. The input impedance of the FET is then found to be a series R-L-C circuit approximating C_gd = 0 in the simplified equivalent circuit. For a frequency change, the reactance of L and C changes but R_i is constant. Thus, the locus of S₁₁ lies in a constant resistance circle for a frequency change. At low frequency, the circuit behaves like a series R-C circuit. However, as the frequency increases, the inductance of the bonding wire becomes dominant, and so the circuit behaves as a series R-L circuit. From this, the resistance at the series resonance corresponds to the channel resistance R_i in the simplified equivalent circuit, but if the ignored contact resistance were to be considered, it would approximate the value of R_i + R_g + R_s. In addition, applying the method explained in Example 2.2 of Chapter 2, the bonding-wire inductance and capacitance can be obtained by calculating the L and C values at resonance. The resulting capacitance and inductance correspond approximately to C_gs and the bonding-wire inductance.

In the case of S₂₂, the drain-source impedance can be approximated by a circuit of R_ds and C_ds connected in parallel. Therefore, as the frequency approaches 0, the drain-source impedance approaches R_ds. As the frequency increases, S₂₂ moves along a constant conductance circle and the trajectory appears in the capacitive region due to capacitor C_ds. As the frequency further increases, S₂₂ is observed to move away from the constant conductance circle and to approximate a constant resistance circle similar to S₁₁ due to the effects of bonding-wire inductor and C_gd.

In the case of S₂₁, at an extremely low frequency, S₂₁ can be computed as

Using Equation (5.9), the approximate value of g_m can be found from the low-frequency measurement data. As the frequency increases, the voltage across C_gs decreases. As a result, |S₂₁| is reduced because it corresponds to the voltage across the termination Z_o. In addition, the influence of C_ds further reduces |S₂₁|. The phase of S₂₁ increases in a clockwise direction due to these capacitors.

In the case of S₁₂, when the frequency is extremely low, we can see that S₁₂ approximates

From Equation (5.10), we see that |S₁₂| increases as the frequency increases. Similar to the phase of S₂₁, the phase of S₁₂ also increases in a clockwise direction as the frequency increases.

Figure 5.10 shows a GaAs FET chip assembled using a commercial ceramic package. Figure 5.10(a) shows the top view with the lid removed and (b) shows the back view. The source is commonly used as the ground terminal. To minimize the inductance arising from the assembly of the source terminal, the terminal is frequently wire bonded in two places, as shown in Figure 5.10(a). The inductance resulting from the assembly of the source terminal, however small, causes feedback from output to input and creates the strong possibility of oscillation or device instability. Thus, to minimize the inductance, the package terminals where the source is connected are usually made wider when compared to the other terminals. The chip is mounted directly on the lead terminal, and the two source pads in the chip are wire bonded twice in each of two places on the lead terminal. The heat is thus dissipated through these lead terminals but it is worth noting that this heat dissipation may not be sufficient in certain cases.

The planes S and S’ shown in Figure 5.10(a) become the reference planes of the S-parameter measurement and the measured S-parameters are usually provided with these reference planes. Thus, many parasitic elements are added to the chip’s equivalent circuit in the packaged device. This is shown in Figure 5.11. The bonding-wire inductances L_g, L_s, and L_d occur as a consequence of wire bonding. In addition, since lines with a finite length are inserted into the package, they thus appear as transmission lines or inductance. Transmission lines T_in, T_out, and inductor L_M in Figure 5.11 represent these transmission lines as inductance. Various parasitic capacitances also occur. Capacitances C_in and C_out occur due to the discontinuity of the transmission lines. The capacitances C_F1 and C_F2 represent feedback capacitances occurring as a result of the coupling between the lines in the package.

These packaged-circuit parasitic elements prevent the accurate determination of the values of the active device’s equivalent circuit. Thus, it is common to obtain first the value of the chip’s equivalent circuit and then the value of the package’s equivalent. These are combined to yield the overall value of the equivalent circuit.

In Figure 5.12, the electrons are generated in the n-type AlGaAs layer, where impurity atoms are richly doped. The heterojunction is formed between the undoped AlGaAs and the undoped GaAs. As a result, an electron well is formed as a result of the heterojunction. The generated electrons in the n-type AlGaAs layer are then easily trapped and gathered in the electron well that is formed beneath the undoped GaAs layer. Since the electron well is very thin, the trapped electrons in the well can be considered to be a sheet of electron gas that is called 2DEG (2-dimensional electron gas). In addition, note that the undoped GaAs layer is almost intrinsic because there are no impurity atoms. Thus, the electrons can move according to the applied electric field without the influence of the impurity atoms. This results in an electron velocity that is much faster than in the GaAs FET. Therefore, the high-frequency gain performance can be improved when compared with a conventional GaAs FET because the electrons move much faster in the undoped channel. For this reason, the device is called an HEMT (high-electron-mobility transistor).

In the fabrication of a GaAs pHEMT, the lattice constants of the AlGaAs and GaAs differ significantly, making it difficult to grow a stable AlGaAs layer on the GaAs. The problem is solved by using the recently developed pseudomorphic technology. Inserting an extremely thin, undoped InGaAs layer between the undoped GaAs and the undoped AlGaAs layers, the stable AlGaAs layer can be grown, which makes it possible to manufacture these high-performance devices. Since the pseudomorphic technology is used to fabricate these devices, they are often called pHEMTs.

The principles of operation for an npn transistor are usually explained using the dotted-line area in Figure 5.13(b), which is also shown in Figure 5.14. Two pn junctions, the base-emitter (BE) junction and the collector-base (CB) junction, appear in the transistor. The two pn junction diodes are connected back-to-back. The BJT can operate in various modes such as active, cutoff, inverse, and saturation. In the active mode, the base-emitter (BE) junction is forward-biased while the collector-base (CB) junction is reverse-biased. As a result, the barrier height of the BE junction is lowered while the barrier height of the CB junction is raised. Due to the lowered BE-junction barrier height, the majority carriers, which are the electrons in the emitter region, are diffused into the base region while the holes in the base region are diffused into the emitter region. However, because the CB junction is reverse-biased, the diffusion between the collector and base do not occur due to the increased barrier height. Normally, the emitter region is more heavily doped than the base region. Thus, more electrons will be diffused from the emitter to the base than will holes from the base be diffused to the emitter. Consequently, the current contribution from the diffusion of holes can be ignored.

A small number of the diffused electrons from the emitter recombine and thereby disappear in the base region, while most of the electrons are collected in the collector region. Thus, the collector current i_C is almost equal to the emitter current i_E. Note that the emitter current i_E depends on the BE junction barrier height, which in turn is controlled by a small voltage applied to the BE junction, V_BE. Therefore, the large emitter current flow of the BJT can be controlled by a small-voltage V_BE, which thus acts as an amplifier. Therefore, the BE-junction voltage plays a similar role to the gate voltage in an FET.

However, the structure of the BJT shown in Figure 5.13(b) needs some improvements before it can be used in a high-frequency application. Basically, high-frequency performance is closely related to the base width. First, the electrons injected from the emitter should transit the base region to reach the collector. The transit time is related to the base width. Thus, the base width should be as narrow as possible. Second, a base-spreading resistance occurs due to the distance between the true base region and the actual base terminals, as shown in Figure 5.13(b). As a result, the gain at high frequencies is reduced. The base-spreading resistance can be reduced by increasing the base-region doping. However, the significantly increased doping of the base region increases the number of holes and, consequently, the number of holes that are diffused from the base to the emitter increases. As a result, the base current increases, which is desirable. As a way of reducing the base-spreading resistance, the base and emitter are implemented using the interdigital structure shown in Figure 5.15. When the finger width and spacing of the interdigital structure are narrowed, the base-spreading resistance can be significantly reduced due to the short length between the true base region and the base terminal.

In addition, because the electrons should pass through the n-type epitaxial layer in order to reach the collector terminal, the epitaxial layer is made sufficiently thin in order for the electrons to arrive at the collector terminal at a much faster rate. This BJT structure is shown in Figure 5.15 and the cross-sectional structure along S–S’ is shown in Figure 5.15(b). In that figure, the base thickness typically has the order of 0.1 μm, and the n-type collector thickness typically has the order of 1.5 μm, which is extremely thin. The base and emitter spacing is found to be about 1 μm in order to reduce the base-spreading resistance.

Therefore, the base current can be expressed in terms of the collector saturation current I_s as follows:

The first two terms of Equation (5.11) are related to the collector current flowing when each of the BE and BC junctions are forward-biased; each of them is divided by its respective current gain, β_F and β_R. The last two terms represent the current of the space-charge-region diode, which is independent of the collector current.

It can be seen that the current due to the BE and BC junction diodes constitutes the total collector current I_CT = I_CF-I_CR. The current is caused by two modes: the first occurs when the BE junction is forward-biased and the BC junction is reverse-biased (active mode); the second occurs when the BC junction is forward-biased and the BE junction is reverse-biased (inverse mode). In this case, the current is in the reverse direction. Thus, the collector current I_CT can be expressed as shown in Equation (5.12).

The q_b in the expression is a factor that represents the Early effect and the Kirk effect that appear in a large collector current and they are expressed as follows:

V_A and V_B in Equation (5.13) represent the forward and reverse Early voltages, respectively, while I_KF and I_KR in Equation (5.14) represent the forward and reverse knee currents of the collector current. Equations (5.11) through (5.14) represent the DC characteristics of the BJT.

Figure 5.17 illustrates how these parameters are determined. Plotting I_B and I_C with respect to V_BE enables us to extract the BE junction-related parameters given by Equations (5.11) through (5.14). This extraction is usually called a Gummel plot. From Figure 5.17, the knee current I_KF of the collector current can be determined from the turning point and from the slopes where the current begins to show. For the base current, on the other hand, the space-charge-region diode and the BE junction-related parameters can be determined from the turning point and the slopes in a small base current. Similarly, by plotting the Gummel plot for V_BC the BC junction-related parameters can be extracted. The parameters are grouped and shown in Table 5.1.

Next, we consider the resistances caused by contacts. These are R_E, R_B, and R_C, but of these, R_B is not a simple contact resistance. It varies according to the current and so two additional parameters (RBM, IRB) are required to describe it. These parameters are summarized in Table 5.1 and are classified as groups.

In addition, depletion and diffusion capacitances appear at the BE and BC junctions. The depletion capacitance is given in Equation (5.15) as

The depletion capacitance has the parameters C_je(0), m_E, and φ_BE. They refer to the capacitance at 0 V, the grading coefficient, and the built-in potential, respectively. The parameters for the BE junction’s depletion capacitance can be determined experimentally from the C–V measurement for V_BE. Through curve fitting of the measured results in Equation (5.15), the parameters can be determined. Similarly, the same parameter group can be defined for the BC-junction’s depletion capacitance and those parameters can be experimentally extracted using the C–V measurement for V_BC. The parameters for the BE- and BC-depletion capacitances are also grouped and shown in Table 5.1. However, because these expressions for the BE- and BC-junction depletion capacitances have singularity at V_BE = φ_BE and V_BC = φ_BC, their applications are usually limited to V_BE ≤ FC⋅φ_BE and V_BC ≤ FC⋅φ_BC. For V_BE or V_BC values greater than these, a straight line that is given by the tangent at FC⋅φ_BE is used instead of Equation (5.15). Thus, the value FC in Table 5.1 represents the range of V_BE and V_BC.

The diffusion capacitance is usually characterized by the transit time, which appears in the active and inverse mode operations. The transit time in the active and inverse mode operations is represented by TF and TR in Table 5.1, respectively. In addition, since the transit time is not constant but depends on several parameters, the parameters that represent this dependence (ITF, VTF, PTF, and XTF) form a group. The capacitors Q_E and Q_C in Figure 5.16 represent the capacitances that are the result of the previously explained depletion and diffusion capacitances. The capacitors Q_C2 and Q_CS depend on the fabrication method, and the reader may refer to reference 7 at the end of this chapter for details. Also, some additional circuit elements can be added to the BJT equivalent circuit described in this book according to the fabrication process. The reader is encouraged to consult other relevant references for details.

The circuit shown in Figure 5.18 is complex and can be difficult to understand. Therefore, the simplified equivalent circuit shown in Figure 5.19 is often used to explain the qualities of the measured S-parameters. The resistor g_π in the simplified equivalent circuit is ignored in a high-frequency application. Since the value of g_μ is also small, it is also ignored and even C_μ is sometimes ignored. The values of R_E and R_C are typically small, and because they are the resistances caused by contacts, they are also ignored. The equivalent circuit thus obtained is shown in Figure 5.19.

In Figure 5.20, similar to the FET, S₁₁ and S₂₂ are plotted on the Smith chart since they are related to impedance. In contrast, S₁₂ and S₂₁ are the transfer functions and so they are plotted on the polar chart to show their magnitude and phase. The radius of S₂₁ is set to 10.0, and the radial scale corresponds to a division of 2.0 per grid. However, as S₁₂ is small, the radial scale is selected to be 0.2 per grid.

Here, as in a GaAs FET, the input impedance includes the bonding wire in the measurement. Thus, the input approximates a series RLC circuit from the simplified equivalent circuit shown in Figure 5.19. As a result, the locus of the S-parameters follows a constant resistance circle, as shown in Figure 5.20. At low frequency, the locus lies in the capacitive region of the Smith chart. However, as the frequency increases, the inductance of the bonding wire becomes dominant and so the locus lies in the inductive region. The resistance value at resonance approximately corresponds to the base resistance R_B in the simplified equivalent circuit. In addition, by using the method described in Chapter 2 to compute the L and C values at resonance, both the inductance and the capacitance of the bonding wire can be obtained. The capacitance obtained can be interpreted as C_π.

In the case of S₂₂, because the collector resistance g_c is small, the effect of g_c is seldom observed in S₂₂. Rather than g_c, the output circuit can be approximated as the series connection of C_μ and r_π || (Z_o + R_B) for an extremely low frequency. In this case, because r_π is generally large, the output circuit appears to approximate the series connection of C_μ and (Z_o + R_B). Therefore, the locus moves, following the constant resistance circle. As the frequency becomes higher, the approximate output circuit appears to be g_c in parallel with a parasitic capacitor C_c. Thus, with increasing frequency, the locus moves along the constant conductance circle. Due to the effect of C_c, the trajectory appears in the capacitive region. The resulting locus is the combined locus that moves along the constant resistance circle at low frequencies, and moves along the constant conductance circle at high frequencies. Even though it is not shown here, with a further increase in frequency, S₂₂ follows a trajectory similar to that of S₁₁ due to the effects of bonding-wire inductors and C_μ.

From the simplified equivalent circuit of Figure 5.19, S₂₁ in Equation (5.16) is

Therefore, by using the low-frequency measurement data, the approximate value of g_m can be determined. Since the voltage across C_π decreases as the frequency increases, its magnitude decreases. It can also be seen that the phase increases in a clockwise direction. Similar to the FET explanation, we can also see in Equation (5.17) that for the low-frequency limit S₁₂ becomes

The phase of S₁₂ can also be seen to increase in a clockwise direction as the frequency increases. From the equation above, the magnitude also increases as the frequency increases.

In Figure 5.21, the BJT is first attached to the lead frame. It is worth noting that the bottom of the chip generally becomes the collector, as shown in Figure 5.13(b). Then, the base and emitter terminals are wire-bonded to the corresponding lead-frame terminals. Since the parasitic elements appearing at the emitter terminal from the assembly provide feedback from output to input, they have a significant effect on device performance. In order to minimize these parasitic emitter inductances due to the assembly, it is common to assign two terminals to the emitter.

After the assembly, the wire-bonded chip is molded using an epoxy material. Then, the lead terminals are appropriately cut from the lead frame to be used as a packaged device. This packaging for a BJT will result in performance degradation at high frequencies as in the case of an FET.

The BE junction of the GaAs HBT is formed by using the n-type AlGaAs emitter and the p-type GaAs base. Thus, an energy trap occurs between the AlGaAs and GaAs heterojunction. The energy trap is useful for suppressing the diffusing holes from the base toward the emitter that appears for a forward-biased BE junction. The diffusing holes are easily trapped and therefore the holes’ diffusion is significantly suppressed. Due to the energy trap, the doping of the base region can be increased. As a result, the base resistance at high frequencies that limits device performance can be decreased. Therefore, the unit-gain frequency given in Equation (5.18) is increased.

Here, f_T is the cut-off frequency at which the short-circuit current gain becomes unity. The frequency f_max represents the maximum oscillation frequency at which the maximum power gain becomes unity.

As previously explained, the injected electrons from the emitter to the base arrive at the collector by diffusion. Thus, the base transit time τ_b is determined by the diffusion constant. The diffusion constant of electrons in the GaAs, D_n is four times larger when compared to that in the Si, and a smaller base transit time results. The base transit time τ_b is directly related to the cutoff frequency f_T. The smaller τ_b results in a further increase in f_max given by Equation (5.18).

The electrons arrive at the collector then move from the collector region by a drift mechanism and finally arrive at the collector terminal. Suppose that the devices fabricated using the Si and the GaAs have the same collector thickness. The drift velocity v_d of electrons in the GaAs is approximately six times faster than in the Si. As a result, the faster v_d will reduce the collector transit time, τ_d. The reduced τ_d also leads to a rise in f_T. Thus, due to such improvements, the GaAs HBT can be used up to 10 GHz. With more advanced processes, the GaAs HBT can be used up to the millimeter wave frequency.

Then, Equation (5.20) finds the emitter current I_E to be

Thus, the desired value of the emitter current I_E is obtained by varying the resistor R_E. In addition, since the RF output is usually taken from the collector, the voltage V_CE will be limited by the resistor R_C. In order to overcome the RF signal-swing limitation by the resistor R_C, an RF choke (RFC) is often employed instead of resistor R_C.

In the case of Figure 5.23(b), the base current I_B is obtained from Equation (5.21) as

Thus, the collector current I_C is subsequently given by Equation (5.22) as

The typically large variations in the value of β among units of the same device type appear. This will result in the large variations of the collector current I_C determined by Equation (5.22) and I_C may generally deviate from the design value. Consequently, the value of the resistor R_B should be adjusted to obtain the desired value of the collector current I_C. Compared with the DC bias circuit shown in Figure 5.23(b), the DC bias circuit that uses the emitter resistor shown in Figure 5.23(a) can yield a designed collector current insensitive to the variations in the values of β. Therefore, the DC bias circuit in Figure 5.23(b) is not generally used at low frequencies, while the DC bias circuit that uses the emitter resistor shown in Figure 5.23(a) is preferred for low-frequency applications.

However, the emitter terminal is usually grounded in an RF application, and a stable ground is needed for an RF application. When the bypass capacitor is added in parallel to the emitter resistor R_E in Figure 5.23(a) for the AC ground, many problems arise due to the unstable AC ground. Practically, this type of configuration is accompanied by unpredictable, small, parasitic elements between the emitter terminal and the ground. Even assuming an ideal bypass capacitor, in order to connect the capacitor in parallel with the resistor R_E, inevitably some land patterns and connection lines are required, which make it very difficult to correctly predict the impedance attached to the emitter terminal. In a worstcase scenario, the emitter’s parasitic impedance may cause oscillations or it may even significantly change the S-parameters of the BJT, which often leads to failure in obtaining the desired gain. Thus, although the circuit shown in Figure 5.23(a) supplies a stable DC collector current, this type of DC bias circuit should be avoided in an RF amplifier circuit, especially when using packaged BJTs. On the other hand, despite the flaws of the bias circuit shown in Figure 5.23(b), such as the device-to-device DC collector current change and the necessity for the adjustment of R_B, the DC bias circuit is preferred in RF amplifier applications because it provides a stable RF ground.

The next problem is the selection of the bypass capacitor C_P for isolating the RF circuit from the external bias circuitry. The bypass capacitor C_P, similar to the DC block capacitor, should be sufficiently large enough to behave as a short at the operating frequency. It is critical that the C_P should be placed so as not to affect the RF circuit. Careful consideration should be given in advance as to whether the flow of the RF signal could be affected. Obviously, when C_P is sufficiently large, the lower-frequency AC noise from the DC supply that may flow into the internal RF circuitry can be effectively blocked. However, a bypass capacitor chosen to block the low-frequency AC noise from the DC supply does not act as a short at the RF as discussed in section 2.3.1 of Chapter 2. Thus, to make a short circuit at the RF, two parallel capacitors or, occasionally, multiple capacitors in parallel are used. In this case, a small-value capacitor operating as a short at the RF and a large-valued capacitor to block the AC noise from the DC supply are selected.

In addition, the capacitor C_E is inserted to provide the RF ground. Since this capacitor bypasses the emitter resistor R_E, it is called a bypass capacitor. However, the bypass capacitor causes significant problems at high frequencies. A capacitor that can be a short at the RF must be chosen for C_E. However, in reality it is difficult to choose such capacitor. Although such a bypass capacitor can be chosen, extra connecting lines and land patterns are necessary to connect the chosen bypass capacitor in parallel to the emitter resistor R_E. As a result, the effects of the connecting lines and land patterns appear at RF and these effects should be also minimized. These effects are more pronounced as the operation frequency becomes higher and so the ground by the bypass capacitor as shown in Figure 5.24 is usually not recommended, except for oscillators and for amplifiers operating at frequencies below a few hundred MHz.

The RFC shown in Figure 5.24 acts as an open circuit at the operating frequency and opens the collector terminal. In the case of RFCs connected to the base, they open the base terminal from the bias resistors R₁ and R₂. In general, however, the RFC bandwidth is narrow and other resonance phenomena can appear. Note that RFCs are not necessary where a resistor can sufficiently ensure an open circuit for an RF. Thus, when resistors R₁ and R₂ are sufficiently large compared with the surrounding impedances, it is usually a good idea to use resistors alone without the addition of RFCs due to the broadband characteristic of the resistors. In contrast, the replacement of the collector RFC by a resistor is usually not recommended due to the DC collector current. Thus, it is necessary to use the RFC in spite of resonance and its narrowband property. In this case, the RFC is selected to resonate at the operating frequency since it opens at the resonance frequency.

Therefore, using Equation (5.24), a current I₁

will flow through resistor R₁. Current I₁ is the sum of the collector current of Q₂ and the emitter current of Q₁. The emitter current of Q₁ is equal to the base current of Q₂, which is negligible compared to the collector current of Q₂. Thus, I₁ is approximately equal to the collector current of Q₂. Therefore, we can see that the current flowing in the transistor Q₂ is determined by the resistor R₁ as in Equation (5.24), regardless of the β of the transistor. Note that the emitter terminal of transistor Q₂ is also directly grounded and the circuit retains the two advantages of the DC bias circuits shown in Figure 5.23. The disadvantage is that the supply voltage V_CC must be greater than the collector voltage of transistor Q₂. This becomes a serious problem when the collector current is large because the power loss due to the collector resistor R₁ is high. Bypass capacitors C_P are inserted to isolate the DC bias circuit from the RF circuit. The criteria for the selection of such capacitors are the same as for the selection of the bypass capacitor C_P previously described.

In Figure 5.26(a), the source resistor R_S is inserted, so that when the drain current flows, a voltage drop across resistor R_S appears, which is the voltage at the source V_S. Since the DC current does not flow through the gate, the gate DC voltage is 0. Therefore, the voltage V_GS between the gate and source is -V_S. This V_GS determines the drain current, which can be adjusted by changing the value of the resistor R_S. If a large value is selected for R_S, a large negative V_GS appears and the drain current becomes small. On the other hand, when R_S is small, a large drain current flows. As previously explained, since there is usually no DC current flowing in the gate, gate resistor R_G has no effect. The reason for inserting the gate resistor in the circuit is to protect the device. In abnormal operation, a positive voltage may appear across the gate and a large gate current flows, which can damage the FET. To prevent this, a resistor is often inserted in the gate for protection. The circuit in Figure 5.26(a) is called a self-bias circuit.

In Figure 5.26(b), two DC voltage sources are used. A negative DC voltage is applied to the gate while a positive voltage is applied to the drain. Thus, the drain current is adjusted by voltage –V_GG. The reason for inserting resistor R_G in the gate is the same as for that shown in Figure 5.26(a). The resistor inserted in the drain sets the drain-source DC voltage. Resistor R_D may not be needed in RF circuit applications. In addition, the pros and cons of two DC bias circuits are the same as those for the BJT DC bias circuits. Figure 5.26(a) shows a stable DC drain current, while Figure 5.26(b) shows a stable RF ground.

Figure 5.27 illustrates an active DC bias circuit of an FET. The transistor Q₁ is a low-frequency DC-biasing pnp transistor, while Q₂ represents an RF FET. The resistors R₂ and R₃, as in the case of the BJT active DC bias circuit, divide the supply voltage. The difference from the active DC bias circuit shown in Figure 5.25 is that both negative and positive voltages are used in the FET active DC bias circuit. The base voltage determined by the voltage division then determines the current through the resistor R₁. The current through R₁ is equal to the sum of the currents flowing through the transistors Q₁ and Q₂. Because most of the emitter current of Q₁ appears at the collector, the negative voltage that results from the voltage division appears at the gate of the FET, and this determines the DC current flowing in the drain of the FET. This method for isolating the DC bias circuit is similar to that of the BJT. Also, the resistor R₆ inserted in the gate is intended to protect the FET from damage when, in an abnormal operation, a large current flows as a result of possible positive voltage appearing at the gate.

A real measurement using test equipment is similar to the same S-parameter simulation shown in Figure 5.28. The DC feed in Figure 5.28 is a component representing an RFC that becomes a short for the DC and an open for the RF. The DC block represents a component that is open at the DC and short for all the RF frequencies. The gate and drain voltages are set to V_GS = –1 V and V_DS = 3 V. Note that the bypass capacitors for DC voltage supplies are not necessary because the DC voltage source provides a complete short at AC.

Figure 5.29 shows the S-parameter simulation results. When the S-parameter simulation is performed with this setup, DC analysis will automatically be performed in advance without the need to specify it separately. At the established DC operating point, the FET will be converted automatically into the corresponding small-signal equivalent circuit, and the S-parameters of the FET will be computed. The computed S-parameters will show the previously explained frequency dependencies.

Figure 5.30 shows a BJT S-parameter simulation setup. It is similar to an FET S-parameter simulation. The only difference is that a DC current source is used for DC biasing the base. Since the operating point of the BJT is usually determined by the DC collector current, the corresponding base current is supplied by the current source. In addition, because the DC current source is open at the AC, an RFC will not be needed. The calculated S-parameters of this set up are shown in Figure 5.31.

Figure 5.32 shows a T-type equivalent circuit. We will show that the derivation of the T-type equivalent circuit from the Z-parameters is converted from the measured S-parameters. From the definition of the Z-parameters, the port voltages can be expressed as

Since the voltage V₁ at port 1 in Figure 5.32 depends on the currents I₁ and I₁ + I₂, by rewriting Equation (5.25), we obtain Equation (5.27):

Thus, comparing Equation (5.27) with V₁ of Figure 5.32, Z_A and Z_B are expressed in Equations (5.28) and (5.29).

Also, by arranging voltage V₂ at port 2 as determined by I₂ and I₁ + I₂, and arranging the remaining terms as determined by the current I₁, we obtain

V₂ = z₂₁I₁ + z₂₂I₂ = z₁₂(I₁ + I₂) + (z₂₂ – z₁₂) I₂ + (z₂₁ – z₁₂) I₁

Comparing the equation above with V₂ derived from the circuit in Figure 5.32 yields Equations (5.30) and (5.31).

Using Equations (5.28) through (5.31), the circuit in Figure 5.32 can be represented using Z-parameters as shown in Figure 5.33.

Similarly, Y-parameters can be represented by a π-type equivalent circuit. Figure 5.34 shows a π-type equivalent circuit.

Note that when two port voltages are present simultaneously, the current flowing from port 1 to port 2 depends on the voltage difference V₁ – V₂. Thus, current I₁ at port 1 can be expressed as

I₁ = y₁₁V₁ + y₁₂V₂ = –y₁₂(V₁ – V₂) + (y₁₁ + y₁₂)V₁

Similarly, current I₂ at port 2 can be expressed as

I₂ = y₂₁V₁ + y₂₂V₂ = –y₁₂ (V₂ – V₁) + (y₂₂ + y₁₂) V₂ + (y₂₁ – y₁₂) V₁

Using the two equations above, we can obtain the π-type equivalent circuit shown in Figure 5.34.

The equivalent circuits in Figure 5.33 and Figure 5.34 are general examples and can be further simplified for passive devices. The equivalent circuit for a passive device is shown in Figures 5.35(a) and (b), respectively. By the reciprocity z₁₂ = z₂₁ and y₁₂ = y₂₁ in the Z- and Y- parameters, the controlled sources disappear in the passive device’s equivalent circuits.

The equivalent circuits in Figures 5.35(a) and (b) are useful for analyzing unknown inductors or capacitors. Practically speaking, (z₁₁ – z₁₂), z₁₂, and (z₂₂ – z₁₂) in the T-type equivalent circuit, and (y₁₁ + y₁₂), y₁₂, and (y₂₂ + y₁₂) in the π-type equivalent circuit may not be represented by a single element such as an inductor or a capacitor, and they may show a frequency dependence. In this case, the frequency dependence of each element can be further decomposed and represented by the complex circuit that consists of frequency-independent elements, as explained in Chapter 2. In addition, using a similar technique, a multiport passive device can be represented in a similar way. The reader may wish to consult reference 8 at the end of this chapter for details.

We now present the method for obtaining the values of the simplified small-signal equivalent circuit shown again in Figure 5.36(a) from the measured S-parameters.² The π-type equivalent circuit in Figure 5.36(b) is similar to the simplified equivalent circuit of an FET. Therefore, by directly matching the simplified FET equivalent circuit to the π-type equivalent circuit, the values of the simplified equivalent circuit can be directly obtained from the measured S-parameters. First, comparing the output impedances of the two circuits in Figures 5.36(a) and (b), the admittance of R_ds||C_ds should be equal to y₂₂ + y₁₂. From this comparison, we obtain Equations (5.32) and (5.33).

2. K. W. Yeom, T. S. Ha, and J. W. Ra, “Frequency Dependence of GaAs FET Equivalent Circuit Elements Extracted from the Measured Two-Port S-parameters,” Proceedings of the IEEE, vol. 76, no. 7, pp. 843–845, July 1988.

Similarly, comparing y₁₂ and C_gd, we obtain Equation (5.34).

Comparing the input impedances of the two circuits, we obtain Equation (5.35).

Rewriting Equation (5.35), R_i and C_gs can be determined using Equations (5.36) and (5.37).

However, the control voltages are different in the dependent sources shown in Figures 5.36(a) and 5.36(b). In the case of Figure 5.36(a), voltage V_gs across C_gs is the control voltage, while in the case of Figure 5.36(b), the control voltage is V₁. The relationship between V₁ and V_gs is

Also,

(y₂₁ – y₁₂) V₁ = y_m V_gs

Using these two equations, g_m can be obtained with Equation (5.38).

And τ is determined with Equation (5.39).

Using Equations (5.32) through (5.39), we find that the values of the simplified equivalent circuit of FET can be directly determined from the measured S-parameters.

From Example 5.2, we can determine the simplified FET equivalent circuit element values. Figure 5.37 again shows the equivalent circuit of a chip FET. The equivalent circuit is known to predict quite closely the measured S-parameters of a chip FET.

The difference between the chip FET and the simplified equivalent circuits is in R_g, R_s, and R_d, which are called extrinsic elements. A method for determining the chip FET equivalent circuit element values, which is similar to the extraction of the simplified equivalent circuit, does not exist at present. The values of R_g, R_s, and R_d were previously determined by optimization, which yields the best fit to the measured S-parameters. However, because resistors R_g, R_s, and R_d in the active state of a FET make only a small contribution to the S-parameters, there is significant uncertainty about their values when determined by this method, and obtaining their exact values is difficult.³ If we assume that R_g, R_s, and R_d do not change even when the DC operating point changes, their values may be determined more accurately using the measured S-parameters at other DC operating points where their effects are dominant. Thus, such operating points should be found first, after which their values can be extracted more accurately.

3. R. L. Vaitkus, “Uncertainty in the Values of GaAs MESFET Equivalent Circuit Elements Extracted from the Measured Two-Port Scattering Parameters,” presented at the 1983 IEEE Cornell Conference on High Speed Semiconductor Devices and Circuits, Cornell University, 1983.

The operating points of V_GS = 0 V and V_DS = 0 V are thought to be suitable for the extraction of R_g, R_s, and R_d. At this bias point, the FET completely becomes a passive device, and the equivalent circuit appears, as shown in Figure 5.38. The zero-bias depletion capacitance C_b appears, and will appear on both the source and drain sides. Because there is no change in the values of R_g, R_s, and R_d, their values are the same as in active mode. The measurement at V_GS = 0 V and V_DS = 0 V is often referred to as a cold-FET measurement.⁴ Even in the cold FET condition, because the values of R_g, R_s, and R_d are typically small, and the impedance of the depletion capacitance C_b is usually very large, it is difficult to determine their values accurately when measurement errors occur.

4. G. Dambrine, A. Cappy, F. Helidore, and E. Playez, “A New Method for Determining the FET Small-Signal Equivalent Circuit,” IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 7, pp. 1151–1159, July 1988.

To overcome this problem, a small positive voltage is applied to the gate terminal, which makes the gate drain and gate source behave like Schottky diodes. The Schottky diodes then begin to conduct for a small positive voltage and so the contribution of C_b disappears. Instead, a small-signal resistance of a Schottky diode appears. In addition, the channel resistance is formed between the drain and source terminals. Since the effect of the channel resistance appears in a distributed form, it must be considered as a distributed circuit. However, the circuit’s distributed effect is not pronounced and so it can be regarded as a lumped element. With the channel resistor considered, the Z-parameters are expressed in Equations (5.40)–(5.42).

Resistor R_c represents the channel resistance, and nkT/qI_g of z₁₁ represents the small-signal Schottky diode resistance that is dependent on the DC gate current I_g. The different contributions of R_c to z₁₁, z₁₂, and z₂₂ are because the effect of the distributed channel resistance yields different contributions to z₁₁, z₁₂, and z₂₂. From Equations (5.40) through (5.42), we find that only z₁₁ depends on the small-signal Schottky diode resistance. Thus, the term that excludes the small-signal Schottky diode resistance can be found by plotting Re(z₁₁) versus Schottky diode current I_g. Figure 5.39 shows a plot of Re(z₁₁) versus I_g. Using this plot, the term that excludes the small-signal Schottky diode resistance in Equation (5.40) can be found from the intercept value obtained by extrapolating the straight line.

However, using Equations (5.40) through (5.42), the values of R_g, R_s, and R_d cannot be determined because there are four unknowns but only three available equations. Therefore, a separate independent measurement is necessary. There are two methods: The first is to use the Fukui method, with which the value of R_s + R_d can be determined.⁵ The second is to directly measure the DC gate resistance in a device. Then, the values of R_g, R_s, and R_d can be determined.

5. H. Fukui, “Determination of the Basic Device Parameters of a GaAs MESFET,” Bell System Technical Journal, vol. 58, no. 3, pp. 771–795, March 1979.

6. G. Dambrine, A. Cappy, F. Helidore, and E. Playez, “A New Method for Determining the FET Small-Signal Equivalent Circuit,” IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 7, pp. 1151–1159, July 1988.

Using the obtained values of R_g, R_s, and R_d, the remaining values of the chip FET equivalent circuit in Figure 5.37 can be determined from the measured S-parameters in active mode. Figure 5.40 shows the method for removing the contribution of resistors R_g, R_s, and R_d from the measured S-parameters in the active mode. Then, the remaining circuit is a simplified FET equivalent circuit (or intrinsic equivalent circuit of an FET). By converting the resulting S-parameters into Y-parameters, the values of the simplified equivalent circuit can be determined, as shown in Example 5.2.

• The principles of operation for small- and large-signal models, and for the typical S-parameters of GaAs MESFET are introduced.

• A GaAs pHEMT has multiple epi-layers and its electron mobility in a channel is improved by removing the impurity scattering that occurs in a GaAs MESFET.

• The base width of a high-frequency Si BJT is minimized to the limit that the process allows and the interdigital structure is employed to implement the base and the emitter in order to reduce the base-spreading resistance.

• The operations of small- and large-signal models, as well as the typical S-parameters of BJT, are explained.

• In a GaAs HBT, the base-emitter junction is implemented using a heterostructure. As a result, the current gain β is not degraded for high base-region doping, which makes it possible to implement small base-spreading resistance. The diffusion in p-type GaAs is faster than that in an Si, which results in the improvement of f_T. Also, the collector drift is reduced because the electron mobility is faster than that in an Si. Combining these facts, the high-frequency performances of the GaAs HBT are superior to those of the Si BJT.

• Self-bias and two-supply DC bias circuits are introduced. The two-supply DC bias circuit has an advantage over the self-bias circuit in providing a stable ground.

• The extraction of a GaAs FET equivalent circuit from S-parameters is explained.

2. G. Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, 2nd ed. Englewood Cliffs, NJ: Prentice Hall, 1997.

3. R. Soares, J. Graffeuil, and J. Obregon, Applications of GaAs MESFETs, Dedham, MA: Artech House, Inc., 1983.

4. J. M. Golio, Microwave MESFETs and HEMTs, Dedham, MA: Artech House, Inc., 1991.

5. J. Mun, ed., GaAs Integrated Circuits, Oxford: BSP Professional Books, 1988.

6. H. Fukui, ed., Low-Noise Microwave Transistors and Amplifiers, New York: IEEE Press, 1981.

7. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE, 2nd ed. New York: McGraw-Hill, Inc., 1993.

8. N. Marcuvitz, Waveguide Handbook, Vol. 2 of the MIT Radiation Laboratory Series. New York: Dover Publications, Inc., 1965.

(1) Calculate the S-parameters setting the reference impedance to Z_o.

(2) Setting Z_o = 50 Ω, compute g_m when S₂₁ = 5∠180°.

(3) When resistor R_f is connected in parallel, as shown in Figure 5P.2, find the value of R_f that makes S₁₁ = 0.

5.2 Figure 5P.3 shows a simplified equivalent circuit of an FET with a source resistance R_s at low frequency. Due to R_s, the equivalent transconductance g_me is lowered from g_m, as explained in Example 5.3. Defining the equivalent transconductance g_me as

show that

5.3 The small-signal equivalent circuit of a GaAs MESFET, including wire bonding, can be approximately represented by Figure 5P.4; given the following S₁₁, determine the values of R_i and L_g. (C_gs = 0.5 pF).

5.4 In the following active DC bias circuit (Figure 5P.5), determine the value of resistor R₁ for a 20 mA current to flow into the collector of transistor Q₂.

5.5 (ADS problem) Using the 2SC4226 in the ADS library, set up the circuit shown in Figure 5P.6 below.

(1) Determine its I_C–V_CE characteristics as shown in Figure 5P.7. (I_B = 20 μA – 160 μA, with a step of 20 μA.)

(2) Compute the S-parameters at V_CE = 5 V and I_C = 5 mA for a frequency range of 1–4 GHz with a step of 0.05 GHz.