Chapter 9. Power Amplifiers

As shown in Figure 9.1, at a low input power P_in, the output power P_L increases in proportion to the input power. However, at a high input power, the output power shows a marginal increase. A further increase in the input power drives the output power of the amplifier into saturation. A point with a 1-dB deviation from the linear output power is referred to as the 1-dB compression point of an amplifier and the output power level at saturation is called the saturated power of an amplifier. As discussed in Chapter 8, an amplifier with maximum small-signal gain can be designed by selecting appropriate source and load impedances computed from the measured small-signal S-parameters at a given DC bias. The designed maximum small-signal gain amplifier generally gives a high gain but also has a lower 1-dB compression point and saturated power compared to an amplifier designed to give maximum output power as shown in Figure 9.1. This is not a special case but a general fact.

To explain this qualitatively, a simplified large-signal FET equivalent circuit is shown in Figure 9.2. Here, the current source I_DS, which depends on the gate-source and drain-source voltages, has the characteristics shown in Figure 9.3. In addition, excluding the current source I_DS, all the other elements in the equivalent circuit of Figure 9.2 are assumed to be linear elements since they typically have low nonlinearity.

The maximum small-signal gain at the operating point Q can be achieved when the load is conjugate matched to the output impedance. Thus, the impedance Z_L of Figure 9.2 must satisfy Z_L = r_DS = (∂I_DS/∂V_DS)^–1. This causes the load line to have a slope of (r_DS)^–1, as shown in Figure 9.3. However, the load line that gives maximum output power is obviously the load line represented by the solid line in Figure 9.3. Since the gain is approximately proportional to g_mR_L, the gain of the amplifier based on the small-signal design is clearly higher than that based on the large-signal design. Yet the amplifier based on the small-signal design has a low saturated power and it generally reaches saturation early as shown in Figure 9.1. The small-signal design clearly does not exploit the maximum output power capability that the active device can supply.

Figure 9.4 shows a power amplifier configuration. The power amplifier can be represented by a block diagram that is similar to a low-noise amplifier. Therefore, the source and load reflection coefficients Γ_S and Γ_L,opt must be determined by experimental or theoretical means in order to design the power amplifier. When Γ_S and Γ_L,opt have been determined, the matching circuit can be constructed similar to that of the low-noise amplifier design. The slight difference between the power amplifier and the low-noise amplifier designs is that the input matching circuit losses must be minimized in the case of the low-noise amplifier design, whereas in the power amplifier design, it is the output matching circuit losses that must be minimized. The input matching circuit losses in the low-noise amplifier are directly associated with noise-figure degradation. By denoting the loss at the input matching circuit as L(dB) and the noise figure of the active device as F(dB), then the noise figure of the low-noise amplifier as explained in Chapter 4 is approximately given by L + F(dB). Thus, for a minimum noise figure, the input matching circuit must be constructed so as to have minimum losses. On the other hand, because the loss in the output matching circuit is directly related to the loss in the output power, the loss in a given output matching circuit must be minimized in the case of the power amplifier.

The impedance Z_L,opt in Figure 9.4 that gives maximum output power can easily be inferred from the DC characteristics in Figure 9.3 at low frequency; however, at high frequency, due to the complexity of the equivalent circuit of the active device and the parasitic elements of its package, it is not easy to derive Z_L,opt analytically. In a case where the large-signal equivalent circuit is known, the optimum impedance Z_L,opt can be obtained at the reference plane of the current source I_DS in Figure 9.2. Using Z_L,opt, the optimum impedance at the output terminals of the package can also be obtained by taking the external parasitic elements into consideration. However, unlike at low frequency, the reference plane of the current source I_DS in the large-signal equivalent circuit is generally not obvious at high frequency. Thus, Z_L,opt is usually determined experimentally through a load-pull measurement or with simulation; that is, load-pull simulation using software when the large-signal model is available. We will cover the determination of Z_L,opt using load-pull measurement and simulation in this chapter.

The next important issue in the implementation of a power amplifier is efficiency, which can be expressed in terms of RF output power for a given supplied DC power, and two definitions are widely used. The first is the collector or drain efficiency. Denoting the DC power consumed in the output terminal as P_DC and the RF output delivered to the load as P_L, the drain efficiency η_D is defined as shown in Equation (9.1).

Here, V_DD represents the DC supply voltage and I_D is the DC supply current when the delivered power to the load at RF is P_L. To some extent, the drain efficiency may be a good measure for representing the efficiency of an amplifier when the amplifier gain is sufficiently high; however, the gain is usually not high enough at a high frequency. Consequently, the input power P_in must be considered in the definition of the efficiency. In general, PAE (power-added efficiency) is used in the definition of efficiency at a high frequency and it is defined in Equation (9.2).

This definition of PAE can be interpreted as the ratio of the output power added by the active device to the DC power supplied to the active device.

The DC biased amplifier shown in Figure 9.3 is usually classified as a class-A amplifier; the problem with this type of amplifier is that its maximum efficiency does not exceed 50%; that is, for the maximum output as shown in Figure 9.3, the approximate drain efficiency can be seen to be

In order to understand the efficiency problem in a class-A amplifier, consider an example of this amplifier with a 20 W RF output power. Even if its efficiency is given as the maximum value of 50%, out of the total 40 W power supplied, 20 W is consumed while 20 W is delivered to the load. This will be more problematic in the absence of any RF input power. The total supplied DC power of 40 W to the active device would be consumed by that device in the absence of the RF input power, and all the supplied DC power would be converted into heat. Therefore, power consumption of the class-A amplifier is most problematic in the case where there is no RF input power. This problem can be solved by changing the active device’s operation and there are various operation techniques for improving efficiency, which we will discuss in the next sections. However, designing the amplifier to improve its efficiency generally gives rise to the problem of distortion. Therefore, for a communication system that employs both amplitude- and phase-modulated signals, it is necessary to reduce the distortion to improve the amplifier’s linearity. The methods for improving linearity will also be explained in this chapter.

The energy band-gap is defined as the difference in energy between the conduction band and the valence band. Thus, a higher-energy band-gap means the valence-band electrons can seldom move into the conduction band because those electrons require energy sufficiently higher than the energy band-gap to move into the conduction band. On the other hand, when the energy band-gap is low, the valence-band electrons can easily move into the conduction band as they can readily attain the required energy. The energy band-gap is thus an important measure for estimating the breakdown voltage of an active device for a given semiconductor material. The breakdown voltage refers to drain or collector voltages where the drain or collector current increases very rapidly. Therefore, the useful range of an active device’s drain voltage is usually limited by the breakdown voltage.

The phenomenon of breakdown can be explained using electron collisions. The electrons accelerated by an applied drain voltage collide with atoms at the drain, thereby generating electrons. When a drain voltage higher than the breakdown voltage is applied, the generated electrons thus attain sufficient energy to move into the conduction band and contribute to the drain current. As a result, the drain current increases rapidly due to the contribution of electrons generated by the collision. However, when the energy band-gap is high, the electrons generated by the collision with the accelerated electrons cannot attain sufficient energy to move into the conduction band. Thus, a high-energy band-gap semiconductor is typically associated with a high breakdown voltage. Due to this fact, when an active device is fabricated with a high-energy band-gap semiconductor, the active device shows a high breakdown voltage; a high DC bias voltage can then be applied and a large output power will be obtained. Therefore, a high-energy band-gap semiconductor is suitable for use as a high-power active device.

Thermal conductivity represents a material’s ability to conduct heat. A higher thermal conductivity means the heat generated in an active device due to power consumption is easily dissipated. As we have seen previously, no matter how well a power amplifier is designed, a portion of the supplied power is consumed as heat. The heat generated increases the temperature of the active device, which can damage the device if the heat exceeds the absolute maximum temperature for the device. A well-designed heat-dissipation structure such as a heat sink may help an active device endure a certain temperature increase, but the amount of heat dissipated will be fundamentally limited by the thermal conductivity of a given semiconductor. Therefore, thermal conductivity is an important parameter for the semiconductor materials used in power amplifiers.

The physical properties of various semiconductors are shown in Table 9.1. In that table, SiC and GaN have an excellent thermal conductivity compared with Si. Because the thermal conductivity of Si is comparable to that of a metal, SiC and GaN semiconductors are known to have a fairly good thermal conductivity. In contrast, GaAs has a lower thermal conductivity than Si by a factor of about one third. Thus, in terms of thermal conductivity, Si, GaN, and SiC semiconductors are suitable for the fabrication of active devices for a power amplifier. Next, in terms of an energy band-gap, SiC and GaN have a higher energy band-gap than Si by a factor of about 3. As a result, the fabricated active devices that use SiC and GaN show a breakdown voltage 3 times higher than that of Si. As a direct measure of breakdown voltage, the breakdown voltage in Table 9.1 is directly related to the breakdown voltage that is approximately 6 times larger in SiC and GaN compared to Si. Thus, a high DC supply voltage is possible with SiC and GaN, which leads to an increase in output power capability.

Therefore, it can be seen that SiC and GaN are suitable semiconductors for a power amplifier’s active devices, considering their thermal conductivity and energy band-gap. However, the electron mobility of SiC is lower compared to that of Si, and thus SiC active devices are inferior to Si active devices in high-frequency applications. Fortunately, the electron mobility in GaN depends on the condition of the heterojunction formation and this mobility can be made to exceed that in Si by using the heterojunction. An active device suitable for a high-frequency power amplifier can therefore be fabricated using a GaN process. Despite the GaN advantages, the late emergence of GaN devices is due to the lack of a suitable substrate for GaN growth. Recently, the technology for epitaxial-layer growth of GaN on SiC has seen significant advances, and the study of GaN-active devices continues to attract great interest.

Figure 9.5 shows the structure of a GaN HEMT formed on SiC. The reason for selecting an HEMT structure is primarily related to the electron mobility of GaN. As this mobility is not much superior to that of Si, its maximum exploitation is required. By employing an HEMT structure, maximum electron mobility can be obtained because that mobility in the channel can be achieved in the absence of impurities, as discussed in Chapter 5. The frequency characteristics of GaN active devices can therefore be improved although the electron mobility of GaN is not greatly superior to that of Si.

In Figure 9.5, an intrinsic GaN epitaxial layer is grown on SiC, on top of which an n–type AlGaN layer is formed for the heterojunction. The electron well created by the heterojunction is formed in the epitaxial layer of the intrinsic GaN, and the doped electrons in the AlGaN are collected in the electron well and thus move through a channel free from impurity atoms. Therefore, great improvement in the frequency characteristics is possible. The T-shaped gate terminal on the n–AlGaN layer in Figure 9.5 minimizes the resistance of the gate terminal and decreases the gate length, and thus improves the frequency characteristics. Note that the drain and source terminals are formed on the n+ GaN layer for ohmic contact.

Figure 9.6(a) is a photograph of a GaN HEMT. The breakdown drain voltage V_DS is reported to be 142 V. This is an advantage that results from the physical properties of a GaN semiconductor. Figure 9.6(b) shows the measured output characteristics of the GaN HEMT at a frequency of 9.3 GHz. The device shows a gain of about 14 dB, and a saturated power of about 35.7 dBm. The PAE is found to be about 40% at 35.7 dBm. The output power per unit gate width is estimated to be 3.7 W/mm.

The frequency characteristics of a 0.25-μm GaN HEMT from Cree, Inc., are shown in Figure 9.7. In that figure, the frequency f_max is approximately 50 GHz where the maximum power gain U in Chapter 8 is 1. The frequency f_T is near 20 GHz where the short-circuit current gain h₂₁ is 1. The f_max and f_T are comparable to the frequency characteristics of a GaAs MESFET. Considering the performances given in Figures 9.6 and 9.7, which were obtained from the initial stages of the GaN process, significant improvements are expected in the future.

1. Cree, Inc., datasheet, CGHV1J006D (the S-parameters are at V_DS = 40 V, I_DS = 60 mA); available at www.cree.com/RF/Products/General-Purpose-Broadband-40-V/Discrete-Bare-Die/CGHV1J006.

Figure 9.8 shows a cross-section of the LDMOSFET. In that figure, the drain region is laterally divided into a lightly doped region (NHV) and highly doped region (n + Drain) for the ohmic contact. In addition, the drain terminal is located at a considerable distance from the channel, which causes the accelerated electrons in the channel to primarily collide in the drain region with a low impurity concentration; as a consequence, the electrons lose energy when they reach the n+ drain region. Thus, this leads to a higher breakdown voltage compared with the case in which the electrons collide directly in the highly doped drain region.

2. Motorola, Semiconductor Technologies for RF Power F701, 2002.9.24.

The next thing to note is that the source terminal is attached to the bottom of the device, which means that wire bonding is not required to connect the source terminal to the ground. A simple die attachment on the metal carrier is sufficient for the connection of the source terminal to the ground. Thus, the inductance that would otherwise arise from the wire bonding during packaging assembly is eliminated, which is an advantage during assembly. Figure 9.9 shows the electric-field simulation around the drain terminal that has a strong electric field across the NHV region, while the n+ drain region can be seen to have a weak electric field. As a result, the generation of electrons by collision occurs primarily in the lightly doped NHV region, where the number of those electrons is relatively smaller. This leads to a higher breakdown voltage than in the case of direct collision.

3. Ibid.

The manufacturing technology for LDMOSFETs is well-established. An LDMOSFET device that can supply up to several hundred W of RF power has been reported in the literature. However, the physical properties of Si limit its operation below the 4-GHz frequency region as the gain becomes low.

In designing a low-noise amplifier, the optimum source and load impedances can be calculated directly from the measured small-signal S-parameters at a given DC bias. However, because the power amplifier basically operates in the large-signal region, the optimum load impedance cannot be determined using the small-signal S-parameters. Therefore, the optimum load impedance is determined either from direct experimental measurement or computed from the large-signal model prior to creating the power amplifier design. In this section, we will describe the method of obtaining the optimum load impedance by the experimental method as well as by a computational method that uses software.

In the case of low harmonics, the optimum load impedances can easily be obtained from the previous load-pull measurement. However, a problem does occur when the harmonic impedances must be considered. In general, the maximum output power is determined from the load impedance of the fundamental frequency, but the efficiency varies according to the harmonic load impedances. Recently, an impedance tuner that can independently tune the harmonic load impedances in order to resolve the harmonic tuning problem has been reported in the literature. A photograph of a harmonic impedance tuner is shown in Figure 9.11. Most recent impedance tuners can also be controlled by a PC, and their impedances can be read without disassembling them from the load-pull setup for the impedance measurement. The PC-controlled impedance tuners also provide utilities that draw a contour plot of the impedance, yielding the same output power or efficiency from measured data. Measuring the optimum source and load impedances using the load-pull method assists in the convenient and reliable design of power amplifiers.

There is another method for designing and fabricating power amplifiers experimentally without relying on load-pull measurements. An example of this method is shown in Figure 9.12. Using this method, a power amplifier’s design allows for adjustable input and output matching circuits that use the optimum impedances in the datasheet, and the power amplifier is designed by adjusting the input and output matching circuits with a given RF input power and DC bias. Once the required specifications such as output power, efficiency, harmonic characteristics, and intermodulation are met, then the adjusted power amplifier can be used as a power amplifier if there are no other problems in size and mass production. However, the size of the power amplifier may be too large for some applications and further miniaturization may be required for those applications. Unlike the power amplifier shown in Figure 9.12, a power amplifier without tuning points may also be necessary for mass production. In those cases, the power amplifier shown in Figure 9.12 is disassembled and the source and load impedances are measured with a network analyzer as in a load-pull measurement. A miniaturized power amplifier can then be redesigned using the measured impedances.

In Figure 9.12, the chip capacitor in the input matching circuit is for input tuning and its position and value can be moved by soldering. Thus, the input matching circuit can be adjusted by trial and error until the optimum input impedance is obtained. The output matching circuit can be similarly adjusted. Thus, the output matching can be achieved through these adjustments.

The advantage of the adjustable circuit impedances is that the power amplifier can be designed without the cumbersome task of modeling the active devices, so the characteristics of the fabricated power amplifier can be determined experimentally, which otherwise would be difficult to predict accurately with the large-signal equivalent circuit. The disadvantage is that because the adjustable range of the input and output matching circuit impedances is limited compared to that in the prescribed load-pull measurement, the input and output matching circuits must be designed to provide the desired input and output matching impedances. Otherwise, the designated goal cannot be achieved. In addition, when changes occur in the DC operating point or input power for a new power amplifier, the obtained input and output matching impedances are not generally optimal for those changed conditions. Therefore, to obtain the optimum input and output impedances when those conditions change, the adjustable power amplifier in Figure 9.12 should be retested using the method discussed above that includes adjusting component values and positions. In the case of mass production, tolerance analysis may also be necessary; however, this method can present difficulties in terms of predicting the effects of parameter changes in an active device or in power amplifier’s matching circuits.

When the large-signal model of an active device is available, this method involves setting up a load-pull simulation circuit in ADS, as shown in Figure 9.13, and calculating the desired optimum source and output load impedances; see reference 1 at the end of this chapter. This approach is frequently used in the design of an MMIC (monolithic microwave integrated circuit) power amplifier.

However, in the case of a packaged active device, the equivalent circuit should take into account the parasitic elements that occur in packaging and may cause the equivalent circuit to become extremely complex and may degrade its accuracy. The advantage that the load-pull simulation method has over the experimental load-pull method is that the optimum source and load impedances can be obtained simply through simulation that reflects the changes that may occur in the power amplifier’s circuit conditions, such as frequency and the DC bias operating point. In contrast, with the experimental load-pull method, each time the power amplifier’s condition changes—for example, if the frequency is changed—a new measurement must be taken to obtain the optimum source and load impedances. The disadvantage is that because it is not easy to obtain the accurate large-signal model, the large-signal model itself includes a certain degree of inaccuracy, which makes the accuracy of the results problematic.

VAR

global Impedance Equations

;Tuner reflection coefficient

LoadTuner=LoadArray[iload]

LoadArray=list(0,rho,fg(Z_l_2),fg(Z_l_3),fg(Z_l_4),fg(Z_l_5))

iload=int(min(abs(freq)/RFfreq+1.5,length(LoadArray)))

fg(x)=(x-Z0)/(x+Z0)

;Source impedances

Z_s=SrcArray[isrc]

SrcArray=list(Z0,Z_s_fund, Z_s_2, Z_s_3,Z_s_4, Z_s_5)

isrc=min(iload,length(SrcArray))

Measurement Expression 9.1 Source and load impedance setup

Measurement Expression 9.1 is the opened view of the globalImpedanceEquations. The value of LoadTuner here represents the resulting load impedance. The function fg(∙) is defined to convert the given harmonic load impedances into the corresponding reflection coefficients. The row vector, LoadArray, is formed using the converted reflection coefficients at each harmonic frequency. The function list(∙) is used to form a vector. Here, the first value of the LoadArray is the reflection coefficient at DC and the second value is the reflection coefficient at the fundamental frequency. All the values are set this way up to the fifth harmonic. It should be noted that the load impedance is open at DC because the reflection coefficient at DC is set to 0. The reflection coefficient of the fundamental frequency in LoadArray is set to rho, which is defined by the variable block named SweepEquations in Figure 9.13.

Figure 9.14 shows the desired frequency-dependent load reflection coefficient. Thus, the load reflection coefficient is Γ_L = ρe^jφ for frequency 0.5f_o < f < 1.5f_o. The ranges of other harmonic frequencies are defined similarly to the fundamental frequency. The variable LoadTuner in Measurement Expression 9.1 represents the frequency-dependent load reflection coefficient shown in Figure 9.14 and it is synthesized using the row vector LoadArray.

In Measurement Expression 9.1, the frequency-dependent load reflection coefficient LoadTuner is implemented using the index of the row vector LoadArray. The variable iload represents the index. Define k as expressed in Equation (9.3).

When 0.5 × RFfreq < freq < 1.5 × RFfreq, the range of k is 2 < k < 3 from Equation (9.3). Also, it can be found that length(LoadArray) = 6. A smaller value between the two values for length(LoadArray) and k is selected using the min(∙) function. For 2 < k < 3, the smaller value becomes k. Thus, taking the integer part of k and using the int(∙) function gives a value of 2. Therefore, the value of iload becomes 2. The value of LoadTuner = LoadArray[iload] is the value corresponding to the index 2, which is Γ_L = ρe^jφ. When 4.5 × RFfreq < freq, it becomes k > 6 from Equation (9.3). The smaller value thus becomes length(LoadArray) = 6. The corresponding reflection coefficient to index 6 is found to be fg(Z_l_5). With similar reasoning, it can be found that the frequency-dependent reflection coefficient LoadTuner shown in Figure 9.14 is synthesized.

It can be seen that the source reflection coefficient is determined in a similar way in Measurement Expression 9.1. The variable Z_s represents the frequency-dependent source reflection coefficient. The variable SrcArray is the row vector of the source reflection coefficients at each harmonic. The index that determines the value of the source reflection coefficient is isrc. It should be noted that the value of SrcArray at DC is set to the reference impedance Z0.

The simulation for the samples in Figure 9.15(b) can be carried out by sweeping the value of Γ_x for a given Γ_y when the load reflection coefficient is defined as Γ_L = Γ_x + jΓ_y. In Figure 9.16, the sweep variables real_indexs11 and imag_indexs11 are defined to represent Γ_x and Γ_y. In the simulation schematic of Figure 9.16, harmonic balance simulation sweeps the value of Γ_x for a given Γ_y in the parameter sweep. The user must specify a number of samples and a region of the circle to be sampled. This is done by entering the number of samples and the center and radius of the circle. The variable block named SweepEquations in Figure 9.16 includes the necessary variables. The variables s11_center, s11_rho, and pts represent the center, the radius, and the number of samples. Using the user-specified variables, the number of lines in the direction of the y-axis, lines, and the number of samples per line, pts_per_line, are calculated and set in the variable SweepEquations VAR, which is hidden. Measurement Expression 9.2 is an opened view of SweepEquations.

real_indexs11=0

imag_indexs11=0

Z0=50

index_s11=real_indexs11+j*imag_indexs11

s11_rho=0.75

s11_center=-0.6+j*0.2

max_rho=min(1.0-mag(s11_center),mag(s11_rho))

pts=100

lines=max(int(sqrt(pts)),1)

pts_per_line=int(pts/lines)

argument=max_rho^2-(imag(s11_center)-imag_indexs11)^2

c_limit=sqrt(if(argument<0) then 0 else argument endif)

Measurement Expression 9.2 Opened view of the variable block named SweepEquations

The first two lines in the expression are for declaring the sweep variables real_indexs11 and imag_indexs11. Note that although they are set to 0, their values are newly defined through the parameter sweep. Variable index_s11 in the next line is the definition of Γ_L at the fundamental frequency using the variables real_indexs11 and imag_indexs11. The value of index_s11 is used as Γ_L instead of rho in the globalImpedanceEquations shown in Measurement Expression 9.1. Variables s11_rho and s11_center were described earlier and max_rho sets the new radius using the user-specified radius. This is necessary when the center and radius settings entered by the user are out of the unit Smith chart. Thus, the newly defined max_rho replaces the user-specified s11_rho.

Next, the number of lines in the direction of the y-axis, lines, is set using the total number of sample points, pts. Since the total number of sample points is proportional to the area, the variable lines is determined from sqrt(pts). The number of points per line, pts_per_line, then becomes the total number sample points divided by the number of lines, lines. Since lines and pts_per_line must be integers, the function int(⋅) converts them all into integers. Due to such definitions, the sample points at both ends of the sample lines will be tightly spaced, while they will be widely sampled around the center line.

After the settings are made, in the case of the x-axis, the sweep range from the left to the right should be specified. However, the sweep range varies according to the y-axis values. That is, given y, from the equation of a circle with radius r, the possible values of x in the circle are represented by –(r² – y²)^½ ≤ x ≤ (r² – y²)^½. The value (r² – y²)^½ is represented by argument. To prevent the argument from being 0, the variable c_limit is newly defined. Therefore, the variable real_indexs11 corresponding to the x-axis reflection coefficient is swept from real(s11_center)–c_limit to real(s11_center)+c_limit, as shown in Figure 9.16. The y-axis reflection coefficient could have been swept in the range imag(s11_center)-max_rho<y<imag(s11_center)+max_rho for the number of lines. However, when lines = 2, y sweeps the two points at the end of the radius, an undesirable situation. Thus, at the end of the radius, the range is set to sweep above and below the line by a sweep range of max_rho/(lines + 1), as shown in Figure 9.17.

Vs_l=exist(“real(Vs_low[0])”)

Vs_h=exist(“real(Vs_high[0])”)

Is_l=exist(“real(Is_low.i[0])”)

Is_h=exist(“real(Is_high.i[0])”)

Pdc=Is_h*Vs_h+Is_l*Vs_l+1e-20

Measurement Expression 9.3 Equations in the display window for calculating the DC power consumption

Pdel_Watts=real(0.5*vload[1]*conj(Iload.i[1]))

Pavs_Watts=10**((Pavs[0,0]-30)/10)

PAE=100*(Pdel_Watts-Pavs_Watts)/Pdc

Pdel_dbm=10*log10(Pdel_Watts)+30

Measurement Expression 9.4 Equations for calculating the power delivered to the load

Measurement Expression 9.4 shows the equations for calculating the power delivered to the load and the efficiency of using DC power consumption obtained from the load-pull simulation. The first line of this expression calculates the delivered power at the fundamental frequency. However, when a power probe P_Load is used, as shown in Figure 9.16, the first line changes as shown in Measurement Expression 9.5.

Pdel_Watts=P_Load.p[1]

Measurement Expression 9.5 Equation for the delivered power using the power probe

The second line in Measurement Expression 9.4 calculates the input power using a variable stored in the dataset in the simulation shown in Figure 9.16. The variable Pavs becomes a two-dimensional variable because the parameter-swept simulation was carried out for two independent variables. Thus, the constant value from the two-dimensional variable Pavs is obtained by specifying Pavs as Pavs[0,0]. In addition, because Pavs is specified in dBm, the unit is changed to W by the equation in the second line. The third line calculates the PAE and the last line calculates the delivered output power in dBm. Once PAE and Pdel_dbm are calculated, they can be used to plot the contours.

PAE_step=2

NumPAE_lines=5

PAEmax=max(max(PAE))

PAE_contours=contour(PAE,PAEmax-0.1-[0::(NumPAE_lines-1)]*PAE_step)

Measurement Expression 9.6 Equations for drawing the contour plot

It is common practice to plot the contours from the maximum point at equally spaced step changes in a descending order. To do this, we first need to obtain the maximum value. The method for doing this is identical to that for finding the maximum of the delivered power, so only the plot of PAE contours will be discussed. Since the max(∙) function used to obtain the maximum value gives the maximum for a single sweep variable, the maximum can be obtained by using the equation max(max(PAE)) shown in Measurement Expression 9.6. The NumPAE_lines in this expression represents the number of contour plots to be drawn. The interval is set by PAE_step. Since PAE in Measurement Expression 9.4 is calculated as a percentage, this corresponds to a step of 2%. The function contour(∙) in Measurement Expression 9.6 is a function that gives the coordinates (x, y) as the output. For the coordinates (x, y), x is the independent variable of the function contour(∙) and y is the value of the function contour(∙). In addition, x is the primary sweep variable, while y is a secondary sweep variable. In the case of the example in Figure 9.16, real_indexs11 is the independent variable of the PAE_contours defined in Measurement Expression 9.6. In the case of the load-pull simulation for the polar sweep in Figure 9.13, Mag_rho is the independent variable of PAE_contours. The y coordinate value is stored in PAE_contours. Thus, to explain Measurement Expression 9.6, for example, the (x, y) coordinates can be represented as (indep(PAE_contours), PAE_contours) and the corresponding value of the contour level is stored as a separate independent variable. The obtained PAE_contours should be converted to the complex numbers in the Smith chart using the equations shown in Measurement Expression 9.7. The first two equations in that expression are used to convert the uniformly sampled swept PAE_contours into the complex numbers in the Smith chart, while the last two equations are used to convert the polar swept PAE_contour into the complex numbers in the Smith chart.

PAE_contours=contour(PAE, PAEmax-0.1-[0::(NumPAE_lines-1)]*PAE_step)

PAE_contours_p=[indep(PAE_contours)+j*PAE_contours]

PAE_contours=contour(PAE, PAEmax-0.1-[0::(NumPAE_lines-1)]*PAE_step)

PAE_conts_forSmithCh=indep(PAE_contours)*exp(j*PAE_contours*pi/180)

Measurement Expression 9.7 Conversion of the contour plot values into complex numbers for plotting on the Smith chart

In the figure, when the amplifier is biased at V_GS = V_GS,A, V_DS = V_DD (operating point Q_A), considerable drain current I_q,A (quiescent drain current) flows in the amplifier even in the absence of RF input. A power amplifier that operates at this DC bias point is called a class-A power amplifier. When a sinusoidal input is applied to the class-A power amplifier, the output drain current i_DS(t) conducts for a whole cycle of the sinusoidal input, as shown in Figure 9.19. Therefore, the input signal is faithfully amplified without distortion and shows a satisfactory linearity. However, as explained in section 9.1, the class-A power amplifier will have a maximum efficiency of 50%. In addition, the drain current flows even in the absence of RF input, which results in DC power consumption. Note that in the absence of RF input, the active device’s DC power consumption is maximum, which requires a large heat sink for sufficient heat dissipation.

The power consumption in the absence of RF input can be improved by moving the active device’s DC bias point. Suppose that the FET is DC biased at V_DS = V_DD and V_GS is set at the FET’s pinch-off voltage V_GS = –V_p, as shown in Figure 9.18. The DC bias point is called a class-B operating point and the power amplifier operating at this point is called a class-B power amplifier. In the class-B case, the drain current is I_q,B = 0 and will not flow in the absence of RF input. Thus, unlike the class-A amplifier, there is no DC power consumption in the absence of RF input. As another form of bias, V_GS can be set smaller than the pinch-off voltage V_p of the FET. This DC bias point is called a class-C operating point and the power amplifier operating at the class-C DC bias point is called a class-C power amplifier. It should be noted that the drain current of the class-C power amplifier is also zero in the absence of RF input. On the other hand, the operating point is often mathematically interpreted as the DC bias for a negative drain current I_q,C in the absence of RF input, as shown in Figure 9.18. However, the real DC drain current is zero. The I_q,C is the projected value from the I_DS–V_GS characteristics curve. The drain current I_q,C at the class-C DC bias point indicates the required amplitude for the sinusoidal RF input applied to the gate to reach the pinch-off voltage. As such, the class-B and class-C power amplifiers have no DC power consumption in the absence of RF input, which is an advantage.

For a sinusoidal RF input applied to the class-B and C power amplifiers, the drain current i_DS(t) flows for a conduction time interval determined according to their DC bias points, while it is zero for the remaining time interval, as shown in Figure 9.20. The time interval in which the drain current flows is called the conduction angle; the conduction angle of class-B is 180° while that of class-C is less than 180°. In addition, for an improvement in linearity and an increase in gain, a small DC current is made to flow in the absence of RF input, in which case the conduction angle becomes higher than 180°, an operation called class-AB.

As shown in Figure 9.20, the drain current waveform shows the shape of a sinusoidal tip in the conduction angle; otherwise, the RF input waveform is cut off. Distortion can naturally be expected when the RF input signal is amplified through the drain current with the sinusoidal-tip shape. Suppose that a class-B or class-C power amplifier is employed in a communication system. The amplitude and phase of the waveform in Figure 9.20 vary according to the modulated input signal. Therefore, when the RF signal is amplified by the class-B or class-C power amplifier, as shown in Figure 9.20, a loss of information may result. However, if expanded in a Fourier series, the waveform of Figure 9.20 will result in harmonics of nf_o. The harmonic signals can be removed using a filter after the amplification with the sinusoidal-tip-shaped waveforms. Both the amplitude and phase of the filtered waveform at the fundamental frequency are obviously proportional to the modulated RF input because the amplitude and phase of the sinusoidal-tip-shaped waveform in Figure 9.20 is proportional to the input signal. Thus, when the I_DS–V_GS characteristic is linear, as shown in Figure 9.18, a relatively faithful amplified signal can be obtained. However, the transfer characteristic, such as I_DS–V_GS, has some nonlinearity and results in distortion. Notably, the distortion becomes more significant as the operation point moves into a deeper class-C.

Previous explanations assume that the output of the active device is considered to be a transconductance-type current source. The output resistance of the current source is ignored. In a case where the output resistance cannot be ignored, it can be included in the load network. Thus, the necessary assumption for a transconductance-type current source is that the amplitude of the input is not set sufficiently large to drive the active device into the saturation region.

In the case of the class-D and class-E power amplifiers that are introduced in this section, the active device does not operate on the basis of the transconductance-type current source. The active device in class-D and class-E operations is assumed to be a switch. That is, when the input signal is sufficiently large, the active device no longer acts as a transconductance-type current source but instead functions as a switch. The modeling of an active device as a switch becomes more appropriate when the active device is driven by a square wave. Using the square wave can significantly increase efficiency, an operation that will be explained in this section. The classification of a class-F amplifier is somewhat ambiguous. Most of these amplifiers are classified according to the load network’s characteristics.

The Q = ω_oCR of the parallel resonant circuit is assumed to be sufficiently large. Thus, the impedance of the parallel resonant circuit is 0 at all harmonics except at the fundamental frequency. Consequently, the voltage due to the harmonic currents is 0 and does not appear across the load resistor R. Only the sinusoidal voltage due to the fundamental current appears across R. The voltage across R is sinusoidal and the drain voltage v_D(t) is thus a sinusoidal voltage waveform raised by supply voltage V_DD due to the DC voltage across the DC block capacitor, as shown in Figure 9.21. Since the supply voltage V_DD is fixed, by selecting an appropriate load resistor R, the maximum peak voltage can reach V_DD. It must be noted that a negative voltage does not appear at the drain. When an RF input V_Gcos(ωt) is applied, as shown in Figure 9.22, the output waveform of the drain current can be written as

The I_q in Equation (9.4) becomes the DC quiescent current that flows in the absence of RF input. That is, I_q = 0 when the amplifier operates in class-B and in class-C when I_q < 0. In addition, I_RF is the amplitude of the fundamental drain current. Using Equation (9.4), the conduction angle θ can be determined as expressed in Equation (9.5).

Now, using θ, Equation (9.4) can be rewritten and expressed as Equation (9.6).

Thus, the maximum current is expressed in Equation (9.7).

Expanding i_D(t) in a Fourier series,

i_D(t) = I₀ + I₁ cosωt + I₂ cos 2ωt + ···

where the DC current component can be obtained as shown in Equation (9.8)

and the fundamental wave component I₁ and harmonic components I_n can be expressed as Equations (9.9a) and (9.9b),

where γ₀ and γ₁ are functions of the conduction angle. Thus, denoting the voltage at fundamental frequency as V₁, the drain efficiency can be computed as shown in Equation (9.10).

Here, ξ is defined as

and, since V₁ < V_DD, generally ξ ≤ 1. Therefore, by substituting ξ = 1 and θ = ½π into Equation (9.10), the maximum efficiency of a class-B amplifier, η_B,max is expressed in Equation (9.11).

From I_max in Equation (9.7), the value of the load giving maximum output power is given by Equation (9.12).

Then, the maximum output power is expressed in Equation (9.13).

The meaning of the optimum load in Equation (9.12) can be understood by using a load line at the device output plane, which represents the trajectory of the voltage v_D(t) and current i_D(t). Using v_D(t) and i_D(t) in Figure 9.22, the load line can be drawn as shown in Figure 9.23. In that figure, the optimum load value that gives maximum output power in a class-B amplifier in Equation (9.12) can be easily inferred from Figure 9.23. In addition, the load resistance of a class-A amplifier that gives maximum output power is double that of the class-B amplifier. Also, from the load line of the class-C amplifier, as the conduction angle decreases, the optimum load resistance that gives maximum output power can also be seen to decrease, as shown in Figure 9.23.

From Equation (9.10), the maximum efficiency is obtained when ξ = 1. The maximum efficiency due to variation in the conduction angle can be expressed as Equation (9.14).

In addition, normalizing the maximum output power P, which varies with respect to the conduction angle, by the maximum power of the class-A power amplifier P_A, gives Equation (9.15).

This is shown in Figure 9.24. As the conduction angle in that figure gets closer to 0, the efficiency gets closer to 100%. Also, as the conduction angle decreases, the output power decreases compared with that of the class-A power amplifier. Therefore, even though the efficiency is good, the maximum output power of the active device cannot be fully utilized. In addition, because the gain approaches 0, a significant increase in the input power is also required. Therefore, power amplifiers below class-B are not practically applicable even though they have increased efficiency.

In the previous explanation using Figure 9.22, a class-B power amplifier is described as using a half-wave current source. It is noteworthy that a sinusoidal voltage appears across the load even though the output current of the active device shows a distorted half-wave current waveform. In addition, the phase and amplitude of the sinusoidal voltage across the load are proportional to those of the sinusoidal input. This indicates that the input signal is linearly amplified. In general, however, a class-B amplifier shows the P_L–P_in characteristic shown in Figure 9.25. The P_L–P_in characteristic has an S-shape for input power that causes distortion to appear in the output. This is primarily because the I_DS–V_GS characteristic is not linear. As a result, the P_L–P_in characteristic has a distorted S-shape. This S-shaped P_L–P_in characteristic can, to some extent, be corrected to a straight line by operating the amplifier in class-AB. An accurate measure of the distortion can be achieved by measuring the distortion for a modulated input signal, which will be described later in this chapter.

An example of the class-D power amplifier circuit is shown in Figure 9.26, where inductor L operates as an RFC and allows only DC current. The DC current value is assumed to be I_o. Capacitor C_∞ acts as a DC block and allows only DC voltage, which is intuitively determined to be V_DD. Thus, when the active device is driven into the off state by the input signal, the voltage across the drain v_D is given by

v_D = V_DD + I_LR_L

In addition, when the active device is on, v_D is 0 and

v_D = 0 = V_DD + I_LR_L

Thus, the drain voltage alternates from 0 to V_DD + I_LR_L according to the active device’s state, which changes from on to off. In contrast, when the active device is on, I_L the current flowing through load R_L is obtained as

and the drain current becomes

i_D = I_o – I_L

Note that when the device is off, the drain current is 0, and when the device is on, the drain current has a value of I_o – I_L. Since the DC component must be I_o, I_o – I_L = 2I_o, then

The resulting voltage and current waveforms are shown in Figure 9.27.

With the class-D operation, the active device’s output switches on/off according to the phase of the input signal. However, even though the phase information of the input signal is preserved at the amplifier output, the amplifier shows some losses to the amplitude information. The technique for solving this problem is that the amplitude and phase of the input voltage are separated using signal processing, and a square wave that varies according to the phase of the input signal is used as the driving input for the amplifier. The amplitude information can be restored by varying the supply voltage V_DD in Figure 9.26 according to the amplitude of the input signal. Since the amplitude of the output signal of the class-D amplifier is related only to the supply voltage, the amplitude and phase information of the input signal can be restored at the amplifier output without any loss.

Even after solving the problem of the loss of the amplitude information, a significant amount of harmonics appears at the output, which presents another problem. A separate filter is required to remove the harmonics. There are several efficient ways of dealing with the harmonic problem of the class-D power amplifier. The voltage and current switching technique shown in Figure 9.28 is one of the ways to deal with the harmonic problem; see reference 3 at the end of this chapter for more information.

In general, the efficiency of a practical class-D power amplifier seldom reaches 100%. One reason for the degraded efficiency is that the output voltage and current of the active device have finite rising and falling times, and a non-zero voltage appears when the device is conducting. Similarly, a non-zero current appears when the device is off. In addition, the charge on the drain capacitor, which is charged to maximum during the device’s off state, flows instantly to the drain when the device enters the on state. This sometimes causes permanent damage to the device and loss in the efficiency.

4. N. O. Sokal and A. D. Sokal, “Class E-A New Class of High-Efficiency Tuned Single-Ended Switching Power Amplifiers,” IEEE Journal of Solid-State Circuits 10, no. 3 (June 1975): 168–176.

The configuration of the class-E input circuit shown in Figure 9.29 is the same as that for a class-D amplifier and the active device operates as a switch, which periodically turns on and off. Because of this, a transient analysis that depends on the on/off states is necessary to explain the class-E amplifier. Collector capacitance may exist in the collector terminal. In this case, the collector capacitance can be included in the capacitor C. DC current is supplied to the collector through the RFC, which is denoted as I_o. The series resonator L_o–C_o eliminates harmonics and is set to series resonate at the fundamental frequency. The Q of the series resonant branch is assumed to be sufficiently high, and harmonic currents other than those at the fundamental frequency cannot flow. Inductor L is added in series to the resonator; when the inductor is included, it makes the series resonant circuit resonate at a frequency lower than the fundamental (usually the resonator is said to be detuned). The class-E power amplifier generally has an optimized efficiency for the detuned series resonator, and it is analyzed by placing a separate L in series with the series resonator resonating at the fundamental frequency. It must be noted that the contribution of the inductor L appears only at the fundamental frequency and has no effects on the harmonics.

The output circuit of Figure 9.29 can be analyzed by considering the active device’s output as a switch. When the switch is opened, because a current I_o + i_R flows through capacitor C, the capacitor voltage rises and thus the collector voltage increases. On the other hand, when the switch is closed, the accumulated charge in the capacitor instantaneously flows through the switch in the form of an impulse current. In this case, even if there is a small voltage on the switch, power loss in the switch increases. This condition is not desirable for optimized efficiency. If the switch is open for the interval of 0.5T ≤ t ≤ T, the following must be satisfied at t = T for optimum efficiency, as expressed in Equation (9.16):

In addition to the impulse current due to the capacitor, a current I_o + i_R flows into the collector when the switch is closed. Although this is not an impulse-type current as in the case of the capacitor, it can cause a current with a step discontinuity. As this current flows instantaneously into the collector, it also leads to a loss of efficiency. In order to make this loss 0, Equation (9.17) must be satisfied.

The conditions of this equation mean that the capacitor current i_C = I_o + i_R should be zero just before the switch is turned on. Thus, at the instant when the switch is closed, the current does not flow and the discontinuity of the current does not appear. These two conditions become the optimum conditions of the class-E power amplifier.

As a first step, the values of L and C that satisfy the optimum conditions for a given load R and supply voltage V_CC should be determined through analysis. Then, the power delivered to the load P_L and the DC current I_o can be computed. Other parameters that must be determined include the maximum value of v(t), V_max, and the maximum value of i(t), I_max. Using the determined V_max and I_max, the active device appropriate for this class-E power amplifier can be selected.

Equivalent circuits based on the switch states are shown in Figure 9.30. In Figure 9.30(a), because the series resonator is assumed to have a high Q, the current through load R can be represented by i_R(t) = I_R sin(ωt + φ). Therefore i(t) can be expressed as

Since i(0) = 0, Equation (9.18) can be rewritten as

The current given by Equation (9.19) for the closed switch flows into the capacitor when the switch is open. Therefore, the voltage across the capacitor is obtained as shown in Equation (9.20).

Applying v_C(T) = 0,

Using tan(φ) given in Equation (9.21), sinφ and cosφ can be obtained as expressed in Equation (9.22).

Then, substituting sinφ and cosφ into Equation (9.20) and rewriting, we obtain Equation (9.23).

Since the average voltage of v(t) should be V_CC, the following relationship is obtained with Equation (9.24):

Therefore, normalizing v(t) by V_CC, we get Equation (9.25).

In addition, normalizing i(t) by I_o and rewriting Equation (9.18), we obtain Equation (9.26).

The normalized waveforms of v_n(t) and i_n(t) are shown in Figure 9.31.

By differentiating Equation (9.25), the maximum voltage is obtained and expressed in Equation (9.27).

Also, by using the relationships shown in Equations (9.19b) and (9.22) where the efficiency is 100%, the power delivered to the load and DC current I_o is obtained as expressed in Equations (9.28) and (9.29).

The maximum current I_max is obtained by differentiating Equation (9.26) and rewriting as Equation (9.30).

Also, applying Equations (9.19b) and (9.22) to Equation (9.28), we obtain Equation (9.31).

However, the values of L and C are still not determined. From the voltage in Equation (9.25), the fundamental component of the voltage is the sum of the voltage drops across the resistor R and inductor L, V_R, and V_L. Therefore V_R and V_L can be determined as

The ratio of these results is expressed in Equation (9.32).

In addition, by using Equations (9.24) and (9.29) we obtain Equation (9.33).

A class-E amplifier can be designed using the equations obtained above. Table 9.3 summarizes the formulas required for the design.

The first characteristic feature of the load circuit of the class-E amplifier is that the load circuit does not resonate at the fundamental frequency as previously explained. However, due to the series resonator in the load circuit, only sinusoidal output appears at the load. The second feature is that the current flows only when the voltage is zero, while the voltage appears only when the current is zero due to the switch operation of the active device. An amplifier with these features is a class-E amplifier and therefore the class-E amplifier is very diverse. The load circuit of the class-E amplifier explained earlier is simple and easy to implement. However, for other types of class-E load circuits that differ from that in the example, the collector voltage and current waveforms should be computed for a new optimum load circuit. The computation of the optimum load circuit becomes more complex when components such as transmission lines are used. In this case, the class-E load circuit can be approximately designed by setting the impedance of the load network at each harmonic frequency to have the same impedance as that of the class-E amplifier in Figure 9.29. For more details, refer to reference 3 at the end of this chapter.

Another feature of the class-E amplifier is that the ratio between the average and the peak values of the collector voltage or current waveform, as shown in the amplifier example, is greater than 2. Therefore, the active device used for a class-E amplifier should have a very high breakdown voltage and a maximum current. That is the disadvantage of the class-E amplifier: the active device’s maximum output capacity is not efficiently exploited.

In addition, in the calculations for the class-E amplifier, the active device was assumed to be a switch. Thus, in order to operate the active device as a switch for a class-E operation, either a driving circuit must be inserted or sufficiently high power must be applied to the input. When the input is not sufficiently high, the active device begins to operate as a half-wave current source similar to a class-B operation. Since the class-E operation is achieved when the device operates as a switch, the class-E operation is not optimum for the transconductance-type current source operation in class-B. Thus, the amplifier designed for a class-E operation does not show an optimum class-B operation. When the input drive is not appropriate, the class-E amplifier will show degradation in terms of efficiency compared to the class-B operation previously described.

Inserting an infinite number of odd harmonic parallel resonators in series, the collector voltage waveform becomes closer to a square wave and the efficiency becomes 100%. Instead of these multiple-harmonic resonators, Tyler presented a class-F power amplifier that uses a quarter-wavelength transmission line at the fundamental frequency, as shown in Figure 9.33. All of the amplifier’s harmonics in that figure can be ideally controlled and the class-F operation is achieved. The input drive circuit in Figure 9.33 acts as it does in a class-B power amplifier. The capacitor C_B in the load side is a DC block capacitor. Inductor L₁ and capacitor C₁ form a parallel resonant circuit that resonates at the fundamental frequency. Thus, assuming a high Q, only the fundamental voltage appears across the load. The transmission line is one-quarter-wavelength long and the impedance seen from the collector toward the load at the fundamental frequency is (Z_o)²/R. At even-order harmonics, since the transmission line becomes an integer multiple of a half wavelength, the impedance seen from the collector toward the load appears similar to that of a short circuit, while at odd-order harmonics, it appears similar to an open circuit due to the characteristic of the one-quarter-wavelength transmission line. Therefore, the one-quarter-wavelength transmission line provides a short-circuit impedance at the collector for even-order harmonics, and it provides an open-circuit impedance at odd-order harmonics. Thus, when the circuit in Figure 9.33 is compared to that shown in Figure 9.32, it acts as the infinite number of parallel resonators inserted in series to resonate at odd-order harmonics.

Since the impedance is an open circuit at odd harmonics, voltages of odd harmonic components can appear at the collector; however, because the impedance is a short circuit for even harmonics, voltages of even-order harmonic components cannot appear at the collector. In contrast, the opposite is the case for the current. Thus, setting θ = ωt and expressing the collector voltage and current waveforms in a Fourier series can be represented by Equations (9.34a) and (9.34b).

Figure 9.34 shows the expected collector voltage and current waveforms because, as mentioned earlier, the collector voltage waveform of a class-B power amplifier around the minimum and maximum is expected to be flattened due to the parallel resonators.

In order to design a class-F power amplifier, it is necessary to take into account the impedance of the load circuit at each harmonic. This can be determined by dividing the harmonic voltage by the corresponding harmonic current shown in Equation (9.34). Then, the load circuit of the ideal class-F power amplifier should be designed to provide the computed load impedances. The load impedance must be designed to have the optimum resistance R_opt at the fundamental frequency. For harmonics, the impedance value must be 0 at even harmonic frequencies and ∞ at odd harmonic frequencies.

An ideal class-F load circuit can be constructed using a transmission line and a parallel resonator that resonates at the fundamental frequency shown in Figure 9.33. However, because the impedance of the transmission line used to implement the class-F load circuit is generally too low, problems can arise when implementing an ideal class-F load circuit. Thus, instead of the load circuit in Figure 9.33, the class-F load circuit is generally made to satisfy the class-F load impedance condition for a limited number of harmonics, as it is generally difficult to satisfy the class-F load conditions for all harmonics. In the case of the harmonic-limited class-F load circuit, the collector voltage and current waveforms given by Equation (9.34) are reduced to those with limited harmonics. Raab has summarized the limited-harmonics waveforms and their efficiencies.^{5, 6} This is not a simple truncation of the Fourier series in Equation (9.34) that retains only a limited number of harmonics. The simple truncation of the Fourier series results in the well-known Gibbs phenomenon and the resulting waveform with the Gibbs phenomenon is not acceptable for the output waveform of a power amplifier. Thus, the waveform with a limited number of harmonics will differ from that obtained by truncating higher-order harmonics using Equation (9.34). Raab proposed two waveforms: maximally flat waveforms and maximum efficiency waveforms. In this section, we will review the maximum efficiency waveforms. To obtain these waveforms, the drain voltage and current are assumed not to take on negative values. To demonstrate this process, a voltage waveform example up to the third-order harmonic can be written as shown in Equation (9.35).

5. F. H. Raab, “Maximum Efficiency and Output of Class-F Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques 49, no. 6 (June 2001): 1162–1166.

6. F. H. Raab, “Class-F Power Amplifiers with Maximally Flat Waveforms,” IEEE Transactions on Microwave Theory and Techniques 45, no. 11 (November 1997): 2007–2012.

Here, the amplitude of the fundamental component has been normalized to 1. The minimum and maximum values can be obtained by taking the derivative of the equation above.

Solving Equation (9.36), we obtain Equation (9.37).

Substituting θ_m into Equation (9.35), the value of v(θ) at the minimum is obtained. The value should be v(θ) ≥ 0. Thus v(θ_m) = 0 for the maximum swing, and it results in

V_CC in Equation (9.38) becomes a function of b. When the value of b is adjusted to obtain the minimum value,

From Equation (9.39), the minimum amplitude of the third harmonic is obtained. When the determined b is substituted into Equation (9.37), θ_m can be determined. The value of V_CC then can be obtained by substituting b and θ_m again into Equation (9.38). Finally, the normalized amplitudes of the fundamental and third harmonic by the value of V_CC can be obtained. This process can be extended to higher-order harmonics. In the case of the current waveform, using the similar calculation, the maximum efficiency waveform can be calculated from Equation (9.34) for up to the harmonic order of m–th. The results are summarized in Tables 9.4 and 9.5 where n represents the harmonic number of the voltage, while m represents the harmonic number of the current. The maximum values of voltage and current waveforms v_max and i_max in Tables 9.4 and 9.5 are normalized values using the values of the DC components, and defined as shown in Equations (9.40a) and (9.40b).

In addition, the values of V₁ and I₁ at the fundamental frequency are also normalized using the DC values as expressed in Equations (9.41a) and (9.41b).

Figure 9.35 shows the voltage and current waveforms plotted using the results of Tables 9.4 and 9.5. In Figure 9.35, as the number of harmonics increases, the waveform is found to approach that of the ideal class-F power amplifier. In addition, slight ripples are observed to occur around the maximum and minimum values of the voltage in Figure 9.35. However, the ripples do not occur in the maximally flat waveforms.

Using the values obtained in Tables 9.4 and 9.5, the efficiency, optimum impedance, and output power capability can be calculated. First, the optimum impedance R_opt at the fundamental frequency is computed as shown in Equation (9.42).

Then, the optimum impedance of the ideal class-F amplifier R_opt at the fundamental frequency can be expressed as Equation (9.43).

With the optimum impedance R_opt, the output power delivered to the load is shown in Equation (9.44).

In addition, since the DC power consumption is represented by Equation (9.45),

the drain efficiency is computed as Equation (9.46).

This computation is summarized in Table 9.6.

Finally, the power capability of the active device can be assessed using v_maxi_max. The output power of the class-F amplifier given in Equation (9.44) cannot fully utilize v_maxi_max, which leads to the definition of the output power capability M_p as

The output power capability given by Equation (9.47) can generally be applied to various types of power amplifiers and can be used as the criteria for assessing the effectiveness of their operations in exploiting an active device’s given output power capability. The M_p of the class-E amplifier is generally low compared to that of the class-F amplifier.

In Example 9.7, the ideal class-F waveforms were explained by modeling the output of the active device as a switch. However, the switch model of the active device cannot explain the class-F waveforms of limited harmonics shown in Figure 9.35. The non-zero voltage appears at the time when the switch is on, and the non-zero current appears at the time when the switch is off. Thus, a reasonable model for the active device will be the transconductance-type current source model employed in the explanation of the class-B operation. The increased peak value of the sinusoidal-tip-shaped current will drive the active device output into saturation, and the clipped collector voltage appears as a result. Due to clipping, the class-F waveforms of limited harmonics can appear according to the class-F load circuit.

7. H-C Jeong, H-S Oh, and K-W Yeom, “A Miniaturized WiMAX Band 4-W Class-F GaN HEMT Power Amplifier Module,” IEEE Transactions on Microwave Theory and Techniques 59, no. 12 (December 2012): 3184–3194.

8. TriQuint semiconductor, TGF2023-01 6 Watt Discrete Power GaN on SiC HEMT, November 2009; available at www.triquint.com/products/p/TGF2023-2-01.

The characteristics of TGF2023-01 are shown in Table 9.7. Since the saturated output power is 38 dBm at a drain voltage of 28 V with a quiescent drain current of 125 mA, the device is considered to be adequate for the design goal of the 4 W above.

TriQuint provides the large-signal model of the TGF2023-01, which is shown in Figure 9.37. The S-parameter data components at the gate, source, and drain terminals in the large-signal equivalent circuit are those from the EM-simulated data of the source via, drain, and gate pads supplied by TriQuint. The large-signal equivalent circuit shown in Figure 9.37 is configured using the EEHEMT model whose required values are provided in the ADS discrete file format from TriQuint since the values to be entered are so many. The discrete file format consists of variable names and their corresponding values. The variable names of the discrete format file are meant to be the same as those in the EEHEMT model. The DAC (data access component) named eehemt_dac and shown in Figure 9.37 is used to read the discrete file format. Then, the variable values of eehemt_dac are read into the variable block named eehemt_vars using the expression Vto=file{eehemt_dac, “Vto”}. Now the variable values in eehemt_dac are represented by the schematic window variables that have the same name as those in the discrete format file. Only one equation of Vto is shown in eehemt_vars and other variables are hidden to avoid congestion. Then, the variables defined by eehemt_vars are again used as the input for the EEHEMT model named EEHEMTM, in which all the variables are similarly hidden except one, Vto. The extrinsic inductors and resistors appearing at the gate, drain, and source are appropriately scaled using the number of fingers and gate width. The component Scaling_Factor specifies the scaling. Table 9.8 lists the values of the EEHEMT model parameters.

9. TriQuint Semiconductor, TriQuint EEHEMT Model Implemented in ADS and AWR for TQT 0.25 μm 3MI GaN on SiC Process 1.25 mm Discrete FET: 30 V @ 100 mA/mm @ 10 GHz, December 2009.

The gate voltage is thus determined as –3.57 V, and a drain voltage of 28 V is applied. A problem arises because the circuit is first configured to be stable before the load-pull simulation. The stability investigation requires S-parameter simulation. But before the S-parameter simulation, the S-parameters of an appropriate bonding ribbon for the connection of the active device’s gate and drain should be predetermined because they appear as fixed components in assembly. After the 3D-simulation of the bonding ribbons with a 3-mil width using AnSoft HFSS, the bonding ribbon S-parameters are determined. They appear as the S-parameter data components in Figure 9.39. The RC circuit connected in shunt to the gate is to ensure the stabilization of the active device. By adjusting the resistance value r, the stability factor can be adjusted to be greater than 1 in the full frequency band. For the value r = 55 Ω, the circuit is stabilized for a full frequency band of up to 10 GHz. Figure 9.40 shows the simulated stability and maximum gain. Since the stability factor is larger than 1 up to a frequency of 10 GHz, the device is found to be stable and the maximum gain at the center frequency of 2.5 GHz is approximately 21 dB.

After the stability circuit is thus configured, the load-pull simulation shown in Figure 9.41 is set up and the simulation is carried out to obtain the source and load impedances giving maximum output power. Here, the sweep center of the load reflection coefficient is set using the maximum output power impedance of the TGF2023-01 in the datasheet as s11_center = polar (0.32, 130°). The optimum source impedance is set to the conjugate of S₁₁ of the small-signal S-parameters at 2.5 GHz in the datasheet. The optimum source impedance is implemented in the variable block named Initial_S11 in Figure 9.41. The circuit is thus set up and the initial load-pull simulation is carried out. Next, using the resulting initial load impedance values, the source-pull simulation is performed. This process is repeated three to four times to obtain the final results. The source impedance value that is eventually obtained is shown as z1 in the variable block named VAR4 of Figure 9.41. It must be noted that the impedance of the load in VAR2 of Figure 9.41 is set to operate in class-F up to the third harmonic. The second harmonic impedance was set to 0 and that of the third harmonic to 1 kΩ, while the rest of the harmonic impedances were set to 50 Ω. On the other hand, all the harmonic impedances of the source were set to 50 Ω. The reason for setting the source impedance is that matching at the input is performed only at the center frequency. In addition, the number of harmonics in the HB simulator is set to 3.

The simulated load-pull contour plot is as shown in Figure 9.42. The maximum output power in that figure shows an output power of 37 dBm. The load reflection coefficient is 0.220∠55°, which can be seen to differ from the maximum output power reflection coefficient 0.320∠130° provided by TriQuint in the datasheet. The PAE can be seen to be approximately 60%. The difference in the maximum output power reflection coefficient is considered to be due to the addition of the stabilization circuit.

Figure 9.43 shows the source-pull simulation; see reference 1 at the end of this chapter for more information. This simulation is similar to the load-pull simulation. The load impedance value of 59.587 + j22.702 determined from the load-pull simulation is used as the load impedance, which is assigned up to the third harmonic for a class-F operation. The variable block named Impedance Equations is used to assign the sweep variable indexs11 to the source impedance. The sweep method of indexs11 is the same as the load-pull simulation, which uniformly samples the region of the circle. In addition, to supply the specified available power Pavs, the one-tone source V_1Tone is used. The value of the V_1Tone source is set using the dbmtov(·) function. Note that the impedance of the V_1Tone source is set using the impedance at the fundamental frequency Z_s_fund. The source-pull simulation results are as shown in Figure 9.44. Only the contours for the delivered power are plotted. The optimum source reflection coefficient providing the maximum delivered power can be seen to be 0.660∠132°.

In summary, the simulated optimum source and load impedances are listed in Table 9.9. The output power is 37 dBm and the PAE is about 60% for the source and load impedances in Table 9.9.

The simulation circuit shown in Figure 9.45 is set up to verify the obtained source and load impedances in Table 9.9. The source and load impedances at the fundamental frequency are declared using the variable block named VAR4 and are used to set the input and output impedance tuners. After the simulation, the equations in Measurement Expression 9.8 are entered in the display window to calculate the output power and the PAE. In addition, the equation for calculating the power gain is also entered.

Pdc=28*real(Id.i[0])

Pout_dbm=10*log10(0.5*real(vload[1]*conj(iload.i[1])))+30

Prf=10**(Pout_dbm/10-3)-10**(Pavs/10-3)

PAE=Prf/Pdc*100

gain=Pout_dbm-Pavs

Measurement Expression 9.8 Equation for calculating the output power, gain, and PAE

Figure 9.46 shows the calculated output power, gain, and PAE. As expected, the output power is 37 dBm at an input power of 20 dBm, and the PAE is about 62% at an output power of 37 dBm. In addition, the power gain can be seen to be approximately 20 dB.

In this section, a simple implementation of the class-F output matching circuit for up to the third harmonic using lumped components will be discussed. Figure 9.47(a) shows the class-F output matching circuit that can yield the determined load impedance from the load-pull simulation. The capacitor C_p represents the drain capacitance, which is computed from the series-to-parallel conversion of the load impedance in Table 9.9. The value is fixed as C_p = 0.35 pF. In addition, G_D and G_L represent the drain conductance and load conductance, respectively.

Basically, the output matching circuit is a kind of low-pass filter that provides a short for the second harmonic frequency and an open for the third harmonic frequency. Series-connected branches L₂–C₂ and L₃–C₃ are established to be series resonant and become short at the second and third harmonic frequencies, respectively. Therefore, the circuit in Figure 9.47(a) provides a short at the second harmonic due to L₂–C₂, independent of the rest of the load circuit. In order for the amplifier to operate in a class-F, the impedance seen from the drain should be open at the third harmonic. Since the impedance of L₃–C₃ is 0 at the third harmonic, the circuit seen from the drain with the branch L₃–C₃ shorted should be a parallel resonant circuit. Consequently, the impedance seen from the drain terminal can be made open at the third harmonic. Thus, the circuit can be set to operate in class-F up to the third harmonic.

In addition, the circuit should have the desired load impedance at the fundamental frequency. The circuit in Figure 9.47(a) becomes a π-type matching circuit at the fundamental frequency and the equivalent circuit of Figure 9.47(a) at the fundamental frequency is shown in Figure 9.47(b). Here, the drain-side admittance at the fundamental frequency is denoted as B₂, the 50-Ω load-side admittance is denoted as B₃, and the series admittance is denoted as B₁. Also, the ratios of the drain and load admittances to the π-matching admittance denoted as n₁ and n₂ are respectively defined as expressed in Equation (9.48).

Note that G_π > G_D, G_L. Given G_π, the values of B₁, B₂, and B₃ can be calculated at the fundamental frequency ω₁ following the method explained in Chapter 6 that can be expressed with Equations (9.49a)–(9.49c).

The value of B₁ in Equation (9.49a) is selected to be negative because B₁ is the admittance of inductor L₁. From the calculated value of B₁, the value of L₁ can be computed as shown in Equation (9.50).

The admittance of the branch L₃–C₃ at the fundamental frequency is B₃, which is short at the third harmonic frequency, ω₃. Using the relationship (ω₃)² = (L₃C₃)^-1,

Thus, from B₃, the value of capacitor C₃ can be determined using Equation (9.51) and inductor L₃ can be subsequently determined using (ω₃)² = (L₃C₃)^-1. In addition, the drain-side branch admittance at the fundamental frequency is B₂, and we obtain Equation (9.52).

At the same time, the admittance seen from the drain at the third harmonic frequencies is 0 and this can be expressed as

As a result, Equations (9.52) and (9.53) become simultaneous equations for C₂ and L_B. Thus, by solving the simultaneous equations, C₂ and L_B can be determined as shown in Equations (9.54) and (9.55).

Thus, the values of all the elements in Figure 9.47(a) can be determined to satisfy the class-F operation up to the three harmonics.

The values of all the elements were calculated by setting G_π = 2G_D and using Equations (9.50)–(9.55). The calculated results give a value of L_B too large to implement. Therefore, the value of C_p was increased by 0.5 pF and the values of all the elements were recalculated. Here, the increased value 0.5 pF can be implemented using a parasitic capacitor that appears together with L_B. The calculated results are shown in Table 9.10.

In order to verify the results above, the simulation circuit shown in Figure 9.48 is set up and the simulation is carried out. The transmission characteristic of the designed class-F load circuit is shown in Figure 9.49(a). As expected, the transmission characteristic shows a match at the fundamental frequency with the transmission zeroes at the second and third harmonics. In addition, in order to plot the impedance seen from the drain, S₁₁, from the S-parameters renormalized by the reference, 50 Ω is plotted as shown in Figure 9.49(b). From that figure, the impedance provides an exact match at the fundamental frequency and provides a short and an open at the second and third harmonics, respectively.

The input matching circuit is designed to produce the source impedance value of 12.2 + j21.3 Ω in Table 9.9. The input matching circuit can be implemented using the L-type matching circuit described in Chapter 6. Figure 9.50 is a simulation schematic for computing the element values of the L-type matching circuit through the optimization. The L-type matching circuit is a low-pass filter type. After the optimization, C_i = 2.2445 pF and L_i = 2.722 nH are obtained.

The entire amplifier circuit is shown in Figure 9.51. Here, the input and output matching circuits are configured as subcircuits. It should be noted that since the active device includes the drain capacitor C_p in the output matching circuit of Figure 9.48, that drain capacitor must be deactivated when the output matching circuit is configured into the output matching subcircuit. The input matching subcircuit represents the L-type matching circuit in Figure 9.50. The gate DC voltage is supplied through a 1-kΩ resistor. The input and output DC block capacitors in Figure 9.51 are set to 22 pF.

The simulated output power and the PAE are shown in Figure 9.52. As in the previous simulation, the output power is 37 dBm, the PAE is about 60%, and the gain can be seen to be about 20 dB. Thus, the designed matching circuits can be seen to reproduce the characteristics obtained from the load-pull simulation results.

Figure 9.53 shows a simulation schematic for determining the initial dimension of the spiral inductor. Using the simulation, the value of inductance can be calculated by varying the inner diameter. The determined diameters are summarized in Table 9.11. In the case of inductors L₂ and L₃, their values were found to be too small and so were implemented using microstrip lines.

The initial dimension of the interdigital capacitor can also be configured in a similar way. The line width, spacing, length, and number of fingers of the interdigital capacitor can be adjusted; among them, only the length is varied with other parameters fixed. The continuous increase of capacitance values can be obtained by changing the length. The line width, spacing, and number of fingers are fixed at 20 μm, 10 μm, and 10, respectively, while the length is adjusted. Figure 9.54 is the simulation schematic for calculating the capacitance.

The calculated dimensions are shown in Table 9.12. The value of C_i in the input matching circuit was found to be too large to be implemented as an interdigital capacitor, and so was implemented using a single layer capacitor (SLC). In addition, because the values of the DC block and bypass capacitors are also large, SLCs are used. To connect the SLC to the substrate, bonding wires are needed. The S-parameters of the bonding wire are required during simulation and have been precomputed using Ansoft’s HFSS.

Using the initial dimensions of the inductors and capacitors, an initial layout of the power amplifier can be drawn and is shown in Figure 9.55. The patterns marked 1–1’, 2–2’, 3–3’, 4–4’ in the figure are inserted for on-wafer probing of the substrate. Using the on-wafer probing patterns, the substrate can be inspected using S-parameter measurements before the assembly of the power amplifier.

The initial power amplifier layout shown in Figure 9.55 should be tuned using EM simulation to obtain the desired input and output impedances. Figure 9.56 shows the schematic of the co-simulation with EM simulation for the output matching circuit. The substrate in the EM simulation, as previously described, is a 5-mil-thick alumina of dielectric constant 9.9 and the conductor thickness is set to 10 μm while the conductivity is set to 4.1 × 10⁷ siemens/m. As mentioned earlier, the inductance of the bonding wire needed for connecting the DC block SLC was determined using Ansoft HFSS simulation, and the value is about 0.2 nH. The 0.2 nH inductors in Figure 9.56 represent the bonding-wire inductances. The effects of landing patterns for SLC capacitors should also be considered; in Figure 9.56, they are represented as data items that were obtained through a separate S-parameter simulation.

If co-simulation is not involved, the layout must be redrawn each time to reflect the changes in the layout dimensions, which is inconvenient. To work around the co-simulation, dimensions such as the inner diameter of the spiral inductors and length of the interdigital capacitors are first declared as variables in the layout. Then, those declared variables can be used as variables in the circuit simulation window. The impedance can thus be obtained from the schematic co-simulation without the necessity of separate EM simulations for the layout with the given dimensions. Using the co-simulation, the layout tuning can be carried out repeatedly until the dimensions are close to the goal.

As mentioned previously, only the inner diameter of the spiral inductor and the length of the interdigital capacitors are selected as the adjustable dimensions. Certain dimensions should be fixed even when the selected dimensions are adjusted. For example, the distance between the drain and the 50-Ω load should be fixed and should not be changed by the adjustments of the inner diameter of the spiral inductor. Also, the location of the DC supplying pad in the substrate should be fixed irrespective of the adjustments. Thus, the length of the transmission line used for connection must also be specified as a variable to prevent changes to the previously fixed dimensions in the layout. In addition, the drain capacitor is increased by 0.5 pF in the output matching circuit. The increased capacitor is implemented by the parasitic elements arising from the spiral inductor for L_B and L₁, and from the interdigital capacitors C₂. Thus, a separate capacitor for the implementation of 0.5 pF is not used. The value of the parasitic capacitor is approximately 0.2–0.6 pF, which is somewhat dependent on the patterns of L_B, L₁, and C₂. The output matching circuit, including the parasitic capacitor, is thus optimized in the course of the co-simulation.

The desired matching can be achieved through optimization. However, because the optimization requires significant computation time, the matching is obtained by trial-and-error adjustment in the co-simulation. The transmission characteristics shown in Figure 9.49(a) help in the adjustment technique. The second harmonic-transmission zero depends on capacitor C₂ and the third harmonic-transmission zero depends on C₃. Thus, the desired transmission zeroes at the second and third harmonics can be achieved by adjusting C₂ and C₃. The matching at the fundamental frequency can be achieved by tuning inductor L₁. Thus, by adjusting capacitors C₂, C₃, and inductor L₁, the desired output matching circuit can be achieved.

Figure 9.57 shows the EM simulation results after completing the final adjustments for the output matching circuit. As the impedance is not the 50-Ω reference impedance, the S-parameters are first converted into the 50-Ω reference S-parameters and plotted in Figure 9.57(b). In that figure, the EM-simulated impedance is found to be well-matched to the desired impedance at the fundamental frequency. In addition, the short and open impedances at the second and third harmonics, respectively, were approximately achieved. However, significant losses appear at the second and third harmonics compared to the loss results in Figure 9.49(b). Despite these losses, looking at the transmission characteristics of Figure 9.57(a), there appear to be no problems eliminating the second and third harmonics. The insertion loss at the fundamental frequency can be seen to be about 0.6 dB.

The EM co-simulation schematic of the input matching circuit is shown in Figure 9.58. The input matching can be achieved by adjusting the value of the SLC C_i and the diameter of the spiral inductor L_i. Here, the inner diameter of the spiral inductor is related to the connection of the device and input port. Thus, the length of the connected transmission line is set to compensate for the change in the inner diameter of the spiral inductor so that an assembly problem does not arise in the connection. In addition, the bonding wire of the DC block SLC at the input that cannot be simultaneously simulated in ADS Momentum is pre-simulated using Ansoft’s HFSS. This is represented by a 0.2-nH inductance, which is a fitted value that uses the HFSS simulation results. Similarly, the input-pad pattern is pre-simulated and represented by a data item for the co-simulation.

It should be noted that because the value of the capacitor C_i is not continuous, it is adjusted using fixed discrete values available from the datasheet. The calculated value is 1.9 pF. The element values of the input matching circuit can be obtained using the properties of the L-type matching circuit, as explained in Chapter 6. The value of L_i is adjusted when the real part of the impedance seen from port 1 differs from 50 Ω. If the imaginary part is not matched, it is matched by adjusting the value of C_i.

The simulated impedance of the input matching circuit at port 1 is shown in Figure 9.59. In Figure 9.59(a), it can be seen that the input part is closely matched to 50 Ω at 2.5 GHz. However, looking at Figure 9.59(b), the matching circuit shows a loss of approximately 1 dB. This is considered to be caused by losses in the input matching circuit. It must be noted that although this loss is high, it does not reduce the output power. Therefore, in order to obtain the same output power, an input power greater by 1 dB must be applied to the input.

Finally, using the EM-simulated results thus obtained, the P_out–P_in characteristics of the power amplifier can be examined. The simulation schematic configured by replacing the EM simulation results by S-parameter data items is shown in Figure 9.60.

The output power, gain, and PAE are shown in Figure 9.61. Due to the losses at the input, the results at an input power of 21 dBm will correspond to the lossless circuit simulation results at an input power of 20 dBm. At 21-dBm input power, the output power is decreased by approximately 0.6 dB compared to the circuit simulation results due to the approximately 0.6-dB loss occurring in the output matching circuit. In addition, due to the same losses, the PAE is 53% and can be seen to have also decreased by about 7%.

The small-signal gain characteristics obtained from the EM simulation are shown in Figure 9.62. The gain in that figure is approximately 20 dB and the return losses for both input and output can be seen to be approximately 10 dB. The reason for the poor return losses is that the power amplifier is matched at large signals. This causes a mismatch at the small-signal level and results in poor return losses.

The transmission characteristics for the small signal are shown in Figure 9.63. As expected, the transmission zeroes can be seen to occur at the second and third harmonics. Another transmission zero exists between the two transmission zeroes as can be seen in Figure 9.63. This is the transmission zero caused by the input matching circuit, which was shown in Figure 9.59(a).

Basically, the evaluation of a power amplifier for a digital modulation signal is, to some extent, related to the previously described two-tone test; however, the two-tone test results provide indirect evaluation for the power amplifier and a new, direct assessment method is required. This has led to the development of new test methods for assessing the degree of signal distortion in the digital modulated signal; they include the BER (bit error rate), the ACPR (adjacent channel power ratio), and the EVM (error vector magnitude) methods. These test methods are widely accepted as new standards. In this section, these methods of evaluating distortions in power amplifiers will be discussed together with simulation techniques in ADS.

However, when the digital signal in Figure 9.64 is transmitted directly, the bandwidth required for the transmission is wider than the bandwidth given by Equation (9.56), which is 1/T_b because the waveform in Figure 9.64 contains a lot of harmonics. To avoid this situation, two transmission techniques are used. One technique uses a digital filter that removes the harmonics; the other transmits a collection of multiple bits using IQ (in-phase and quadrature-phase) modulation. Denoting the modulation carrier frequency as ω_c, the IQ modulation uses two orthogonal carriers, cos(ω_ct) and sin(ω_ct) as shown in Equation (9.57).

When the odd bits shown in Figure 9.64 are assigned to I(t) and the even bits are assigned to Q(t), two bits can be transmitted simultaneously instead of only a single bit. Using the waveform in Figure 9.64 as an example, paired bits of (1, 0), (1, 1), (0, 0), ... are transmitted. A pair of bits is usually called a symbol. The number of transmitted symbols per unit time is defined as a symbol rate. In the example just explained above, two bits are transmitted as a symbol and the symbol rate can be seen to be one-half of the bit rate. Therefore, the transmission bandwidth can be reduced by half.

Extending this concept further, two odd bits can be assigned to I(t) and two even bits can be assigned to Q(t). This way, I(t) and Q(t) will each have four discrete levels. In the previous example, one bit is assigned to I(t) and Q(t), and the resulting I(t) and Q(t) will have two levels, 0 or 1. However, increasing the bit allocation to n, the levels of I(t) and Q(t) will increase to 2ⁿ. The symbol rate then is determined as

Thus, the transmission bandwidth required is reduced by 2ⁿ. In the case where one bit is assigned to I(t) and Q(t), the modulation is called QPSK (quadrature phase shift keying) or 4 QAM (quadrature amplitude modulation). The modulation is called 16 QAM in the case of 2 bits, 64 QAM in the case of 3 bits, and 256 QAM in the case of 4 bits.

When an IQ-modulated signal is demodulated, I(t) and Q(t) appear at the output. The demodulated I(t) and Q(t) can be plotted in the I–Q plane. Figure 9.65 shows the I–Q plots for QPSK and 16 QAM. This is referred to as a constellation plot. By repeatedly plotting each demodulated signal at each symbol time, all possible symbols appear at the I–Q plane and the constellation plot will be similar to the plots shown in Figure 9.65. The constellation plot can be plotted using commercially available instruments. The lower the distortions in the channel of the communication system, the more likely it is that the constellation point or symbol point will appear at a single point, as shown in Figure 9.65. However, in a significantly distorted channel, jitters of the constellation points appear, and by evaluating the jitters, the degree of distortion in a power amplifier can be evaluated.

The standard way to evaluate the jitters of the constellation points is defined as EVM (error vector magnitude) measurement. Figure 9.66 illustrates the concept of EVM measurement.

The EVM can be measured for every symbol time, as shown in Figure 9.66, and calculating the RMS (root mean square) value enables the evaluation of the degree of distortion. Thus, EVM is defined as shown in Equation (9.58).

Here, I_j and Q_j are the I and Q values measured at the j–th symbol time and I_o,j and Q_o,j are the ideal I and Q values. Also, v_max represents the value of the maximum vector magnitude of the ideal constellation point.

Figure 9.67 shows the measurement of the EVM. A spectrum analyzer with the EVM measurement utility is necessary for the EVM measurement. First, the reference constellation points are identified from the input reference signal, and then the EVM obtained with Equation (9.58) is measured by connecting the power amplifier’s output to the spectrum analyzer.

10. Agilent Technologies, Inc., Agilent Technologies ESA-E Series Spectrum Analyzers Modulation Analysis Measurement Personality, E4402-90071, 2002.

We have discussed that the required transmission bandwidth can be reduced using the IQ modulation. Another method to reduce the bandwidth is to use a low-pass filter, which converts the harmonic-rich bit waveform shown in Figure 9.64 into a smooth waveform. However, a simple analog lowpass filter generates ISI (intersymbol interference). When the bit waveform in Figure 9.64 is viewed as a superposition of independent square waveform bits, the analog low-pass filter’s output waveform for a bit overlaps with that of another bit, which causes problems in the decision of bits. Usually, the impulse response waveform of an analog low-pass filter disappears at t = ∞. Thus, the response of each bit overlaps, which results in an error in bit value at the sample time or the decision time, denoted as • in Figure 9.64.

Thus, a filter giving the impulse response

h(nT_b) = 0 n ≠ 0

is required. As an example, the following impulse-response waveform in Equation (9.59) gives a value of 0 at t = nT_b and it does not affect other adjacent bits.

The spectrum of this impulse response H(f) is given by Equation (9.60) and is called a raised-cosine filter. The α here is called the roll-off factor; its value is selected between 0 < α < 1, and 0.5 is usually used.

Figure 9.68 shows the plots of h(t) and its frequency response H(f) given by Equations (9.59) and (9.60). In that figure, when a digital-bit waveform is passed through a raised-cosine filter, the bandwidth of the transmitted signal is determined as approximately 1/T_b.

The complex amplitude or phasor A(t) is called an envelope and is assumed to be a slowly varying waveform compared to the carrier, while signal x(t) can be viewed as a sine wave with the time-varying envelope as its amplitude. An example of the waveforms is shown in Figure 9.69.

Figure 9.70 shows this signal behavior in the frequency domain. Here, the sine-wave envelope signal is chosen. The signal can be considered as a sine wave having amplitude A₁ at time t₁; the spectrum for the signal at time t₁ appears on the right side of Figure 9.70. Similarly, at time t₂, the signal can be considered as a sine wave having amplitude A₂. Thus, the modulated digital signal given by Equation (9.61) can be seen as a carrier whose amplitude is slowly varying with time in the frequency domain.

Figure 9.71 shows the concept of the approximate circuit analysis for the envelope-modulated input signal. First, harmonic balance simulation is performed for the input sine wave with constant amplitude V(t₁) at sample time t₁. The resulting output can be represented by harmonics and the amplitude of the fundamental frequency becomes A(t₁), as shown in Figure 9.71. Here, A(t₁) is called the envelope for the fundamental carrier and other envelopes for other harmonics can be similarly defined. The amplitude A(t₁) is the approximate envelope of the time-varying output signal that corresponds to the time-varying input envelope signal. Through sequential harmonic balance simulations (also called envelope simulation), the envelope of each harmonic is obtained from the simulation results. Thus, the time-domain waveform of the envelope can be observed. Note that the envelope can be interpreted as a time-varying phasor. Furthermore, by expanding the envelope waveform in a Fourier series, the spectrum of each envelope can be seen in the frequency domain. Envelope simulation is used for analyses such as determining the ACPR of a power amplifier, the transient response of an oscillator, the tracking response of a PLL (phase locked loop), and so on. The details of the envelope simulations can be found in the ADS manual.

From Figure 9.73, the TOI and IMD3 are not independent and measuring the IMD3 determines the TOI as expressed in Equation (9.63).

Here, P_o as a tone output power represents the power at which the IMD3 is measured.

The previously explained two-tone method is the appropriate evaluation tool for the metric of power amplifier linearity used in communication systems employing frequency-division multiplexing. However, the two-tone method does not give direct criteria for power amplifier linearity in digital communication systems. The spectrum of digitally modulated signals is typically spread over a wide frequency range and the two-tone method does not provide a direct evaluation for the interference effects on other channels. As a result, in digital communication systems employing CDMA (code division multiple access), power amplifier linearity is evaluated by ACPR (adjacent channel leakage power ratio). ACPR can generally be defined as

However, although conceptually the same, the ACPR definition may depend on the type of communication system. In addition, various communication systems’ standards are usually referred to in the evaluation of the ACPR of a power amplifier.

In addition, the efficiency of the power amplifier generally improves as the output power level approaches saturation; however, communication systems employing digitally modulated signals are mostly operated at low power. In addition, the power amplifier is rarely operated at its maximum output power. In this case, as the power amplifier is used mainly at the output power level with low efficiency, the amplifier’s efficiency significantly drops. Thus, a power amplifier with high efficiency at a wide input power range is required and one such amplifier is the Doherty. The operation of the Doherty amplifier will be briefly discussed in this section.

In Figure 9.74, V_i, V_p, and V_o represent the voltage amplitudes of the fundamental frequency. The typical V_o–V_p characteristic of a power amplifier is also shown in Figure 9.74. The output voltage departs from the straight line as the input voltage increases and enters saturation. If the output voltage V_p of the predistorter increases as V_i increases, as shown in Figure 9.74, the entire input-output characteristic of the system will show linearity. As a result, the linear characteristic can be improved. Figure 9.75 shows the method of obtaining the required input-output characteristic of the predistorter for a linear power amplifier. In Figure 9.75(a), the power amplifier has an output power P_L,1 for an input power P_in,1 (point A). In order to align this to the straight line, the output power P_L,2 corresponding to point B must appear at the output. The output power P_L,2 appears at the output for an input power P_in,2 instead of P_in,1, corresponding to point C. Therefore, for an input power of P_in,1, the predistorter should produce P_in,2. By repeating this process, the predistorter required for the linear power amplifier can be obtained and the linear output power range of the power amplifier can be increased up to the saturation point.

In the previous explanation, three questions must be considered:

1. Is it possible to implement such a predistorter with the specified input-output characteristic?

2. The method in Figure 9.75 is possible only when the input-output characteristic of the power amplifier is assumed to be purely resistive. Can this method still be applied when the input-output characteristic of the power amplifier is not purely resistive?

3. When configured in this way, is the linearity improvement truly achieved?

For the first question, various configurations for the predistorter are possible. For example, it can be implemented using a diode. Assuming the diode to be a purely nonlinear resistive device, it can be considered as an open circuit for a low-input power level, and as an approximate short circuit for a higher input power. Thus, using this property of the diode, the predistorter can be constructed using a well-known branch-line coupler, as shown in Figure 9.76.

If R_A is close to the port impedance of the branch-line coupler, the predistorter provides a linear-attenuated output power due to a small mismatch by resistor R_A. Here, the diode is approximated as an open circuit because the RF input power level is low. Thus, the input-output characteristic is considered to be approximately linear. On the other hand, as the diode comes close to being a short circuit for a high RF input power, total reflection occurs from the diode and the sum of the two reflected powers appears at the output. This combined power will be close to the input power level. Thus, the attenuation is high when the input is low and the input-output characteristic is linear. On the other hand, when the input power level is high, the input-output characteristic shows a gain closer to 1. Thus, an appropriate input-output characteristic for the predistorter can be obtained. By adjusting the values of the devices in Figure 9.76, a predistorter having the required characteristic of Figure 9.75(b) can be designed. There are a variety of predistorter circuits and more details about them can be found in reference 2 at the end of this chapter.

For the second question, the distortion of power amplifiers requires further analysis. In the explanation above, by viewing the distortion of the power amplifier as purely resistive, the output voltage of the power amplifier v_L in terms of the input voltage can be written by Equation (9.64).

When the input is a sinusoidal voltage given by v_in = V₁cosωt, by substituting this into Equation (9.64), the fundamental component of V_L = Fund(v_L(t)) can be rewritten as Equation (9.65).

Here, depending on the sign of the coefficient a₃, the input-output characteristic shown in Figure 9.75(a) can be obtained. However, in general, the power amplifier does not take the form of Equation (9.64). It is commonly known that a time delay appears at the third-order term. Therefore, Equation (9.64) can be rewritten as Equation (9.66).

Thus, substituting the sinusoidal input v_in = V₁cosωt, and rearranging the fundamental component, it can be written as Equation (9.67).

In this case, the previous resistive-predistorter design method may not work due to the differences in the phases of the fundamental and third-order distortion terms. However, the predistorter used in combination with a phase-shifter can improve the linearity of the power amplifier. This Solution is somewhat complicated, but is theoretically possible by expanding the input-output relation of the power amplifier in the form of Equation (9.66). Reference 2 at the end of this chapter can be consulted for more information.

The third question can be proved using the two-tone method. By substituting a two-tone signal into Equation (9.66) and expanding the equation, the third-order term can be removed and the linearity is clearly improved; as a result, the linearity for other modulation signals will also be improved. An ACPR improvement by 10–20 dB has reportedly been achieved, as shown in Figure 9.77. This method is simple but widely used for power amplifier linearization, and the literature currently describes several other methods.

The feedforward power amplifier is the implementation of this concept and is shown in Figure 9.79.

In Figure 9.79, when a two-tone signal is applied to , the amplified two-tone signal with the IMD3 appears at the output of the power amplifier, . In contrast, a distortion-free two-tone signal with an appropriate delay appears at . Assuming the delay line offers a phase delay such that the two two-tone signals at and have a phase difference of 180°, the resulting sum of the two signals appearing at will be a pure IMD3 signal, as shown in the figure. Since the magnitude of the IMD3 signal is generally small, after being sufficiently amplified by the error amplifier, the two signals are combined at the power amplifier’s output. Thus, an amplified two-tone signal alone appears at the output of the power amplifier at , as shown in the figure. In order to make the phase difference of 180° between the two IMD3 signals, a delay line is inserted at the output of the power amplifier.

Thus, the feedforward power amplifier can be experimentally designed using a two-tone input. There may be a disadvantage to this method in that the linearity performance is easily degraded by environmental changes because the adjusted condition to eliminate the distorted signal depends on the conditions of many components. In addition, since the condition is satisfied for selected two-tone input frequencies, the IMD3 elimination condition can also be broken when the frequency changes. Therefore, the bandwidth of the feedforward power amplifier can, in principle, only be a narrow one. In general, this type of amplifier is reported to show more improvement in linearity in a narrow bandwidth than does a predistorted power amplifier.

However, unlike conventional amplitude modulation, both the amplitude and phase of a carrier changes in modern digitally modulated signals. It is not easy to separate the amplitude-modulation and phase-modulation components. However, using digital signal processing, as shown in Figure 9.80, the modulation signal can be separated into the signals that require amplitude and phase modulations. The phase modulation is independently performed for the sinusoidal input and is applied to the power amplifier’s input. Thus, the power amplifier amplifies only the phase-modulated signal. On the other hand, the DC supply of the power amplifier varies according to the envelope signal and, using this type of amplification, the efficiency of the power amplifier can be improved.

In the case of a fast modulation signal, the EER structure is not easy to implement because the DC supply of the power amplifier generally changes slowly. The power amplifier usually requires a large current, from a few amperes to several tens of amperes, and a DC supply voltage from as much as a few volts to typically several tens of kV. Therefore, varying this amount of power supply voltage according to the modulation signal is not an easy task. In addition, because the DC voltage for a power amplifier is generally supplied through a bypass capacitor, that capacitor significantly limits the high-frequency modulation signal.

11. G. Hanington, P-F Chen, et al., “High-Efficiency Power Amplifier Using Dynamic Power-Supply Voltage for CDMA Applications,” IEEE Transactions on Microwave Theory and Techniques 47, no. 8 (August 1999): 1471–1476.

Figure 9.82 shows the efficiencies of a class-B power amplifier and Doherty amplifier with respect to input power. The x–axis is scaled in decibels. In the case of the class-B power amplifier, the efficiency rapidly increases with respect to the input power. Therefore, when a class-B power amplifier is employed in a system having the output-power probability distribution shown in Figure 9.81, the power amplifier will operate at low efficiency for most of the time. In contrast, the Doherty amplifier maintains efficiency at maximum output power within a significant input power range even when the input power is low. Thus, when the operation requires better efficiency for a wide range of input power, the Doherty amplifier appears to be the ideal choice. A multistage Doherty amplifier can be used to further improve the range of this efficiency. Refer to reference 2 at the end of this chapter for more information.

Figure 9.83 shows the structure of the Doherty power amplifier. Two active devices are used in the power amplifier; the device used as “Main” is biased as class-B using the DC supply voltage V_bm; the device marked as “Peaking” is usually biased as class-C by adjusting the DC voltage V_bp. In addition, all the transmission lines used in the input and output are one-quarter-wavelength long. The two active devices used in the Doherty amplifiers may be different due to their costs or specifications; however, for this discussion it is assumed that both devices are the same.

Figure 9.84 shows the normalized drain currents versus input voltage for the devices “Main” and “Peaking,” which operate in class-B and -C, respectively. The drain current waveform of the class-B power amplifier has a sinusoidal-tip shape. The drain current I_m in Figure 9.84 represents the fundamental component of the sinusoidal-tip-shaped waveform. A plot of I_p versus the input voltage can be similarly interpreted. The drain current I_m linearly increases from 0 with respect to the input voltage because the device “Main” is biased as class-B. However, in the case of I_p for the device “Peaking,” the drain current I_p does not flow below a certain level of the input voltage because it is biased as class-C. The current I_p begins to increase with respect to the input voltage beyond the threshold voltage. In Figure 9.84, the “Peaking” device is so biased in class-C such that no output current flows below V_in = 0.5. In addition, denoting the maximum values of I_m and I_p as I_M and I_P, respectively, the normalized drain currents I_m and I_p by I_M and I_P are shown in Figure 9.84. It is also assumed that I_M = I_P. Thus, denoting the normalized input voltage V_in as x(0 < x < 1), I_m and I_p can be expressed as shown in Equations (9.68) and (9.69).

In order to analyze the combined output of the “Main” and “Peaking” devices in Figure 9.84, the equivalent circuit of the Doherty amplifier’s output from Figure 9.83 is drawn in Figure 9.85. The current sources I_m and –jI_p in Figure 9.85 represent the currents arising from the drains of the “Main” and “Peaking” devices, respectively. The drain current of the “Peaking” device is phase-delayed by 90° due to the phase delay of the input voltage, as shown in Figure 9.85.

The transmission line is represented by ABCD parameters as expressed in Equation (9.70).

From Equation (9.70), it can be seen that V_p = –jZ_oI_m. Thus, as shown in Figure 9.84, the drain voltage V_p of the “Peaking” device has the same dependence on the input voltage as I_m. The drain voltage V_p reaches the maximum value for I_m = I_M, and the maximum voltage of V_p is denoted as V_M. Then, the magnitude of V_p normalized by V_M can be plotted against the input voltage, which is the straight line of I_m shown in Figure 9.84. Using Equation (9.70) again, V₁ can be expressed as Equation (9.71).

Because I_p = 0 for x < 0.5, there is no contribution of I_p up to x = 0.5 in Equation (9.71). Setting (Z_o)²/R to reach the maximum output voltage V_M at x = 0.5, the drain voltage V_m of the “Main” device will reach maximum voltage V_M at x = 0.5, as shown Figure 9.84. Since the “Peaking” device is in the off state, the efficiency of the “Main” device becomes the efficiency of the Doherty amplifier below x < 0.5. For x > 0.5, the “Peaking” device turns on and the drain current I_p flows. The voltage V_m changes due to the contribution of the current I_p and generally becomes a piecewise line. As the signs of the two terms in Equation (9.71) are different, they are found to cancel out each other. If the further increase by I_m is exactly cancelled by I_p for x > 0.5, the drain voltage V_m of the “Main” device maintains the maximum output voltage V_M at the normalized input voltage of 0.5. Thus, the plot of V_m appears, as shown in Figure 9.84. The cancellation of the two terms in Equation (9.71) is done to make the two terms have the same slopes for x. Since the slope of I_p is 2 for x, (Z_o)²/R should be equal to 2Z_o in order to cancel out each other. Thus, the relationship in Equation (9.72) is satisfied.

Because Z_o = 2R in Equation (9.72), the efficiency of the “Main” device when operating as a class-B amplifier decreases for x > 0.5; however, the efficiency of the “Peaking” device when operating as a class-C amplifier increases as x increases. As a result, the Doherty amplifier maintains an approximately constant efficiency in the range of 0.5 < x < 1. The efficiency of the Doherty amplifier can be calculated from the Fourier series of class-B and class-C amplifiers explained in section 9.4.1. Since Figure 9.84 represents the amplitude of the fundamental component, the DC current component can be calculated using Equations (9.8) and (9.9a). The DC components of the “Main” and “Peaking” devices I_m,0 and I_p,0 are expressed in Equations (9.73) and (9.74).

Here, the conduction angle is θ = cos^-1(0.5). Thus, setting the DC drain supply voltage to V_DD = 1, the normalized DC power consumption can be obtained with Equation (9.75).

The RF output power is determined by computing the power supplied by the two current sources of Figure 9.85. The RF output power is given by

From Equation (9.76), the efficiency is calculated as shown in Equation (9.77).

The DC power consumption computed using the DC current calculated from Equations (9.73) and (9.74) and the RF power calculated from Equation (9.76) are shown in Table 9.13.

Figure 9.86 is a plot of the calculated efficiencies in Table 9.13. Considering that the Doherty amplifier is normally used in the high-efficiency range starting from the normalized input voltage V_in = 0.5, it means that the Doherty amplifier in Figure 9.86 provides high efficiency up to 6-dB back-off input power. The peak of the efficiency at V_in = 0.5 can be moved by adjusting the conduction angle; using this method, a Doherty power amplifier with various ranges of back-off input power can be achieved.

• The active devices such as GaN HEMT and LDMOSFET that are widely used for PAs are introduced. GaN has a wide bandgap and good thermal conductivity, which leads to a high breakdown voltage and a high power dissipation capability. As a result, a GaN HEMT is an appropriate device for a high-power amplifier.

• The Si LDMOSFET is a device with a breakdown voltage that is improved through drain engineering. However, due to the low electron mobility of Si, its use is primarily limited to applications with frequencies below 4 GHz.

• The optimum load impedance of an active device is experimentally obtained from a load-pull measurement setup that employs impedance tuners. Alternatively, the optimum load impedance can be obtained through a load-pull simulation when the large-signal model of an active device is available. In the load-pull simulation, harmonic impedances should be taken into consideration.

• Power amplifiers can be classified into class-A, -B, -C, -D, -E, and -F. A class-A PA provides high linearity; however, its efficiency is limited to 50% or less. A class-B PA eliminates the stand-by power consumption of the class-A PA and its efficiency is below 78.5%. Moving the operating point further from the pinch-off results in the class-C PA provides a higher efficiency than does the class-B PA; however, from the output power point of view, the power capability of the active device is not fully exploited.

• Class-D and -E PAs operate with a transistor as a switch and their efficiency can reach 100%. However, they lose the amplitude information. A class-E PA employs the detuned resonator circuit. Using the class-E PA, the drain or collector voltage does not show an abrupt transition or possible device damage, and an efficiency drop can be avoided.

• A class-F PA uses multiple resonators in the load to flatten the drain voltage. The maximally flat and maximum efficiency waveforms for limited harmonics are derived. They can be used to estimate the efficiency and optimum resistance of a class-F PA.

• A design example of a class-F PA using the TriQuint GaN HEMT model is demonstrated. The design follows these steps:

1. Stabilize the device

2. Obtain the optimum source and load impedance extraction using load-pull simulation

3. Implement the input matching circuit and a class-F load matching circuit using lumped-element matching circuits

4. Replace the lumped-element matching circuits with the physical layout components

5. Tune the implemented matching circuits through EM simulation

6. Verify the EM-simulated matching circuits

• Power amplifier evaluation methods and specifications for linearity are presented. The two-tone, ACPR, and EVM methods are described.

• A power amplifier’s linearity can be improved by building a composite PA. Predistorter, feedforward, and EER techniques are used to improve PA linearity.

• The high-efficiency range of a power amplifier can be extended by using a Doherty power amplifier. Using a simplified example, we demonstrate that the amplifier’s high-efficiency range can be extended.

• The power amplifier is a key component of a communication system and it is constantly attracting the interest of many researchers. Because power amplifier design is a field in which new concepts are continuously emerging, the readers should keep abreast of recent research results.

2. S. C. Cripps, Advanced Techniques in RF Power Amplifier Design, Boston: Artech House, Inc., 2002.

3. A. Grebennikov and N. O. Sokal, Switchmode RF Power Amplifiers, Amsterdam: Elsevier, 2007.

4. TriQuint semiconductor. TriQuint EEHEMT model implemented in ADS and AWR for TQT 0.25 um 3MI GaN on SiC process 1.25 mm discrete FET. April, 2009.

5. S.C. Cripps, RF Power Amplifiers for Wireless Communications, Boston: Artech House, Inc., 1999.

6. Agilent Technologies, Advanced design system 2009U1. Available at http://www.keysight.com/en/pd-1612226/ads-2009-update-1?cc=US&lc=eng, 2009.

global Impedance Equations

;Tuner reflection coefficient

LoadTuner=LoadArray[iload]

LoadArray=list(0,rho,fg(Z_l_2),fg(Z_l_3),fg(Z_l_4),fg(Z_l_5))

iload=int(min(abs(freq)/RFfreq+1.5,length(LoadArray)))

fg(x)=(x-Z0)/(x+Z0)

9.2 Prove that the optimum load resistance value of a class-C power amplifier is

Then, normalizing the output power by the maximum output power of a class-A amplifier, prove that the following ratio is obtained.

9.3 (ADS problem) Using the output circuit of the class-B power amplifier shown in Example 9.5, and fixing the load resistance value as the resistance value that gives maximum output power, plot the output power versus the input power. In the plot, consider the input power as the output power of the fundamental frequency. Compare this result with the results of Figure 9.25 and discuss the reasons for the difference.

9.4 (ADS problem) Consider the BJT of the voltage-switching class-D amplifier shown in Figure 9P.1 as an ideal switch; using ADS, show that the output voltage V_L appears as a sinusoidal voltage. Set the Q of the series resonant circuit to be more than 10.

9.5 (ADS problem) In the single-ended class-D amplifier circuit shown in Figure 9.26, simulate the circuit using ADS with the DC block capacitor replaced by a high Q-series resonant circuit. Explain why the result is different from that of problem 9.4.

9.6 Prove Equation (9.32).

9.7 The harmonic impedance Z_n of the class-E amplifier can be expressed by inspection as shown below. Explain why. Another way to express this is for Z_n to expand v_n(t) and i_n(t) into a Fourier series and Z_n can then be determined from the ratio of the Fourier series of v_n(t) and i_n(t) at the same frequency.

9.8 Figure 9P.2 is a class-E amplifier. For operating in the optimum condition, the following relationship must be satisfied (see reference 3, above).

Then, setting f_o = 1, P_out = 1, and V_CC = 1, plot the waveforms of v(t), i(t), and v_out(t).

9.9 Prove that the value of b that satisfies Equation (9.39) is b = 0.1667.

9.10 Calculate the power capability, M_p, of the class-E amplifier in Figure 9.35. Compare this with the power capability of the ideal class-F amplifier.

9.11 For the following amplifier in Figure 9P.3, given that power supply voltage V_CC = 10 V, and the maximum current I_max = 1 A, determine the optimum impedance, R_opt, for maximum efficiency using Tables 9.4, 9.5, and 9.6.

9.12 In the following circuit in Figure 9P.4, given that the L_o–C_o has a high-Q and resonates at the frequency ω_o and that it has the following settings for the output matching circuit,¹²

12. A.V. Grebennikov, “Effective Circuit Design Techniques to Increase MOSFET Power Amplifier Efficiency,” Microwave Journal 43, no. 7 (July 2000): 64–72.

Calculate the maximum efficiency.

9.13 (ADS problem) The circuit of Figure 9P.5 is an example of an ideal class-F amplifier. By considering the output of the active device as a switch, plot the waveforms of v(t), i(t), and v_out(t). Now given that the L₁ – C₁ resonates at the fundamental frequency f_o, set a high value for Q and then simulate.

9.14 Discuss the π/4-DQPSK modulation scheme, and explain why PAPR (Peak to Average Power Ratio) in this scheme can be improved.

9.15 A pre-distorter with the input-output characteristics given by v_p=v_in+b₃(v_in)³ is to be used to linearize the power amplifier represented by the input-output characteristics given by v_L = a₁ v_p – a₃(v_p)³. In order to linearize the amplifier, prove that b₃=a₃/a₁. With such a pre-distorter, the output voltage characteristic of the power amplifier is represented by the 5th, 7th, and 9th distorted terms; determine the coefficient of the 5th term.

9.16 For a power amplifier and a predistorter modeled by v_L = a₁ v_p(t)–a₃(v_p(t–τ))³, and v_p = v_in(t)–b₃(v_in(t–τ’))³ respectively, find a relation for a sinusoidal input to eliminate the third-order term at the amplifier output.

9.17 In the pre-distorter with v_p = v_in(t)–b₃(v_in(t–τ’))³, the third order term design requires the conditioning of amplitude and phase. When only the third-order term can be separately extracted, the design of the pre-distorter is made easy, which is called a “cuber” in reference 2. Propose the block diagram to extract the third-order term of the predistorter.

9.18 The most general approach for modeling the power amplifier will be the recently developed X-parameter method. Search X-parameters on the Web.

9.19 (ADS problem) In this chapter, the 6-dB back-off Doherty amplifier was explained, which maintains a high efficiency even at 6-dB back-off power. By a similar concept, a 10 dB back-off Doherty amplifier is also possible. Calculate the efficiency characteristics of this amplifier.