Chapter 11. Phase-Locked Loops

A crystal oscillator is known to be the most stable oscillator to date and most communication systems require a phase noise as low as that provided by the crystal oscillator. However, it is not possible to fabricate crystal oscillators beyond a few hundred MHz. In contrast, microwave oscillators can be fabricated for high-frequency applications albeit with poor phase noise. The comparison of the phase noises of a 10-GHz VCO (voltage-controlled oscillator) and 10-MHz crystal oscillator (its frequency is multiplied by a factor of 1000 to obtain 10 GHz) is shown in Figure 11.1.

In that figure, the optimum frequency source may be one that has the phase noise of the crystal oscillator for a low offset frequency, while it follows the phase noise of the VCO for a high offset frequency. The optimum phase noise characteristic is shown by a solid line in the figure. The frequency source with the optimum phase noise characteristic in Figure 11.1 can be implemented using a PLL (phase-locked loop). In addition, a frequency source whose frequency increases or decreases with a specified frequency step (usually referred to as a channel) is usually required in communication systems. This type of frequency source is referred to a frequency synthesizer that can be configured using a PLL. In this chapter, the configuration and basic operation of a PLL will be discussed.

Since the oscillation frequency of the VCO, ω_v, varies according to the tuning voltage V_c, it can be expressed using θ_v with Equation (11.2).

Expressing Equation (11.2) in a Laplace transform gives Equation (11.3).

Here, K_v is termed the tuning sensitivity of the VCO, and its unit is [rad/sec·V]. The phase detector in Figure 11.2 is a device that converts the phase difference between the two input signals into a voltage and its proportionality constant is termed a phase detector constant K_d. Thus, denoting the output voltage of the phase detector as V_d, we obtain Equation (11.4).

The dimension of K_d is thus [V/rad]. Note that the output voltage of the phase detector is a slow time-varying voltage close to the DC voltage. The low-pass filter connected to the phase detector is called the loop filter and its function is to remove the harmonics that appear in the phase detector. F(s) represents the transfer function of the loop filter.

In order to examine the operation of the PLL in Figure 11.2, first consider the case of F(s) = 1, and θ_n = 0, which results in V_c = V_d. Assuming that the steady state is reached, the tuning voltage V_c of the VCO is no longer considered to vary with time. If V_c varies with time, then the assumption of the steady state would be violated. Therefore, the output voltage of the phase detector V_d does not vary with time. Thus, the phase error θ_ε at the steady state is expressed in Equation (11.5).

Under the steady state condition, since V_d is a DC voltage that no longer varies with time, then differentiating both sides of Equation (11.5) gives Equation (11.6).

Thus, when F(s) = 1, the frequency of the VCO is found to be equal to that of the reference oscillator; however, it should be noted that the reference oscillator and the VCO have a phase difference given by Equation (11.5). Initially, the frequencies of the VCO and reference oscillator are different prior to reaching the steady state and a tuning voltage proportional to the phase difference is then formed that drives the frequency of the VCO to a value equal to that of the reference oscillator. As a result, the tuning voltage of the VCO should be established to make the frequency of the VCO equal to the frequency of the reference oscillator and the phase error defined by Equation (11.5) inevitably occurs when F(s) = 1.

This phase error can be removed by implementing F(s) with an integrator. However, even with the integrator, the frequency of the VCO should not be time-varying at the steady state and subsequently the tuning voltage, V_c, of the VCO does not become time-varying. Since the tuning voltage V_c in Figure 11.2 is the output of the integrator, that output is therefore constant and independent of time at the steady state. Thus, the input of the integrator must be zero. If that input is not zero, then by integrating the non-zero input with respect to time, the output will consequently vary with time.

When the input is positive, the output of the integrator increases with time while it decreases with time when the input is negative. As a result, the integrator output will vary with time. Since the integrator output is the tuning voltage V_c, that tuning voltage varies with time, which violates the assumption of a steady state. Therefore, by simply inserting an integrator into the PLL circuit, the phase error given by Equation (11.5) becomes 0, that is, θ_ε = 0. As a result, when an integrator is used as a loop filter, not only the phases but also the frequencies of the two oscillators are made equal. The VCO is thus synchronized with the frequency and phase of the reference crystal oscillator.

Next, we examine the phase noise of the PLL’s output (and also the VCO’s output). Here, setting K = K_d K_v, the PLL output θ_o is computed as shown in Equation (11.7).

Here, H(s) represents the closed-loop gain of the PLL. Since the output phase noise consists of two independent noises θ_i and θ_n, the PLL output phase noise can be written as Equation (11.8).

In general, since the closed-loop transfer function H(s) → 1 when s → 0 and H(s) → 0 when s → ∞, H(s) thus shows the characteristic of a low-pass filter. The phase noise of the PLL output from Equation (11.8) follows the phase noise of the reference oscillator within the bandwidth of H(s), while it follows the phase noise of the VCO outside the bandwidth of H(s). That is, the expression above can be approximately written as Equation (11.9).

Thus, the phase noise of the PLL’s output can be determined using Equation (11.8). This is plotted as shown in Figure 11.3.

To configure the PLL in Figure 11.2, the frequencies of the VCO and of the reference oscillator must be equal. This is practically impossible to achieve as it is common for the reference oscillator’s frequency to be low, while the VCO’s is usually high. The problem can be solved by using a frequency multiplier or frequency divider in the PLL. The frequency divider is often used to configure the frequency synthesizer. Two configurations of the PLL using the frequency divider are shown in Figure 11.4.

The operations of the two PLLs can be explained using the steady-state concept. Assuming the loop filters in Figure 11.4(a) and 11.4(b) are implemented using a kind of integrator, the output voltage of the phase detector will be zero in the steady-state. Thus, in the case of the frequency synthesizers shown in Figure 11.4(a), Equation (11.10) is satisfied.

The output frequency of the PLL can be obtained by differentiating Equation (11.10) with respect to time, which results in ω_o = Nω_i. Thus, the PLL output frequency can be obtained by multiplying the frequency of the reference oscillator by N. In addition, from Equation (11.9), the output phase noise is equal to the phase noise of the reference oscillator (multiplied by N) in the loop bandwidth, while it is equal to the phase noise of the VCO outside the loop bandwidth.

In the case of the reference oscillator shown in Figure 11.4(b), whose frequency is R-divided, Equation (11.11) is written by the same method as

Therefore, by varying the frequency division ratio, a frequency corresponding to integer multiples of the frequency step ω_i/R becomes the output frequency. At the same time, the phase noise of the reference oscillator multiplied by N/R is obtained inside the loop bandwidth, while outside the bandwidth, the phase noise of the VCO is obtained.

The output voltage v_IF(t) of the DBM in Figure 11.5 can be written as Equation (11.12).

It should be noted here that v_IF(t) in Equation (11.12) is independent of the LO signal amplitude, V_REF. This is possible when the amplitude V_REF of the LO signal in Figure 11.5 is sufficiently large. As a result, the output v_IF(t) is proportional only to the RF signal amplitude, V_RF. Also note that v_IF(t) is composed of two components: the frequency up-converted and down-converted components. However, only the down-converted components are used as the output of phase detector. Thus, when the frequencies of the LO and RF signals are equal, the output of the phase detector is expressed in Equation (11.13),

which is proportional to the cosine of the phase difference between the two signals. Therefore, the output of the DBM phase detector acts as shown in Figure 11.6.

From Figure 11.6, the output of the phase detector has a period of 2π for the phase difference between the two signals, and it has a positive slope in the range of +180°-+360°. Therefore, phase-locking is possible for the phase difference in the range of +180°-+360°, but the linear range appears in a narrow range around 270°. The output voltage of the phase detector is 0 when the phase difference is 270°, and thus the reference signal and the VCO synchronize with the phase difference of 90° when a DBM phase detector is used in a PLL. As is obvious from Equation (11.13), the disadvantage of the DBM phase detector is that the linear range occurs only in a limited range of the phase difference. Also, because the phase detector constant is proportional to the RF amplitude, the RF amplitude should be kept constant to preserve the phase detector constant given by the K_v = K_LV_RF constant.

The DBM phase detector operates as a linear phase detector for a small phase difference. The linear range of the phase detector can be significantly increased by implementing the phase detector that uses logic circuits, and a typical example is the Exclusive OR (XOR) phase detector shown in Figure 11.7.

As shown in Table 11.1, the XOR gives the logical output for the two logical signal inputs. Consider the supply voltage V_CC and 0 (GND) as the logic values that correspond to H (logic high) and L (logic low), respectively. Therefore, the XOR output yields H (V_CC) for the logic inputs pairs (H, L) or (L, H). When two waveforms with the same frequency are applied to the inputs of the XOR, the XOR output waveform appears, as shown in Figure 11.8. When the XOR is viewed as a phase detector, its output is the average DC voltage of the output waveform also shown in Figure 11.8.

From Figure 11.8, the output waveform shows two pulse tips per period T. The width and amplitude are t₂ - t₁ and V_CC, respectively. Thus, the average DC voltage can be expressed as Equation (11.14a).

Here, θ corresponds to the phase difference between the two signals, and the phase detector constant is given by

Therefore, the XOR phase detector gives an output that is proportional to θ and has a phase detector constant given by Equation (11.14b).

When the two inputs applied to the XOR phase detector have a phase difference of less than 180°, the output voltage increases in proportion to the phase difference, as shown in Figure 11.9. Conversely, when the phase difference is greater than 180°, the phase detector output decreases as shown in Figure 11.9. From that figure, phase detector voltage V_d,1 arises for two phase difference values θ₁, and θ₂. An XOR phase detector does not have a one-to-one correspondence with the phase difference. The reason for this phenomenon is that the two pulse tips occur per period as a result of the XOR’s operation. Therefore, the XOR phase detector can be used as a phase detector with a positive slope for a phase difference range of 0° < θ < 180°.

Another type of phase detector can be constructed that uses a sequential logic circuit, as shown in Figure 11.10. The phase detector in that figure is usually referred to as a PFD (phase frequency detector). The PFD can be configured with various sequential logic circuits.

If the reference signal (REF) is leading when compared to the comparison signal (SIG), as shown in Figure 11.11(a), the UP output of the PFD in Figure 11.10 climbs to H at the rising edge of the REF signal and falls to L at the rising edge of the SIG. Conversely, if the comparison signal is leading when compared to the REF signal, as shown in Figure 11.11(b), the DN output climbs to H at the rising edge of the SIG and falls to L at the rising edge of the REF signal. In addition, when the UP is in the H-state, the DN shows no change even at the rising edge of SIG. Similarly, when the DN is in the H-state, the UP shows no change even at the rising edge of REF.

Thus, for the UP and DN outputs, the phase detector output voltage v_o(t) will appear as shown in Figs. 11.11(a) and (b), respectively. Note that in the absence of input, v_o(t) stays at one-half of the supply voltage. In this state, the external circuit is also cut off from the PFD circuit and is said to be in a high impedance state.

Thus, for input waveforms of the same frequency, the PFD yields a pulse tip only once in a period, as shown in Figure 11.11. Since the phase detector output is the average DC voltage of v_o(t), it can be expressed as Equation (11.15)

and the output is proportional to θ. This is shown in Figure 11.12.

Note that the phase detector output is at its maximum when the phase difference between the two waveforms is 360º; also note that the phase detector voltage has a one-to-one relationship with the phase difference in the range of 0°-360°. In addition, compared with the other phase detectors previously discussed, the PFD is found to operate as a linear phase detector for a wide range of phase difference.

Note that the PFD output appears as a voltage. When the output of the phase detector is a voltage, an ideal integrator for the loop filter is difficult to implement with passive components. Thus, a current drive circuit is inserted at the end of the PFD shown in Figure 11.13. The circuit in that figure provides a constant current I_p flowing toward the load when the UP is H, whereas the constant current I_p flows from the load when the DN is H. With such a configuration, the phase detector voltage V_d of Equation (11.15) is converted to a current I_d and the relationship between the phase detector output current and the phase difference is written as Equation (11.16).

The current drive circuit is called a charge pump. Modern phase detectors are configured by connecting a charge pump to the PFD and the phase detector then provides a current proportional to the phase difference. With this type of configuration, the tuning voltage of the VCO becomes the phase detector current multiplied by the impedance of an external loop filter (V_c = I_dZ(s)), which drives the VCO. The integrator can thus be implemented with a simple capacitor. By easily connecting a capacitor to the phase detector in Figure 11.13, the tuning voltage becomes the integral of the phase detector current. However, in the case of the voltage-type phase detector, an integrator cannot be implemented with a simple capacitor.

As described earlier, the PFD provides a voltage output proportional to the phase difference and that voltage output is converted to a current output using a charge pump. However, the output of a typical phase detector is accompanied by a noise floor that can cause problems in the detection of the phase difference. Usually, the larger the frequency division ratio becomes, the smaller the phase noise of the frequency divided by the output of the VCO. The smaller divided phase noise is then applied to the input of a phase detector, which may be less than the noise floor of the phase detector. If the divided phase noise of the VCO is less than that noise floor, the output of the phase detector is simply its own background noise and the desired phase difference cannot be obtained.

The noise floor of a PFD phase detector is usually presented as a specification of the phase detector and an example of the PFD noise floor is shown in Figure 11.14. In that figure, when the comparison frequency increases, the noise floor of the phase detector also increases. The specification of the phase detector is usually defined as the phase detector noise at a comparison frequency of 1 Hz. Therefore, at a comparison frequency of f_r, the noise floor of the phase detector can be empirically expressed as

The empirical Equation (11.17) can be verified using Figure 11.14, in which the noise floor of the PFD at a comparison frequency of 10 kHz and 100 kHz is about -175 dBc/Hz and -165 dBc/Hz, respectively. Because of this, the PFD noise floor increases by 10 dB due to a decade change of the comparison frequency. Equation (11.17) clearly shows the computed decade change of the noise floor. Therefore, when the noise floor at an arbitrary comparison frequency is known, then the noise floor at all other comparison frequencies can be determined using Equation (11.17).

To examine the effect of the phase detector noise floor, consider the case in which the frequency of the VCO is divided by N in order to lower the VCO frequency to the comparison frequency. Denoting the phase noise of the VCO as φ_v(f), the divided phase noise of the VCO is φ_v(f)/N². Also, denoting the noise floor of the phase detector as φ_PD, the phase detector provides an output proportional to the phase difference for the frequency-divided VCO input when the phase noise of the VCO is greater than φ_PD; this is given by

For noise levels lower than the value given by Equation (11.18), the phase detector comparison function is disabled. Equation (11.18) can then determine the offset frequency f_m of the VCO. Since the phase noise of the VCO increases as the frequency offset approaches 0 below f_m, the phase detector provides an output proportional to the VCO phase noise, while the phase detector provides an output corresponding to its noise floor above f_m. In addition, as the division ratio N in Equation (11.18) gets larger, the phase detector provides an output proportional to the VCO phase noise for only a narrow range of the offset frequency.

Generally, there are two types of frequency dividers: a fixed divider (with a fixed division ratio such as /2, /4, /8, and so on, as shown in Figure 11.15) known as a prescaler and a programmable divider whose division ratio can be determined by a program (i.e., a programmable divider or counter). The fixed divider generally operates up to high frequencies, while the programmable divider that is required for a PLL operates at low frequencies.

Thus, in order to divide the high-frequency output of the VCO, a high-speed fixed divider is first placed in the frequency divider’s chains, as shown in Figure 11.16, and the programmable divider follows the fixed divider. However, as shown in that figure, due to the fixed divider, it is not possible to implement a frequency synthesizer that successively increases with a frequency step of the comparison frequency f_r. That is, when a frequency divider chain is built using the fixed P-divider and the programmable M-divider, the frequency that can be synthesized is f_o = PMf_r (M = 1,2, ...). Thus, the frequency step of the frequency synthesizer becomes Pf_r.

In contrast, for the high-speed fixed P-divider, it is possible to change the division ratio between P and P + 1 based on the control signal. This type of counter is called a dual modulus counter. Using a P/P + 1 dual modulus counter, the output frequency step of the frequency synthesizer can be lowered to f_r. Generally, the output frequency of the frequency synthesizer with a frequency step of f_r can be expressed as

f_o = Nf_r = (MP + A) f_r

where M and A are integers and represent the quotient and remainder, respectively, when N is divided by P. This can be rewritten as

Thus, based on Equation (11.19), the division ratio of N is accomplished by dividing the VCO signal A– times by P + 1, and then dividing (M - A) times by P.

To implement the right side of Equation (11.19), the divider chain is configured as shown in Figure 11.17. Then, one period of the square wave is generated after N cycles of the VCO input; that is, the frequency of the VCO can be divided by a general integer N, not by the integer multiples of P. The A-counter and M-counter of Figure 11.17 are programmable dividers, and the division ratios of M and A are initially determined by built-in registers. In addition, the division ratio of the dual modulus counter in Figure 11.17 is initially set to P + 1.

From Figure 11.17, the VCO frequency divided by P + 1 is concurrently applied to the input of the A- and M-counters. When the A-counter completes A times of division, the A-counter generates the control signal (usually the rising edge occurring after counting is completed); the division ratio of the dual modulus counter is then set to P and no further division is performed in the A-counter. Thereafter, only the M-counter operates. Thus, for the rest of VCO cycle, the VCO frequency divided by P is the input to the M-counter, which then divides the input (M - A) times. Similarly, the M-counter generates the “RESET” control signal when the division is completed and the M- and A-counters and the dual modulus counter return to their original states by the “RESET” control signal. After this, the operation explained above is repeated. As a result, the frequency of the VCO is divided by N = (M- A)P + A(P + 1). That is, after N cycles of VCO output, one period of the square wave is generated. Therefore, the frequency divider then divides the VCO output frequency by an arbitrary integer N.

A fractional frequency divider can be configured by adding some structures to the architecture of the integer frequency divider shown in Figure 11.17. That is, when the division ratio is changed to N = 100, 100, 100, 101, it corresponds to an average division of 100.25. As a generalization, suppose that, among total F cycles, a signal frequency is divided by N + 1 for K cycles and then divided by N for the remaining (F - K) cycles. The average division ratio M* becomes,

which gives the same effect as dividing the signal frequency by a fraction. It should be noted that the integer K is less than F. The average frequency of the divided output obtained by this division is obviously equal to the VCO frequency divided by M*, but the instantaneous frequency varies with time. The reason for implementing the fractional frequency divider in this way is that the frequency divider basically cannot perform fractional division and only integer division is possible. Thus, denoting the comparison frequency as f_r, the synthesized output frequency of the VCO f_o can be expressed in Equation (11.20).

The implementation of Equation (11.12) depends on the periodic implementation of N + 1. Increasing the division ratio from N to N + 1 is done by increasing the division ratio of the A-counter by 1 from Equation (11.19). In addition, the periodic increment of the A-counter by 1 is accomplished by connecting the output of the M-counter (after the VCO input is divided by N or an N + 1 rising edge is generated) to the input of a separate counter (accumulator), which is made to generate K carries in F cycles. The carries then periodically increase the division ratio of the A-counter by 1. As described above, the implementation of 100,100,100,101 is done by implementing the accumulator as a 2-bit counter. The 2-bit counter generates a carry as

0, 1, 2, 3↑0, 1, 2, 3↑... (1 carry is generated every 4 cycles)

When overflow occurs, the carry is generated. By passing it on to the A-counter, the A-counter is incremented by 1. Therefore, because the carry generation is accomplished with the accumulation of the rising edge outputs of the M-counter, the 2-bit counter is called the accumulator. The detailed architecture of the accumulator can be found in commercial application notes.¹

1. Texas Instruments, Fractional/Integer-N PLL Basics, SWRA029, August 1999. Available online at www.ti.com/lit/an/swra029/swra029.pdf.

From the phase noise point of view, implementing the division ratio as a fraction has several advantages. First, it is not necessary to set the comparison frequency to be equal to the frequency step of the frequency synthesizer; the comparison frequency can be set to a higher frequency; for example, to make a frequency synthesizer of 890 MHz with a frequency step of 50 kHz using an integer divider, the comparison frequency must be f_r = 50 kHz. Thus, the division ratio becomes N = 890/0.05 = 17,800. In contrast, for F = 16, the comparison frequency f_r = 50 × 16 = 800 kHz and the division ratio N_F becomes

In addition, note that the ratio between the integer and the fractional divider is N/N_F = 16. Due to the lowering of the division ratio by 20log(16) = 24 dB, the effect of the phase detector noise floor can be reduced by 24 dB according to Equation (11.18), assuming the noise floor of the phase detector is constant irrespective of the comparison frequency. Thus, the fractional frequency divider eliminates the need to divide the VCO frequency by a large number N and the phase detector noise floor contribution is significantly reduced. As a result, the phase detector noise floor may not be considered in the output phase noise of the frequency synthesizer. Also, because the comparison frequency is high, the loop filter bandwidth of the PLL can be made wider, giving the advantage of a faster lock time.

The architecture of a PLL is shown again in Figure 11.18. In that figure, because the PLL is structured as a feedback, it can be analyzed based on open-loop gain (simply referred to as loop gain). Denoting the transfer function of the loop filter by F(s), the open-loop gain L(s) is obtained as with Equation (11.21).

Note that F(s) has the highest order of s^m+n–1 in the denominator because the VCO contributes 1/s to the denominator.

In addition, using the open-loop gain, the closed-loop gain can be expressed as Equation (11.22).

The classification of the loop filter is based on the highest order of the denominator of L(s), which is defined as the order of the loop filter. Therefore, for Equation (11.21), the order of the loop filter is m + n. In addition, even when the phase detector is directly connected to the VCO without the loop filter (in this case, F(s) = 1), the open-loop gain will have a term of s^-1 due to the transfer function of the VCO. Thus, the order of the loop filter becomes a first order even when there is no loop filter in the PLL. Also, when a low-pass filter whose transfer function has a first-order denominator is included in the PLL, the order of the loop filter becomes a second order. The definition of the order may be different in other literature if the order is defined as the order of a loop filter alone.

In addition, the integration factor in Equation (11.21) is critical in determining the characteristics of the PLL, and its number is often used in the classification of loop filters. This is called the type of the loop filter. Equation (11.21) has the term s^m in the denominator and the loop filter is thus referred to as type m. That is, the type indicates the number of ideal integrators included in the transfer function. The closed-loop gain H(s) of the PLL configuration in Figure 11.19 for a first-order loop filter is expressed as

Therefore, from Equation (11.23), the 3-dB bandwidth (the frequency at which the magnitude of the open-loop gain is 1/2^½) is K/N. As a result, the loop bandwidth is K/N.

When a step phase change (θ_i = Δθ_ru(t)) is applied to the input with the closed-loop transfer function in Equation (11.23), the output phase is

The inverse of the Laplace transform in Equation (11.24) can be written as

From Equation (11.25), the output phase at the steady state can be seen to be NΔθ_r for a step phase change of Δθ_r. Also note that the output frequency for a step frequency change follows the form of Equation (11.24) as expressed by Equation (11.26).

Thus, the output frequency tracks the step input frequency change as the output phase follows the step phase change. Figure 11.19 shows a first-order PLL frequency response and the output waveform for a step phase change.

Note that the phase detector output generates an error given by Equation (11.5) for tracking the step frequency change; however, the output frequency tracks the step frequency change without error. In the first-order PLL, the output is able to track the input frequency change that accompanies the phase error. In addition, as we saw in the previous explanation of phase detectors, not only the DC phase detector voltage, but also many of the comparison frequency’s harmonic components are present in the actual phase detector output. Since the first-order loop filter applies the phase detector output to the VCO without filtering the harmonics, many frequency-modulated spurious components appear at the VCO’s output due to those harmonics. Therefore, the first-order PLL is not commonly used due to its inability to remove the harmonics rather than because of the phase error problem.

The first term in Equation (11.27) is the integration of the input and the second term is proportional to the input. Substituting Equation (11.27) into Equation (11.21), the open-loop gain can be obtained with Equation (11.28).

Thus, the closed-loop gain H(s) is obtained as expressed in Equation (11.29).

Here, ω_n and ζ are called the natural frequency and damping ratio, respectively, of the second-order transfer function, and ω_n and ζ are defined in Equations (11.30a) and (11.30b).

As s → 0, H(s) approaches N, and H(s) → 0, for s → ∞. Thus, the closed-loop gain H(s) has the frequency response of a low-pass filter. Its frequency response is shown in Figure 11.20 with ζ as a parameter. The bandwidth is approximately ω_n, which varies slightly according to ζ. Calculating the 3-dB bandwidth results in Equation (11.31).

From Equation (11.31), the loop bandwidth is close to the natural frequency and varies according to the damping ratio ζ. Therefore, the approximate loop bandwidth can be considered the natural frequency. From Equation (11.28), the magnitude of the open-loop gain L(s) at the natural frequency ω_n can be approximated as 1 by ignoring the term sτ₂, which is generally small at ω_n. Therefore, the natural frequency ω_n is the frequency at which the magnitude of the open-loop gain becomes approximately 1.

Using the transfer function of Equation (11.29), the output phase for a step phase change is found to be

and θ_o(t) can be obtained from an inverse Laplace transform expressed in Equation (11.32).

The time response θ_o(t) is shown in Figure 11.21 with ζ as a parameter. Note that Equation (11.32) is the output phase change due to the step phase change, but as explained previously, the output phase change can be interpreted as the output frequency change for a step frequency change (ω_i = Δω_ru(t)). The same response will be obtained for the output frequency ω_o(t) for a step frequency change ω_i = Δω_ru(t).

From Figure 11.21, at the steady state, the output phase tracks a step phase change that is irrespective of the damping ratio ζ. Thus, the output phase should track the input change as quickly as possible without overshooting it. From Figure 11.21, the optimal tracking can be observed for ζ = 0.707. The time taken to reach the steady state is known as the lock time. The lock time is defined as the time typically taken to reach within 5% of the steady state’s value. The lock time usually varies depending on ζ, but for ζ = 0.707, Equation (11.33) gives

Here ω_n = 2πf_n. Note that in the case of the second-order loop filter, due to the role of the integrator, the phase and the frequency track the input without phase errors for a step frequency change. Therefore, beyond the second order, because the VCO tracks the phase and frequency of the reference oscillator without error, the VCO can be viewed as a phase lock state in the truest sense.

From the results of the second-order loop filter described above, the loop bandwidth is approximately the natural frequency ω_n and the optimal tracking for a step change can be achieved by selecting ζ = 0.707. The lock time thus obtained is the same as that given by Equation (11.33). As a result, the narrower the loop bandwidth ω_n, the longer the lock time, whereas the wider the loop bandwidth ω_n, the faster the lock time. Therefore, once the loop bandwidth is determined in the second-order loop filter PLL, the optimal lock time can be automatically determined. However, in order to make the lock time faster, the loop bandwidth cannot be set to be infinitely large. The loop bandwidth should be set to be less than the comparison frequency. If the loop bandwidth is greater than the comparison frequency, the equations previously derived will not hold. In the derivation, the phase detector output was assumed to be DC. However, in such a case, the loop filter is unable to sufficiently filter out the harmonics of the phase detector and, just as in the first-order loop filter, the harmonics of the comparison frequencies are transferred directly to the VCO. The phase detector output waveform will then severely frequency-modulate a VCO frequency, which gives rise to many unwanted spurious characteristics.

The loop gain of Figure 11.22(a) is expressed in Equation (11.34).

Thus, the ideal second-order transfer function can be implemented using only passive components. Also note that the transfer function of the loop filter F(s) is the impedance Z(s). In the case of Figure 11.22(b), assuming an ideal operational amplifier, Equation (11.35) gives us,

which also implements an ideal second-order transfer function. Since F(s) has a voltage–voltage relationship, the loop filter in Figure 11.22(b) can be applied to the voltage–output phase detector without a charge pump. In addition, because the loop filter uses an active device, it is called an active loop filter. In the case of Figure 11.22(c), F(s) is expressed in Equation (11.36)

and can be used as an approximate second-order loop filter.

The spurious characteristics can be obtained by measuring the output spectrum of the VCO with the spectrum analyzer, as shown in Figure 11.23. To measure phase noise, a spectrum analyzer is used, as explained in Chapter 10. When the phase noise utility is installed in the spectrum analyzer, the phase noise can be conveniently measured without the computation of the N/C ratio as described in that chapter.

The unit step transient response can be obtained by measuring the tuning voltage V_c of the VCO with an oscilloscope, as shown in Figure 11.23. However, the tuning voltage is not a direct measurement of the VCO’s frequency even though it is proportional to the VCO’s frequency. The instrument that can directly measure the frequency change is the signal analyzer or modulation analyzer.² Alternatively, the frequency change with respect to time can be measured by setting the spectrum analyzer SPAN to 0 Hz, as shown in Figure 11.23, and applying the trigger pulse that is synchronized to the unit step frequency change and to the external trigger input in the spectrum analyzer. With these settings, the spectrum analyzer shows the input power variation within the RBW (resolution bandwidth) of the specified center frequency versus time. Consequently, the measurement shows the frequency of the VCO with time and the lock time can be obtained by measuring the time taken to reach the steady-state frequency with an error of the RBW.

2. Agilent Technologies, E5052A Signal Source Analyzer, Advanced Phase noise and Transient Measurement Techniques, Application Note 5989-1617EN, October 2004.

Some examples of measurement results for a frequency synthesizer are shown in Figure 11.24. The output phase noise of the frequency synthesizer and the transient frequency response for a unit step frequency change are shown in Figures 11.24(a) and 11.24(b), respectively. As expected, the output phase noise tracks the phase noise of the VCO outside the loop bandwidth, whereas it follows the phase noise of the reference oscillator within the loop bandwidth. In Figure 11.24(a), the phase noise approximated by two straight lines can be seen to intersect at about 15 kHz and the loop bandwidth can be estimated to be about 15 kHz. Figure 11.24(b) shows the time response to a unit step frequency change. This is measured using a modulation analyzer; the lock time in the figure can be seen to be about 500 μsec.

Next, Figure 11.25 shows the spectrum of the frequency synthesizer measured by expanding the SPAN of the spectrum analyzer. The SPAN is set wider than the comparison frequency. Spurious characteristics can be seen to occur in addition to the synthesized frequency components. As mentioned earlier, the phase detector includes many harmonic components of the comparison frequency. The loop filter removes these harmonics to some extent, but when the filtering is not sufficient, the remaining harmonics modulate the VCO and spurs occur.

To see these effects, by denoting the leakage voltage of the comparison frequency harmonics at the output of the loop filter as V_ssin(ω_mt), the VCO is FM modulated by this leakage voltage. This can be expressed with Equation (11.37).

In addition to the synthesized frequency, the output, the two frequency components ω_c + ω_m and ω_c – ω_m from the right-hand term of Equation (11.37) appear. Thus, spurs occur as shown in Figure 11.25 and it is necessary to lower the spur level by narrowing the loop filter. In the case where a fast lock time is required, the bandwidth should be set wider and the loop filter is then unable to sufficiently attenuate the comparison frequency harmonics appearing at the phase detector’s output. Consequently, this results in larger spurs at the VCO’s output. However, when the bandwidth is overly reduced so as to suppress the spurs, the lock time becomes longer. Higher-order loop filters may be used in such a situation.

Note that a higher-order loop filter yields the transfer function of an open-loop gain that is higher than a third order. Generally, the PLL can become unstable for the open-loop gain transfer function with the third order and above. One way of resolving the PLL instability is to provide a phase margin or gain margin in the open-loop gain. The phase margin method is commonly used in a PLL. The design of higher-order loop filters depends in part on the type of the loop filter. In this section, we will discuss a design that is limited to a charge pump PLL loop filter. The higher-order loop filters are shown in Figure 11.26 and they are formed by modifying the second-order loop filters to give more attenuation at the comparison frequency harmonics. Figure 11.26(a) shows a third-order loop filter and Figure 11.26(b) shows a fourth-order loop filter.

In Figure 11.26(a), R₂ and C₂ comprise the second-order loop filter. The impedance Z(s) of R₂-C₂ branch is expressed in Equation (11.38).

At lower frequencies, the impedance Z(s) is approximated by 1/sC₂, which decreases as the frequency increases. However, at higher frequencies, the impedance becomes Z(s) ≅ R₂. Thus, there is no attenuation of the harmonic leakage for a frequency higher than f_c = 1/2πR₂C₂. By adding C₁ in parallel to the R₂-C₂ branch, the harmonic leakage of higher frequency can be attenuated due to C₁. For the fourth-order loop filter in Figure 11.26(b), an R₃-C₃ stage is added to the third-order loop filter. The R₃-C₃ stage has no effect at low frequency. However, at high frequency the R₃-C₃ stage functions as a low-pass filter thereby severely attenuating the harmonic leakage of the phase detector output. Note that the values of C₁ and C₃ added in the higher-order loop filters are basically small and therefore have little or no effect on the basic form of the second-order loop filter within the loop bandwidth. However, they are inserted to give more harmonics attenuation outside the loop bandwidth. Thus, within the loop bandwidth, the added components in the third-order and fourth-order loop filters have minimum effect on the basic form of the second-order loop filter; this effect appears outside the loop bandwidth and attenuates the high-frequency harmonic leakage of the phase detector output. In reality, however, the added components somewhat distort the response of the second-order loop filter and the effects of the added components must be taken into account when determining their values.

When the third-order loop filter in Figure 11.26(a) is used in the PLL with the integer frequency divider shown in Figure 11.18, the loop gain L(s) is expressed in Equations (11.39a)–(11.39c).

Therefore, the frequency response characteristics can be computed using Equation (11.40).

Generally, the phase of L(s) increases from -180° and then tends to decrease again as the frequency increases, as shown in Figure 11.27. Therefore, for stability, the loop gain must be 1 at the point where the phase is maximum, which then gives the maximum phase margin. The phase from Equation (11.40) is

Differentiating Equation (11.41) to obtain the frequency ω_p at which φ(ω) is maximum, we obtain Equation (11.42).

Then, the frequency for the maximum phase margin ω_p is given by

The frequency ω_p can be defined as the loop bandwidth. This definition is somewhat different from that of the loop bandwidth ω_3dB of the second-order loop filter, but it can be used to identify a newly defined loop bandwidth.

From Equation (11.43), T₂ can be expressed in terms of ω_p and T₁ with Equation (11.44).

Denoting the phase margin as φ_p, the phase margin from Equation (11.41) is φ_p = φ (ω_p) + 180°. Thus, substituting the result of Equation (11.44) into Equation (11.41), T₁ can be obtained with Equation (11.45).

Then, once the loop bandwidth ω_p and phase margin φ_p have been defined, the time constants T₁ and T₂ can be calculated from Equations (11.44) and (11.45).

In addition, in order to make φ_p of Equation (11.45) equal to the phase margin, for the determined T₁ and T₂, |L(jω_p)| = 1. Thus,

Since ω_p, T₁, and T₂ have already been determined, the value of C₁ can be calculated using Equation (11.46), from which R₂ and C₂ can be determined using Equations (11.39b) and (11.39c), and expressed in Equations (11.47) and (11.48).

In summary, for the given loop bandwidth ω_p and phase margin φ_p, the two time constants T₁ and T₂ can be calculated with Equations (11.44) and (11.45). As a result, all the element values of the third-order PLL loop filter can be determined. The lock time of the third-order loop filter is similar to that of the second-order loop filter, and T_lock ~ 1/ f_p (ω_p = 2πf_p).

With the loop filter thus configured, it is not possible to know absolutely the magnitudes of the spurs. However, they are more attenuated than in the case of the second-order loop filter and the relative degree of their attenuation can be determined by comparing the open-loop gain with that of the second-order loop filter. When the spurs of the configured third-order loop filter are measured and are still found to be greater than the specifications shown in Figure 11.25, the spurs’ performance can be improved by employing a fourth-order loop filter, which is an extension of the third-order loop filter. In Figure 11.25, in order to make the spurs below the phase noise, an attenuation of approximately 10 dB is required. The 10-dB attenuation can be achieved by extending the third-order loop filter to the fourth-order loop filter in Figure 11.26(b). The transfer function of the additional R₃-C₃ stage is expressed in Equation (11.49).

Therefore, the required attenuation of the spurs at the comparison frequency f_ref, ATTN can be defined with Equation (11.50).

Using Equation (11.50), the time constant T₃ can be calculated using Equation (11.51).

Adding R₃-C₃ to the third-order loop filter causes a slight change in its element values. The loop gain of the fourth-order loop filter can be approximately written as Equation (11.52).

Here, the time constants T₁ and T₂ are the same as those in Equations (11.39b) and (11.39c). This is similar to the transfer function of the third-order loop filter given by Equation (11.39a). Therefore, Equation (11.44) can be rewritten as Equation (11.53)

and the relationship between the loop bandwidth and phase margin is obtained with Equation (11.54.)

Thus, T₃, T₁, and T₂ can be determined from Equations (11.51), (11.53), and (11.54). The calculated values T₁, T₂, and T₃ can be substituted into L(s) of Equation (11.52). For the phase margin, |L(s)| must be equal to 1 at ω_p. As in the third-order loop filter design, C₁ can be obtained with Equation (11.55).

In addition, C₂ and R₂ can be calculated from the time-constant relationships using Equations (11.56) and (11.57).

Using these formulas, all the fourth-order loop filter element values can be determined. However, as T₃ is expressed in terms of R₃C₃, there is a certain degree of freedom. The value of C₃ should be set 10 times smaller than C₁ because R₃C₃ must not affect C₁. Thus, all the element values are accurately calculated, and the reader may refer to reference 3 at the end of this chapter for the exact values.

As phase noise simulation is related to small-signal noise simulation, the phase noise simulation can be performed using an AC simulation, while the transient response requires an envelope simulation.

In Figure 11.28, LinearPFD is a subcircuit built with a voltage-controlled current source (VCCS). The LinearPFD models the charge pump PFD explained in the previous section, which generates the current in proportion to the phase difference. Here, the phase difference is given by the voltage source. The LinearVCO is an integrator that is similarly modeled using two controlled sources. The LinearDivider also models the frequency divider using a VCVS (voltage-controlled voltage source). The previously mentioned component values of PLL are defined in VAR2. The element values of the loop filter are defined in VAR4.

In VAR5, the variable UnityGainFreq represents the loop bandwidth where the open-loop gain is 1. The variables Min_Phase_Margin and Max_Phase_Margin define the allowable values for the phase margin in optimization. The original schematic does not include the group delay. In that case, the phase of the open-loop gain may not be optimized at the phase peak frequency, which we do not want. Since the group delay is equal to 0 at the phase peak frequency, the allowable group delay limit is set using the variable GD_Limit, which is then used in Goal1 to optimize the group delay to 0. The meas1 defines the open-loop gain, phase margin, and group delay necessary for optimization. The meas2 is a declaration of the output variable for the display window. The original schematic includes more variables but they are deleted for simplification.

The goals from Goal1 to Goal3 are connected to the AC simulation AC1. The AC1 is modified to simulate three frequencies, from UnityGainFreq-Deltaf to UnityGainFreq+Deltaf. This is necessary to compute the group delay. The group delay GD defines the phase change with respect to frequency. Then, the loop filter can be designed using optimization to minimize the three goals. The optimization control Optim1 optimizes the loop filter element values to fit the goals. The AC simulation AC2 is not connected to the goals and it is used to compute the Bode plot of the open-loop gain after the optimization. The sweep frequency range of AC2 is specified in SwpPlan1. After the optimization finished, the Optim1 computes the Bode plot using AC2.

First, the loop filter element values are optimized for a 10-kHz loop bandwidth and a 45° phase margin using the PLL parameters given in Example 11.10. The phase margin is set to the range 45°– 46°. The OLgain is set to the range 0.99–1.01. The group delay GD is set to close to 0. The optimized element values are compared in Table 11.2.

Figure 11.29 shows the magnitude and phase of the optimized open-loop gain. The phase margin is close to 45° and the open-loop gain is close to 1 at the frequency of the 10-kHz loop bandwidth. The higher-order loop filter, such as the fourth-order loop filter, can be obtained using a similar optimization procedure.

In order to compare the results of Example 11.1 with the ADS simulation, the loop filter is set to be a second-order loop filter, as shown in Figure 11.30. The values of C₁ and R₁ of the second-order loop filter can be determined using the given f_n = 1 kHz and f_n = 10 kHz, and the damping ratio ζ = 0.707. From Equations (11.30a) and (11.30b), τ₁ and τ₂ can be determined as

and from the values of τ₁ and τ₂, C₁ and R₁ can be computed as

The values of C₁ and R₁ are computed using the equation in ADS.

Then, since the noise floor of the frequency divider and phase detector were not considered in Example 11.1, a frequency divider and a phase detector without the noise floor should be selected. However, the phase detector without the noise floor is not available in ADS and thus the noise current is set to 0 to eliminate the effect of the noise floor. The frequency divider without the noise floor is available in ADS and the frequency divider is replaced with the new frequency divider in the default PLL simulation schematic. Next, it is necessary to input the phase noises of the reference oscillator and VCO. Instead of a tabular form, the phase noise requires an input as shown in Figure 11.30 that is represented by the 30 dB, 20 dB, and 10 dB slopes, and the noise floor. The phase noise values in Table 11E.1 are thus entered as shown in Figure 11.30.

The simulated phase noise is shown in Figure 11.31. The phase noise simulation results with respect to the loop bandwidth change are the same as those in Example 11.1. The phase noises of the VCO and reference oscillator multiplied by 1000 are also shown in Figure 11.31. These correspond, respectively, to PNTotal, PN_VCO_FreeRun, and PN_RefChain_FreeRun of that figure. They are calculated in the display window using the following equations in Measurement Expression 11.1:

PN_VCO_FreeRun=10*log(0.5*VCO_FR.noise**2)

PN_RefChain_FreeRun=10*log(0.5*RefChain.noise**2)

PNTotal=10*log(0.5*VCOout.noise**2)

Measurement Expression 11.1 Definitions of phase noises in the display window

The calculated values in Figure 11.30 are the voltage values of the noise with respect to frequency. Note that because the simulation gives the noise simulation results, all the noise voltage variables in the previous equations have the noise extension. Of the computed noise voltages, VCO_FR.noise is not explicitly specified in the simulation schematic of Figure 11.30, but it is the value automatically calculated by the subcircuit VCO and stored in the dataset as VCO_FR.noise.

In that figure, it is necessary to understand the two components, VCO_DivideByN and PhaseFrequencyDetCP in order to be able to simulate the PLL’s transient response. PhaseFrequencyDetCP is the PFD with the charge pump explained earlier, and its input signal becomes the baseband signal, which is a time-varying waveform without a carrier. In Figure 11.32, the reference signal is set using a DC power supply and is made to vary with time using the following equation in Measurement Expression 11.2:

Vref=2*pi*Fref*rem(time+0.25/Fref, 1/Fref)-pi,

Measurement Expression 11.2 Reference signal definition in the schematic window

Here, the rem(x, y) function represents the remainder when x is divided by y. Denoting 1/Fref = T, then f(t) = rem(time, 1/Fref) is a sawtooth waveform with a period T. Thus, 0 ≤ f(t) < T and multiplying f(t) by 2*pi*Fref results in Vref having a value 0 ≤ V_ref < 2π. As a result of subtracting the last π term, f(t) becomes a sawtooth waveform having a value of -π ≤ V_ref < π. The function f(t) also shifts to the left along the time axis by 0.25T. The function f(t) is shown in Figure 11.33. Therefore, despite being represented as a DC source, it is, in reality, a time-domain source.

The waveform in Figure 11.33 is fundamentally different from the PFD input waveform described earlier. However, because the PFD is a component that gives rise to a pulse-tip current proportional to the phase difference between the two input waveforms, the same result is obtained even though the input waveforms are different. In addition, the PFD changes at the rising edge of the input waveform. In the case of the sawtooth waveform shown in Figure 11.33, the rising edge corresponds to the time when the input sawtooth waveform crosses 0.5 V.

The output waveform of the VCO appears at the VCO terminal in the form of an envelope signal. The VCO frequency also appears at the frq terminal, which is the baseband signal. Note that the baseband signal’s unit is GHz, while the following Measurement Expression 11.3 expresses it in MHz:

VCO_Freq_MHz=real(frq[0])*1e-3

Measurement Expression 11.3 VCO frequency definition in the MeasEqn

Therefore, VCO_Freq_MHz shows the change of the VCO’s frequency (in MHz) with time. The output of the N–divided VCO in Figure 11.34 appears at the vcon terminal, which is also a baseband signal. The output waveform is also a sawtooth waveform that also represents a sawtooth waveform shifted to the left by 0.25T as in the case of the reference waveform. When the two inputs are applied to the input of the PhaseFrequencyDetCP, the output current of the phase detector appears, as shown in Figure 11.34. In that figure, the output current begins to rise at the rising edge of the reference signal, Vref (the point where Vref crosses 0.5 V), and falls at the rising edge of the input VCO (the point where vcon crosses 0.5 V).

In addition, the VCO frequency division ratio can be made to change from N to N + N_Step, which is achieved by applying a step function with step height N_step to the dN terminal of the VCO. Here, N_step is set to N_step = 400, which allows for easy viewing of the transient waveform, but a similar waveform appears even when N_step = 1. The next issue is that the unit frequency step change represents the reference signal frequency step change in the previous explanation of section 11.4.2. However, here, the division ratio of the frequency divider is changed. This will give the same results as the unit step change of the reference signal; that is, when the division ratio of the frequency divider is changed from N to N + 1 at t = 0, the input signal to the phase detector becomes

Thus, an increased step change of θ_i × (N + 1)^-1 appears at the reference input of the phase detector. When the reference signal of the step change Dθ_i is applied, the phase detector experiences an increased step change of reference signal Dθ_i. Thus, from a phase detector point of view, the step increase in the division ratio is the same as the reference signal step phase change.

The simulation result is shown in Figure 11.35. In that figure, because N0 = 4500, the start frequency is N0 × Fref = 4500 × 200 kHz = 900 MHz. Also, since N_Step = 400, the frequency shift is N_Step*Fref = 400 × 200 kHz = 80 MHz. Figure 11.35 shows the VCO frequency settled at the steady state frequency of 980 MHz, which shows that the step change is tracked. In addition, because the bandwidth of the loop filter is set to 10 kHz, the lock time is

From Figure 11.35, T_lock is found to closely predict the lock time of the PLL. Many ripples appear because the loop bandwidth is not sufficiently narrow compared with the comparison frequency.

• At the PLL’s steady state, the phase detector output voltage is constant and not time-varying. When the loop filter is above the second order, the phase detector output voltage is 0 at the steady state. This condition is used to find the VCO frequency at the steady state.

• Inside the loop bandwidth of the PLL, the phase noise of the VCO output follows that of the reference oscillator, while the phase noise of the VCO output as it is appears outside the loop bandwidth.

• Frequency dividers are used in a PLL to make the frequencies of the VCO and reference oscillator close; these frequencies are incident to the phase detector inputs. Frequency dividers are usually composed of a fixed divider and a programmable divider. Usually, the dual modulus counter is used as the fixed divider for consecutive dividing.

• Adding the accumulator to the divider composed of a dual modulus counter and a programmable divider, fractional dividing is possible and a fraction synthesizer can be constructed, which can reduce the in-band noise floor of the synthesizer.

• Phase detectors can be implemented using a DBM, Exclusive OR, and a phase-frequency detector (PFD). The phase detector characteristic of a PFD is linear and one-to-one for the phase difference 0–2p. When a charge pump circuit is added to the PFD, phase detector output becomes the current proportional to the phase difference, which makes for easy implementation of the loop filter that includes an ideal integrator.

• The loop filters can be designed using an open-loop gain. The second-order loop filter can be designed by setting ω_n to be equal to a loop bandwidth and damping ratio ζ = 0.707. The open-loop gain of the third-order loop filter shows a phase peak. The third-order loop filter can be designed by setting the phase peak frequency to be equal to the loop bandwidth and setting the loop gain at this frequency to be equal to 1

• The fourth- and higher-order loop filters can provide spur attenuation. A higher-order loop filter can be designed by optimization.

• PLL simulation in ADS is possible and the process for simulating the phase noise and lock time of the PLL is presented.

2. U. L. Rohde, Digital PLL Frequency Synthesizers: Theory and Design, Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.

3. D. Barberjee, PLL Performance, Simulation, and Design, 4th ed. Indianapolis, IN: Dog Ear Publishing, 2006.

11.2 Express the output phase noise, θ_o, of Figures 11.4(a) and 11.4(b) in terms of θ_i and θ_n.

11.3 Use Figure 11P.1 to solve the following problems:

(1) What is the phase noise at a 10-Hz offset frequency when a 10-MHz crystal oscillator is multiplied by 100? Compare this to the phase noise of 1-GHz DRO at a 10-Hz offset frequency.

(2) A 10-MHz crystal oscillator is used as the reference oscillator and it must phase lock at a 1-GHz DRVCO using a PLL. Obtain the optimum loop bandwidth BW. Then, plot the phase noise of the phase-locked DRVCO.

11.4 Use Figure 11P.2 to solve the following problems:

(1) From the figure, what is f_v when N = 124?

(2) Calculate the output frequency f_v when the frequency divider N is varied from 120–128.

11.5 Using Figure 11P.3, calculate the output frequency f_o.

11.6 Using Figure 11P.4, solve the following problems:

(1) From the figure, what is f_o?

(2) Calculate the output frequency when the frequency divider n varies from 160–660.

(3) Given the phase noise characteristics of the OCXO and VCXO that appear in Table 11P.1, determine the optimum bandwidth of the F2 loop filter.

11.7 Explain why the characteristics of the XOR phase detector are as shown in Figure 11.9.

11.8 Solve the following problems using Figure 11P.5:

(1) Given that the frequency of the VCO varies from 1.5 to 1.6 GHz when the tuning voltage is varied from 0 to 3 V, calculate the tuning sensitivity K_v in [rad/sec/V].

(2) Given that the PFD flows a current of 1.52 mA when the phase signal leads that of the reference signal, and conversely, that the PFD flows a current of -1.52 mA when the phase signal lags, as shown in Figure 11P.5, what is the phase detector constant K_d [A/rad]?

(3) For a reference oscillator with a frequency of 250 kHz, a PLL is built using the PFD in problem 11.8.2, above, the VCO with a frequency of 1.5 GHz from problem 11.8.1, above, and a frequency divider with a ratio N (N = 1500/0.25). Determine the open-loop gain of this PLL. Determine C₂ and R_2, shown in Figure 11P.6, to yield the bandwidth for the PLL of 10 kHz.

11.9 By referring to the spectrum analyzer’s manual and setting the SPAN to 0, explain the principles of measuring the time-varying power in an RBW.

11.10 For a given loop bandwidth ω_c and a phase margin φ, calculate the exact values of the fourth-order loop filter using the appropriate software. Confirm the results using a Bode plot.

11.11 (ADS Problem) Given that the loop bandwidth is 10 kHz, the phase margin is 45°, the comparison frequency is 200 kHz, and f_o = 900 MHz, after setting the phase detector constant for the tuning sensitivity of the VCO, as shown in Example 11.10, then calculate the element values of the second- and third-order loop filters and compare the loop gains.

11.12 (ADS Problem) In the simulation schematics shown in Figure 11.32, given that N0 = 4500, Fref = 200 kHz, and N_Step = 10, simulate the transient response after configuring the third-order loop filter with a loop bandwidth of 1 kHz.