11.1.1 Bidirectional AC–DC–AC Topologies

There are several configurations possible for three-phase to three-phase AC–DC–AC full-bridge converters, which can connect two AC systems. The most popular is a two-level converter, as shown in Figure 11.2(a), which is used mostly in low voltage and low-power or medium-power applications, for example, adjustable speed drives. On the other hand, three-level diode-clamped converters (DCCs) [11–12] and flying capacitor converters (FCCs) [4 6, 7] (Figure 11.2(b and c)) are becoming increasingly popular, but usually in the medium-voltage range for medium- and high-power applications [4], for example, marine propulsion, renewable energy conversion, rolling mills and railway traction. There are several advantages of multilevel converters, such as lower voltage stress of components, low current and voltage, total harmonic distortion factor and reduced volume of input passive filters. The main differences among the mentioned multilevel topologies are as follows [4]:

• DCC is the most popular topology and needs fewer capacitors. However, for higher voltage levels, it requires serially connected clamping diodes, which increases the losses and switching losses. In addition, for higher voltage levels, the DC capacitor voltage balancing cannot be achieved with classical modulations.
• FCC is less popular because it needs initialization of the FC voltage, and higher switching frequency is required (greater than 1.2 kHz, whereas for high-power applications the switching frequency is usually between 500 and 800 Hz) in high-power applications because of the FC limits, that is, capacitance versus volume.

Another group of AC–DC–AC converters are simplified topologies obtained by reducing the number of power electronic switches [8–10]. These attempts were based on the idea of replacing one of the semiconductor legs with a split capacitor bank and connecting a one-phase wire to its middle. In simplified topology, the lower number of switching devices, compared with that of a classical three-phase converter, corresponds to a reduced number of control channels and insulated-gate bipolar transistor (IGBT) driver circuits. Thus, connecting a three-phase AC system to a single-phase AC system is possible by using a single-standard three-leg integrated power module as the AC–DC–AC converter, as shown in Figure 11.3(a).

The same concept can be used to simplify an AC–DC–AC converter by connecting one three-phase system to another using only one additional leg, as is shown in Figure 11.3(b). Despite the advantages of these solutions, there is a necessity to develop new modulation techniques and to keep the DC voltage significantly high in order to maintain all nominal phase-to-phase converter voltages, which places higher voltage stress on the converter semiconductor devices.

This problem can be solved by application of a three-level DCC. When this technology was emerging in industry, not a single integrated power module product for three-level devices was available. Today, manufacturers are selling easy-to-use integrated half-bridge power modules with clamping diodes. New compact devices make it easier to improve the topology with a split capacitor in the DC-link. Thus, the improved topology of a simplified AC–DC–AC converter is shown in Figure 11.4, for applications of three-phase to single-phase, as well as for three-phase to three-phase systems. The first topology is dedicated only to low-power applications, whereas the second is devoted to low- and medium-power applications.

The simplified three-level DCC has several advantages compared with that of a simplified two-level topology [13]: reduction of machine torque pulsations (mechanical stress in cases where generator/motor application is decreased), additional zero vectors, and reduction in size of passive filters on the AC side.

11.1.2 Passive Components Design for an AC–DC–AC Converter

This section is devoted to the methods of passive components of an AC–DC–AC converter design. Among them, there are input filters (L or LCL), DC-link capacitors, and flying capacitors (FCs), which have a significant impact on the size, weight and final price of the AC–DC–AC converter.

11.1.3 DC-Link Capacitor Rating

In the literature, many design procedures [17–20] for DC-link capacitors are presented, where the minimum capacitance value is designed to limit the DC-link voltage ripple at a specified level. With the assumption of a balanced three-phase system and of ideal power electronics switches, the DC capacitor current can be expressed as:

11.1

where is the capacitance of a DC capacitor, is the DC voltage, is the DC current, is the load DC current, are letters of AC circuit phase, and are the AC circuit phase instantaneous current and switching states at the appropriate phases, respectively, and is the load active power in DC. The selected approach of the calculation of the DC capacitors is focused on the following constraints:

• The voltage ripple, because of the high-frequency components of the modulated DC currents of both AC–DC and DC–AC converters, has to remain within desired limits,
• The capacitor energy has to sustain the output power demand for a period equal to the time delay of the DC voltage control loop.

The final constraint determines the capacitor value. By assuming that is a time delay of the DC voltage control loop, and that is a variation of the maximal load power, the energy exchanged by the DC capacitor can be estimated as:

11.2

Where is the sum of small time constant. From this equation, the maximal DC voltage variation during maximum power change is proportional to energy change:

11.3

where is the considered maximum DC voltage change within the transient load and is the minimum DC capacitance. Taking into account the maximal voltage variation and by rearranging Equation (11.3), the minimal capacitance can be calculated as [20]:

11.4

The minimum DC capacitance value in an AC–DC–AC converter with respect to different nominal powers is presented in Figure 11.5. Therefore, it can be assumed that for given nominal power, the DC capacitance depends mainly on the switching pattern of the AC–DC converters and on the quality (accuracy and dynamics) of the applied control method for the AC–DC–AC converter, that is, for a shorter sampling time , the DC capacitance would be lower because the DC voltage regulation accuracy is improved. However, it should be noted that the switching frequency is limited by the switching losses of the power electronics devices applied in the AC–DC–AC converter.

11.1.4 Flying Capacitor Rating

FC capacitance, assuming sinusoidal converter output voltages and currents, can be calculated as [21]:

11.5

where is the RMS phase current flowing through the FC, is the assumed maximum voltage ripple across the FC and is the frequency of changes of the switching states (charging and discharging) applied to the FCC, which are used for FC balancing. It is important to note that is not the same as the switching frequency, because the frequency of changes of the switching states applied to FCC depends on the type of modulation and, in the case of FC balancing, is typically a multiple of the switching frequency by a factor 0.5, 1 or 2.

11.1.5 L and LCL Filter Rating

An AC–DC–AC converter is connected to the grid through an AC filter (e.g., L or LCL). The inductance allows current control by the voltage drop on itself. In order to obtain better reduction of current ripples, the LCL T-type filter has been introduced.

For the LCL filter to fulfill the grid codes, or recommended practices for example, IEEE 519-1992 [21 22] a variety of optimization criteria exist, such as minimum costs, losses, volume, weight, or design. However, it is a complex task because many parameters influence this process, for example, DC-link voltage level, phase current, modulation method, modulation index, switching frequency, fundamental frequency, and resonance frequency. Therefore, the design can be done using two different methods:

• simple trial-and-error method, which has to be supported by simulation to prove that the grid codes are fulfilled (simulation has to take into account all elements of the system),
• complicated iterative, which calculates directly the filter parameters fulfilling the grid code; however, detailed information is required regarding many parameters, for example, modulation method and modulation index [24 25].

A general algorithm of a simple trial-and-error filter design is presented in Figure 11.6. The starting point for the design procedure is usually assumptions of the converter's rated power, grid, and switching frequencies. Those parameters allow the calculation of base values (base impedance , capacitance and inductance ):

11.6

11.7

where is the line-to-line grid voltage and is the grid voltage pulsation.

The first step is the design of the filter inductance. This should be designed carefully because a large inductance value may, by itself, attenuate higher frequencies and limit current ripples. On the other hand, it brings many disadvantages, such as greater inductor size, a decrease in the converter's dynamics and a smaller range of operation. The operation range is limited through the maximum reachable voltage drop across the inductance. It is dependent indirectly on the DC-link voltage. Thus, in order to achieve a large current through the inductance, a high DC-link voltage level or low input inductance is needed.

The maximum total inductance of the input LCL filter may not be larger than [14]:

11.8

where is the grid maximum voltage value and is the grid current maximum value.

In addition, the total value of the LCL filter inductance should be lower than 5% of the base impedance value, in order to limit the voltage drop during normal operation and to achieve excellent dynamics and reasonable cost [14 26]. Based on the IEEE 519-1992 limitations and the assumption that peak ripples must not exceed 10% of the grid current, the converter-side inductance can be calculated, as shown in Figure 11.6 [14 23]. Typically, the converter-side inductance is larger than the grid-side inductance in order to attenuate most of the current ripple. In this case, a split factor , given by Liserre et al. [26]:

11.9

is set by the desirable ripple attenuation described as:

11.10

where is the grid higher harmonics current and is the converter higher harmonics current.

In order to limit the harmonic currents absorbed by the filter, the capacitor is limited to 5% of the reactive power absorbed at rated conditions (base capacitance) [26]. Therefore, the final capacitance of the LCL filter (Y-connected) cannot be larger than as presented in Figure 11.6. In the case of just an filter, the value of the inductance can equal .

Another constraint in the design process of the LCL filter is an obligation to maintain the resonance frequency between 10 times the line frequency and one-half of the switching frequency [14 26]. These limits guarantee that there will be no resonance problems in both the lower and higher parts of the harmonic spectrum. The actual resonance frequency of the LCL filter may be calculated as in Figure 11.6.

11.1.6 Comparison

Table 11.1 presents a comparison of selected classical AC–DC–AC converter topologies: two-level three-phase/three-phase converter (2L-3/3); three-level three-phase/three-phase DCC converter (3L-DCC-3/3); three-level three-phase/three-phase FCC converter (3L-FCC-3/3), and simplified topologies with reduced number of transistors: simplified AC–DC–AC two-level converter three-phase/one-phase (S2L-3/1), and three-phase/three-phase (S2L-3/3); simplified DCC AC–DC–AC converter three-phase/one-phase (S3L-DCC 3/1), and three-phase/three-phase (S3L-DCC 3/3).

	I	II	III	IV	V	VI	VII
2L-3/3	12	0/1		1	1
S2L-3/3	8	0/2
S2L-3/1	6	0/2
3L-DCC-3/3	24	12/2		1
S3L-DCC 3/3	16	8/2
S3L-DCC 3/1	12	6/2
3L-FCC-3/3	24	0/7b

^aSimplified converter only between transistors legs.

^bIncluding one standard electrolytic capacitor in DC link and six floating capacitors designed for rapid discharging.

I, Total number of IGBT transistors; II, Number of independent diodes/number of capacitors; III, Total number of converter states; IV, DC voltage level in p.u. in comparison to 2L-3/3; V, Blocking voltage for transistors in p.u. in comparison to 2L-3/3; VI, Minimum voltage level step change; VII, total L filter inductance for all phases.

11.2.1 Space Vector Modulation for Classical Three-Phase Two-Level Converter

Table 11.2 presents all possible switching states for a single leg of a two-level VSC (see Figure 11.2(a), generating output pole voltage between the phase terminal and the DC-link “” terminal , where is the leg indicator.

Because the three-phase system is assumed symmetric, the Clarke transformation from natural into a stationary coordinate system can be used. Figure 11.7(a) shows a graphical representation of the SV voltage plane with possible output voltage vectors of the three-phase two-level converter. All voltage vectors are described by three numbers, which correspond to the switching states in leg , leg , and leg , respectively. A three-phase two-level converter provides eight possible switching states, comprising six active (, , , , , and ) and two zero switching states ( and ). The active vectors divide the plane into six sectors, where reference vector is obtained by switching on (for proper time) two adjacent vectors. It can be seen that vector (see Figure 11.7(b)) can be implemented by the different ON/OFF switch sequences of and , and that zero vectors and decrease the modulation index.

Reference vector , used to solve equations that describe times , , , and , is sampled with fixed sampling frequency . Digital implementation is described with the help of a simple trigonometric relationship for the first sector (11.14):

11.14

and is recalculated for the following sectors (from 2 to 6). After the and calculation, the residual sampling time is reserved for zero vectors and with condition . Equation (11.14) is identical for all variants of SVM. The only difference is in the different placement of zero vectors and . This gives different equations defining and for each method, but the total duration time of the zero vectors must fulfill the following conditions:

11.15

The most popular SVM method is modulation with symmetrical zero states' space vector PWM (SVPWM) where:

11.16

Figure 11.8 shows gate pulses for and the correlation between time , , and the duration of vectors , , , and . For the first sector, commutation delay can be computed as:

11.17

For classical SVM, times , , and are computed for one sector only. Commutation delay for the other sectors can be calculated with the help of a matrix:

11.18

11.19

11.2.2 Space Vector Modulation for Classical Three-Phase Three-Level Converter

Tables 11.3 and 11.4 present all possible switching states for the single leg of a three-level DCC and FCC (see Figure 11.2(b and c)), respectively, generating output pole voltage between the phase terminal and the DC-link “” terminal , where is the leg indicator.

States
	OFF	OFF
	OFF	ON
	ON	ON

States
		OFF	OFF
	A	ON	OFF
	B	OFF	ON
		ON	ON

Figure 11.9 shows a graphical representation of the SV voltage plane with possible output voltage vectors of the three-phase three-level converter, which is constructed from the main switching states: , , and .

For the three-phase three-level VSC, the 27 voltage vectors can be specified as follows: three zero vectors (, , and ); 12 internal small-amplitude vectors (, , , , , , , , , , , and ); six middle medium-amplitude vectors (, , , , , and ); six external large-amplitude vectors (, , , , , and ).

The external vectors divide the vector plane into six sectors (see Figure 11.9), which is similar to the two-level VSC. However, for the three-level VSC, each sector is divided into four triangular regions. Figure 11.10(a and b) shows that the first sector is divided into four regions with all possible switching states for the DCC and the FCC topologies, respectively. As FCC switching state 1 can be divided into two redundant switching states: and (see Table 11.4, highlighted in Figure 11.10(b)), for this topology, the number of possible switching states increases to 64.

Conventional SVM for multilevel VSC is based on the assumption that for the generation of reference vector all possible nearest vectors, including their redundant states, are used (, , and in the first; , , and in the second; , , and in the third; and finally, , , and in the fourth region) with symmetrical placement of the zero and internal vectors.

The calculation of the region number of the location of the reference vector and switching times is based on two additional factors called the small modulation indices (, ). Index and are the projection of the reference vector on the sector sides, limited by the external vectors (see Figure 11.10). According to the trigonometric dependence, the small modulation indices are calculated as follows:

11.20

In each sector, calculations are carried out to achieve vector switching times that are the same and where the difference is only in the power switch selection for the gating signal. Thus, the reference vector is normalized to the first sector and after evaluation of the vector switching times, a proper transistor switching sequence is created for the reference position. Table 11.5 presents the calculation of the region number and switching times with respect to and .

Conditions	Region	Switching times
	First	, ,
, ,	Second	, , ,
	Third	, , ,
, ,	Fourth	, , ,

11.3.1 Flying Capacitors Voltage Balancing in Flying Capacitor Converter

Proper operation of the FCC requires that the FC voltage should be half that of the DC-link voltage. With this condition, switching state 1 can be divided into two redundant states: 1A and 1B (highlighted in Table 11.4, Figure 11.10(b)), which generate the same output voltage . As the output voltage does not depend on the type of selected state, either 1A or 1B can be used for independent control of . However, to decrease the number of commutations, only one state for each phase is chosen in the sampling period. For proper FC voltage balancing, only information about the sign of the phase current flowing through the FC is needed. Table 11.8 shows the selection between redundant states 1A or 1B based on the sign of phase current .

Conditions

Figures 11.12 and 11.13 present the switching sequence in all regions in sector 1 for different switching states 1A or 1B for all phases, respectively. When the selected redundant state 1A or 1B is changed, the next modulation period can contain additional switching between sampling periods: two in the second and four in the first, third, and fourth regions. These additional switching can damage the converter; all switches are changing their state, which can generate overvoltage. To eliminate this phenomenon and to provide better switching distribution between particular switches, a modification of the switching pattern should be introduced [6] (see Figure 11.14).

11.3.2 Pulse-Width Modulation for Simplified AC–DC–AC Topologies

Modulation for simplified AC–DC–AC converters is also realized separately for the DC–AC and AC–DC stages. It can be considered in this case as a single-phase modulation for the DC–AC part, as shown in Figures 11.3(a) and 11.4(a), or as three-phase modulation for the DC–AC or AC–DC parts, as shown in Figures 11.3(b) and 11.4(b).

Single-phase modulation for two-level DC–AC converters is simple and is described by Equation (11.25). Slightly more complicated is the modulation for a single-phase three-level DC–AC converter [13] shown in Figure 11.4(b), because an additional zero state is included (Figure 11.15).

11.25

It can be utilized using a universal concept of time-domain duty-cycle computation technique (11.26) for single-phase multilevel converters, described as a one-dimensional modulation (1DM) technique and presented in Ref. [34].

11.26

Modulation for a simplified three-phase converter requires a different approach than a classical topology, because only two reference signals in the coordinate system are needed to obtain a balanced three-phase voltage output, which implies that a higher voltage must be supplied to the DC-link to maintain the reference voltage vector in the linear modulation area (Figure 11.16).

SVM for a simplified converter is based on a modified transformation from to [35]:

11.27

Figure 11.17 shows two cases of a graphical representation of a SV voltage plane with four achievable voltage vectors of the three-phase two-level simplified converter shown in Figure 11.3(b). In the first case (Figure 11.17(a)), all active vectors (, , , ) divide the plane in four sectors: sector I (), sector II (), sector III (), and finally, sector IV (). The reference voltage vector , like in classical converters, could be obtained by switching two adjacent vectors, but this causes a voltage imbalance on DC-link capacitors. For the first sector, switching times can be computed as:

11.28

The issue of voltage imbalance on DC-link capacitors can be solved by different divisions of the plane (Figure 11.17(b)). The number of sectors does not change, but the sectors are shifted 45° (e.g., sector I ), which gives more vectors forming (e.g., in sector I). For the first sector, switching state times can be computed as [10]:

11.29

Switching signals for a simplified three-phase, 2-level AC–DC or DC–AC converter (Fig. 11.3(b)) are shown in Fig. 11.18.

Another simplified three-phase converter is the three-level converter, as shown in Figure 11.4(b). A graphical representation of the nine achievable voltage vectors in the voltage plane for such a converter is shown in Figure 11.19.

Eight of them (, , , , , , , ) are active and there is a zero vector (). The reference voltage vector , like in classical converters, could be obtained by switching two adjacent vectors with the use of the zero voltage vector in the middle of the switching period [12]. Switching times for the sector I () can be computed as:

11.30

and switching sequences for each of the eight sectors are shown in Figure 11.20.

11.3.3 Compensation of Semiconductor Voltage Drop and Dead-Time Effect

The voltage drop on semiconductor devices and the dead-time (between pairs of IGBT's) value distorts the phase current. In both cases, it is the result of increased or decreased amplitude (length) of the reference SV, depending on the sign of the phase current, respectively. To avoid that, the voltage drop and the dead-time effect compensation algorithms are used. The impact of voltage drop and dead-time effect of semiconductor devices on phase current distortion have been well investigated for the classical two-level and multilevel converters. These methods can be divided into two groups:

• modification of amplitude (length) of the reference SV [6 36–38],
• modification of the duty cycles at the output of the modulator [6 36, 38–40].

The solution is slightly more complicated in the case of simplified topologies. Because these converters use transistors in only two of three phases, the impact of voltage drop and dead-time effect of semiconductor devices is more significant, compared with that of classical topologies, owing to the different lengths of individual vectors. Moreover, these issues in reduced topologies cannot be considered as a mature. Therefore, in the following section, only reduced topologies will be considered.

Currents for ideal models of controlled switches and models including voltage drop on semiconductor devices are shown in Figure 11.21. In the other case, the converter currents are distorted significantly.

The effects of voltage drop on semiconductor devices are compensated by adding a correction to the reference signals on the input of the modulator [41]. In order to estimate the values of the voltage drops, the phase currents should be predicted for the next switching instant. Values of the predicted current in and phases are given by:

11.31

where is the value of the current in the present sample and is the value of the current in the earlier sample. Predicted current values are compared with values calculated from transistor and diode data sheets to determine the state of elements in both phases and corresponding voltage drops:

11.32

where and are the currents for the transistor and diode, respectively. denotes the voltage drop on the transistor CE junction, denotes the voltage drop on the diode, and are the conductances of the transistor and diode for conduction operation mode, respectively, and are conductances of the transistor and diode for blocking operation mode, respectively, and finally, and are the resulting voltage drop for the transistor and diode, respectively.

Using and transformed to the two-phase coordinate system, as in Equation (11.27), a mean value of voltage drop per sampling period is estimated. Assuming that at switching state 1, the phase voltage error is (single transistor and a single DCC diode in a branch are conducting) and in the remaining states, it is or we can write

11.33

the duty cycles for zero states. Therefore, the correcting signals for voltage drop compensation for a leg (and similar b leg ) are:

11.34

where denotes the direction of phase current flow, and are the duty cycles for positive and negative voltage output states and denotes zero voltage. These voltage-correcting signals are transformed to the coordinate system by using the modified transform from Equation (11.27) and adding them to the reference voltages for the modulator. Currents with no compensation and with the applied compensation method for semiconductor voltage drop only are shown in Figure 11.22.

Another necessary compensation relates to the influence of the so-called dead time. Because IGBT devices turn off much more slowly than they turn on, there is a need for the introduction of a delay in control signals between complementary switching devices to prevent short-circuiting the DC-link. This effect is more visible for a low modulation index and low-frequency operation [41]. Figure 11.23 shows a comparison of phase currents without and with dead time included between complementary switching devices.

Correcting signals for limiting the effect of dead time are calculated based on current sign and saturation level ; usually chosen experimentally to take into consideration the noise near the current zero-crossing. If phase current polarity, which depends on the measurement noise level as well as on the control delays, is not calculated properly, inadequate compensation can worsen the shape of the phase current. Therefore, in the range of the dead-time correction value should be limited linearly. An example of a limiting function, modeled by two linear functions marked as 1 and 2, is shown in Figure 11.24.

Because a reduced converter generates voltages that are not equal in length in vector representation (Figure 11.19), after obtaining the above correction, it is necessary to choose which switching combination should not only be increased or decreased, but also multiplied with a scaling constant. For long vectors ( and for the two-level converter and and for the three-level converter), the scaling constant is equal to , but for short vectors ( and for two-level converter , , , , _, and for three-level converter), the scaling constant is equal to . The effect of compensation for converters without and with dead-time compensation between the complementary switching devices is shown in Figure 11.25. As can be seen, the shape of phase currents and is improved mainly near the zero-crossing.

11.4.1 Field-Oriented Control of an AC–DC Machine-Side Converter

The FOC can be divided into direct field-oriented control (DFOC) and indirect field-oriented control (IFOC). A simplified block diagram of the IFOC is presented in Figure 11.27. The IFOC seems to be more convenient than DFOC, especially for permanent magnet synchronous machines (PMSMs) because flux estimation is not necessary. The IFOC needs the coordinate system to rotate synchronously with the rotor flux angular speed . In this case, the system of coordinates is oriented with the rotor flux linkage component, such that:

11.35

All variables are transformed from the natural into rotating the reference frame. Then, the referenced stator current values and are compared with the actual values of stator current component and , respectively. It should be stressed that (for steady state) is equal to the magnetizing current, whereas the torque state, both dynamic and steady, is proportional to . The current errors and are fed to two PI controllers, which generate referenced stator voltage components and , respectively. Furthermore, referenced voltages are transformed from rotating coordinates into the stationary coordinates system by using the rotor flux vector position angle . Therefore, the obtained referenced voltage vector is delivered to SVM, which generates the appropriate switching signals .

It should be taken into account that and are coupled with each other. Any change of stator voltage component has an influence not only for d but also for the q current component (the same applies to the q component). Therefore, a decoupling network (DN) in the control loops is necessary. The solution for this phenomenon is presented in Figure 11.28. It should be noted that the decoupling between the d and q axes appears in all control methods, discussed in this chapter, for both GCs and MCs (VOC and FOC). In the case of direct torque control and direct power control, the SV modulated by the coupling phenomenon is reduced significantly and therefore, DN can be omitted.

11.4.2 Stator Current Controller Design

The model is very convenient to use for the synthesis and analysis of current controllers for MC. In the case of FOC, an asynchronous machine can be approximated and treated as a DC machine [48 51]. However, it should be pointed out that presence of coupling requires an application of a DN, as presented in Figure 11.28.

Hence, it can be seen that referenced decoupled machine converter voltages should be generated (after simplification) as follows:

11.36

11.37

where , and , is the total leakage factor, is the stator windings self-inductance, and are the stator and rotor windings resistances, respectively.

It simplifies the analysis and enables the derivation of analytical expressions for the parameters of stator current controllers. The control structure will operate in a discontinuous domain (digital implementation); therefore, it is necessary to take into account the sampling period . This could be done by S&H block. Moreover, the statistical delay of the PWM in VSC should be taken into account. In the literature [6 16, 47 50, 51], the delay of the PWM is approximated from 0 to 2 sampling times . Furthermore, is the VSC gain, and is the dead time of the VSC ( for an ideal converter). The block S&H and VSC sum of their time constants is expressed by:

11.38

Therefore, the model of the stator current control loop can be approximated as in Figure 11.29.

Please note that is the sum of small time constants, is a large time constant, and is a gain approximation of the stator windings. Hence, gives a dominant pole. Among several methods of analysis, there are two simple ways for the design of the controller parameters: modulus optimum (MO) and symmetry optimum (SO) [48]. With the assumption that the internal voltage induced in the machine winding (EMF) is , for the circuit presented in Figure 11.29, the proportional gain and integral time constant of the PI current controller can be derived as [48 51]

11.39

11.40

After simplifications, the closed-loop transfer function of the VSC can be approximated by the first-order transfer function as:

11.41

11.4.3 Direct Torque Control with Space Vector Modulation

To avoid the drawbacks of the switching table in classical DTC, instead of hysteresis controllers and the switching table, PI controllers with the SVM block have been introduced, as in IFOC. Therefore, DTC with SVM (DTC-SVM) joins DTC and IFOC features in one control structure, as shown in Figure 11.30.

DTC-SVM requires that the coordinate system rotates synchronously with the stator flux angular speed . In this case, the coordinate system is oriented with the stator flux linkage component, such that

11.42

Based on actual stator currents , DC voltage , mechanical angular speed , and switching signals , the commanded electromagnetic torque is delivered from the outer PI speed controller (Figure 11.30). Then, and the commanded stator flux amplitudes are compared with the estimated values of electromagnetic torque and stator flux . The torque and stator flux errors are fed to the PI controllers. The output signals are the referenced stator voltage components and , respectively.

Furthermore, voltage components in the rotating system of coordinates are transformed into stationary coordinates by using stator flux position angle. The obtained referenced stator voltage SV is delivered to the SVM, which generates the desired switching signals for the MC.

11.4.4 Machine Stator Flux Controller Design

Figure 11.31 presents a block diagram of the PI-based stator flux magnitude control loop with neglected voltage drop on the stator resistance [47]. However, the delay introduced by the inverter is taken into consideration.

According to the SO criterion [48 49], the plant transfer function can be written as:

11.43

Therefore, according to the SO design technique, the stator flux PI controller parameters: proportional gain and the integral time constant can be calculated as [47 48]

11.44

11.45

11.4.5 Machine Electromagnetic Torque Controller Design

Figure 11.32 presents a block diagram of the simplified PI-based torque control loop with omitted coupling between the torque and stator flux. Consequently, the torque control loop is very simple Thus, for this model, not one criterion can be applied.

In this case, according to Ref. [47], the simple (practical) way to design the torque PI controller can be used. Starting from initial values, for example, proportional gain and an integral time constant , the value of increases cyclically. From these tests, the best value of for fast torque response without oscillation and defined overshoot can be selected.

11.4.6 Machine Angular Speed Controller Design

If the magnitude of the stator flux is constant, , the dynamics of the IM can be described as follows:

11.46

where is the moment of inertia and is the load torque.

Accordingly, Figure 11.33 shows a block diagram of the PI-based speed control loop, where is the transfer function of the closed torque control loop with prefilter (to compensate the forcing element in the transfer function of the closed torque control loop).

Approximating the torque control loop by the first-order integral part [47], the simplified transfer function can be written as:

11.47

where:

11.48

and:

11.49

where is the machine pole pairs number, is the phase number, is the total leakage factor, is the stator windings self-inductance, is the main magnetizing inductance, is the rotor windings self-inductance, and are the stator and rotor windings resistances, respectively.

According to the SO criterion [48 49], the plant transfer function can be written as:

11.50

where is the gain of the plant and is the sum of small time constants and filters:

11.51

The speed PI controller parameters: proportional gain , and the integral time constant , can be calculated as [47 48]

11.52

11.53

11.4.7 Voltage-Oriented Control of an AC–DC Grid-Side Converter

The VOC presented in Figure 11.34 guarantees high dynamic and static performance via an internal current control loop. It has become very popular and, consequently, it has been developed and improved [15 53–55]. The goal of the control system is to maintain the DC-link voltage , at the required level, while currents drawn from the power system should be sinusoidal and in phase with the line voltage in order to satisfy the unity power factor (UPF) condition. The UPF condition is fulfilled when the line current vector is aligned with the phase voltage vector of the grid.

For the UPF condition, the commanded value of the reactive component grid current vector is set to zero. The reference value of is an active component of the grid current vector. After comparing commanded currents with actual values, the errors are delivered to the PI current controllers. Voltages generated by the controllers are transformed to coordinates by using the grid voltage vector position angle . Switching signals for the GC are generated by an SVM.

11.4.8 Line Current Controllers of an AC–DC Grid-Side Converter

The model is very convenient to use for the synthesis and analysis of the current controllers for a grid-connected converter. However, the presence of coupling requires an application of a DN (as with FOC in Figure 11.28), as presented in Figure 11.35.

Hence, it can be seen clearly that referenced decoupled GC voltages should be generated as follows:

11.54

11.55

Therefore, the model of the current control loop can be presented as in Figure 11.36.

Please note that is the sum of small time constants, is a large time constant, and is a gain of input choke. Hence, gives a dominant pole. Between several methods of analysis, there are two simple ways for the design of the controller parameters: MO and SO [48]. With the assumption that disturbance for the circuit presented in Figure 11.5, the proportional gain and integral time constant of the PI current controller can be derived as [16]

11.56

11.57

After simplifications, the closed-loop transfer function of the VSC can be approximated by the first-order transfer function as:

11.58

For comparison, the parameters of the PI current controller calculated based on MO differ only in integral time constant:

11.59

The VSC with current controllers designed by MO can be approximated as:

11.60

For more information, please refer to Refs. [16 53].

11.4.9 Direct Power Control with Space Vector Modulation of an AC–DC Grid-Side Converter

Direct power control with space vector modulation (DPC-SVM) [52] assures high dynamic and static performance via internal power control loops. Instead of line currents, the active and reactive powers are used as control variables (Figure 11.37). The command active power is generated by the outer DC-link voltage controller, whereas command reactive power is set to zero for UPF operation. These values are compared with the estimated and values, respectively [15 16]. Calculated errors and are delivered to the PI power controllers. Voltages generated by the power controllers are DC quantities, which eliminates steady-state error, as in VOC. Then, after transformation to stationary coordinates [16], the voltages are used for the generation of switching signals in the SVM block.

11.4.10 Line Power Controllers of an AC–DC Grid-Side Converter

The assumptions are the same as for the design of current controllers in VOC. Because the same block diagram can be applied to both and power controllers, only the active power control loop will be described briefly (Figure 11.38).

As in the case of VOC, SO is chosen because of its good response to a disturbance step change. With the assumption that , an open- and closed-loop transfer function can be obtained easily [16]. The proportional gain and integral time constant of the PI current controller in DPC-SVM can be calculated as:

11.61

11.62

The PI controller with such parameters gives power-tracking performance with approximately 40% overshoot. Therefore, for decreasing the overshoot, a first-order prefilter can be used on the reference signal:

11.63

where usually equals a few [48].

In further investigation, a time delay of the prefilter is set to . Finally, a closed control loop of the VSC can be approximated by a first-order transfer function as:

11.64

11.4.11 DC-Link Voltage Controller for an AC–DC Converter

For calculation of the parameters of a DC-link voltage controller, the inner current or power control loop can be modeled with the first-order transfer function [16]. Therefore, the power control loop of a grid-connected converter can be approximated by further consideration of the first-order block with an equivalent time constant as:

11.65

where for inner current or power controllers designed by MO or for current/power controllers designed by SO criterion. Therefore, the DC-link voltage control loop can be modeled as in Figure 11.39.

For the sake of simplicity, it can be assumed that

11.66

where is the DC voltage filter time constant, is a sum of time constants, and is an equivalent integration time constant. Hence, the proportional gain and integral time constant of the DC-link voltage controller can be derived from

11.67

11.68

11.5.1 Analysis of the Power Response Time Constant of an AC–DC–AC Converter

Based on Equation (11.58), the time constant of the GC response is determined. With the assumption that power losses of the converters can be neglected, the power-tracking performance can be expressed by

11.75

Similarly, for the MC, it can be written as

11.76

where is the equivalent time constant of the MC step response.

11.5.2 Energy of the DC-Link Capacitor

The DC-link voltage can be described as

11.77

So,

11.78

Assuming the initial condition is in steady state, the actual DC-link voltage is equal to the commanded DC-link voltage . Therefore, Equation (11.78) can be rewritten as

11.79

where . Therefore, we can obtain

11.80

If the power losses of the GC and MC are neglected (for simplicity), the energy storage variation of the DC-link capacitor will be the integral of the difference between the GC power and the MC power . Therefore, it can be written as

11.81

From this equation, it can be concluded that for the most accurate control of the GC power , the commanded power is

11.82

where describes the power of the DC-link voltage feedback control loop and is equal to the instantaneous APFF signal. After the necessary assumptions, we obtain [16]:

11.83

From Equations (11.75) and (11.76), the open-loop transfer function of the grid and machine converter active powers can be expressed as

11.84

11.85

Based on these equations, the analytic model of the AC–DC–AC converter with APFF can be defined, as in Figure 11.41. Such a system can be described by an open-loop transfer function as

11.86

Assuming initial steady-state operation, and , the transfer function of the AC–DC–AC converter drive can be derived.

The active power of the machine converter can be calculated from the commanded values of the stator voltages and actual stator current. Assuming the case where , theoretically, the DC-link voltage should not be affected by the change of the load power. However, in the real system, the unbalanced power difference that causes the fluctuations of the DC-link voltage occurs mainly because of the power estimation error, the moment of inertia of the rotor and low-pass filter in the speed control loop, and the saturation of the commanded control variable.

In Figure 11.42, waveforms illustrate the operation with a torque control loop. Torque reversal is applied when the mechanical speed reaches ±71% of the nominal speed. Very good stabilization of DC voltage can be seen with the use of APFF. The selected control method for the AC–DC–AC converter was direct power and torque control with space vector modulations (DPTC-SVM) [16]. The important advantage of this method is that there is no need to rescale the APFF signal.

Moreover, based on Figure 11.42, it can be concluded that for ideal control methods with sufficiently high sampling time, the DC voltage fluctuation during transient for reduced capacitors could be even smaller than for the higher value of capacitance without APFF. Moreover, for the circuit with APFF, it can be seen that the fluctuations of DC voltage during transient for C = 1 p.u. and for C = 0.1 p.u. are almost equal for higher sampling times. Based on this, it can be stated that stabilization of the DC voltage in an AC–DC–AC converter with a controllable GC depends mainly on the quality (control loops accuracy and bandwidths) of the used DC voltage, the grid, and the MC power flow control methods. It can be expected that for high switching frequency, for example, 20 kHz, easily available for silicon carbide devices in wider power ranges than in the case of silicon devices, very accurate power flow control will be obtained. A simulation of DC voltage control accuracy in a simplified model (no switching losses) is presented as a function of sampling = switching frequency up to 100 kHz (Figure 11.43) with the DPTC-SVM control method applied [16].