23.2.1 Parallel-Connected H-Bridge Converter (H-BC)

Figure 23.1 shows a single-phase parallel-connected H-BC with a common DC-link fed from the transformer with two low-voltage windings [10–14]. Among the main advantages of this topology are:

• low harmonics distortion of current for transformer high-voltage side at the hybrid and the unipolar modulations,
• high reliability – in the case of one module failure, the H-BC still works with the same amplitude of but at twice reduced power and with an increased THD factor of .

Despite the obvious advantages introduced by parallel connection of the VSC, this is also a major disadvantage because of:

• the high cost, weight and size of a step-down transformer with two secondary windings,
• the increased current and voltage rating of the semiconductor devices.

Each module of the converter shown in Figure 23.1 has two legs, with insulated gate bipolar transistors (IGBTs) denoted and , where is the negation of and is the leg indication: or . The IGBT is switched ON when the gate signal is and switched OFF when the gate signal is . All switching states for one module are shown in Table 23.1.

Switch number	Levels of output t voltage
	0	0	1	1
	1	0	1	0

To calculate the duration of the switching states, the modulation index is indispensable, which is the proportion of the control algorithm reference with respect to the DC-link voltage :

23.1

where is the reference amplitude of the converter output voltage_. Note that cannot be greater than ; thus, .

The decision as to which output voltage level is applied (positive or negative) depends on (Equation 23.1):

23.2

The switching state time durations for every level are assigned as follows: for and for , and are calculated as:

23.3

23.4

The IGBT state and its time duration depends on the PWM technique applied: the HPWM or UPWM.

The HPWM [22–24] for the single H-BC module is based on the assumption that only two among four transistors are pulse-width modulated in each sampling period (Figure 23.2). This means that in each period, only one leg is modulated and – as a consequence – only one of two possible redundant states for the voltage level is used. Switching states are applied symmetrically with respect to the middle of the sampling period. Which leg is modulated depends on the sign of :

23.5

The HPWM applies two switching states in each sampling period for a single H-BC, which gives three output voltage forming states for module 1 (Figure 23.2(a)) and module 2 (Figure 23.2(b)). For two parallel-connected H-BC modules, the interleaved modulation is applied, which means that for each the same switching pattern and duty cycles of the HPWM can be used, but the sampling periods are shifted ½ between modules. Interleave modulation gives five levels on the transformer high-voltage side: , , and five output voltage forming states (Figure 23.2(c)).

The other technique, UPWM [22 24], for the single H-BC module is based on the assumption that all switches are modulated in every sampling period (Figure 23.3). As a result, two redundant states for zero voltage level are applied. Thus, the UPWM applies three switching states in each sampling period for the single H-BC, which gives five output voltage forming states for module 1 (Figure 23.3(a)) and module 2 (Figure 23.3(b)). For the parallel-connected H-BC, interleaved modulation is applied, which means the same switching pattern and duty cycles of the UPWM can be used, but the sampling periods are shifted ¼ between modules_. Interleave modulation gives five levels on the transformer high-voltage side: , , , and nine output voltage forming states (Figure 23.3(c)).

23.2.2 H-Diode Clamped Converter (H-DCC)

The DCC was proposed in 1981 by Nabae et al. [25]. Figure 23.4 presents the single-phase H-DCC [18–21], which has two legs, with IGBTs denoted , , and , where and are the negation of _and , respectively and _x is the leg indication: a or b. Two clamping diodes and are parallel connected to and for each leg, and the clamping point is connected to the center of the series capacitors and in the DC-link. Clamping diodes conduct the current during the generation of the intermediate H-DCC voltage levels.

Three different switching states generating three different output pole voltages can be distinguished for the single leg:

• , when and are turned OFF (output pole voltage equals ),
• , when is turned OFF and is turned ON (output pole voltage equals ½, leg is clamped by and diodes),
• , when and are turned ON (output pole voltage equals ).

The single-phase H-DCC gives nine possible switching states, allowing five levels of output voltage to be obtained: three redundant for , two redundant for whichever and one for whichever . The output voltage level depends on M (Equation 23.1):

23.6

All possible switching states for the H-DCC are shown in Table 23.2. For every level, the switching state duration times are assigned as follows:

• for ,
• for ,
• for ,

Switch number	Levels of output voltage
							½
	0	0	0	0	0	1	1	0	1
	0	1	0	0	1	1	1	1	1
	1	1	0	0	0	1	0	0	0
	1	1	1	0	1	1	1	0	0

and are calculated as:

23.7

23.8

23.9

23.10

In order to provide the correct H-DCC operation, the voltage on each DC-link capacitor should be stabilized on ½. Switching states used for the balancing of capacitor voltages and – depending on output voltage level and sign of line current – are shown in Table 23.3. For each sampling period, one (over the entire calculated time ) or two (each at the appropriate parts of calculated time ) redundant states affecting the DC-link capacitor voltages can be used. Switching state selection and duration time depend on the PWM technique applied, which are described subsequently: 1D-N2V or 1D-N3V modulations.

Output voltage level	DC-link voltages	Line current	Switching state
½			0	1	0	0
			1	1	0	1
			1	1	0	1
			0	1	0	0
			0	1	1	1
			0	0	0	1
			0	0	0	1
			0	1	1	1

The 1D-N2V modulation for the H-DCC is based on the assumption that only two switching states are applied in each sampling period [20 26]. To reduce the number of switching, between output voltage transition from to , only is selected from the three redundant (Table 23.2). Figure 23.5 presents the H-DCC positive output voltage-switching patterns for the 1D-N2V modulation. The 1D-N2V modulation allows obtaining the symmetrical duty cycle placement of three voltage-forming states for all output voltage levels.

Another modulation technique for H-DCC is the 1D-N3V. Figure 23.6 presents the positive output voltage-switching patterns for 1D-N3V modulation, which is based on the assumption that both redundant switching states, for whichever output voltage level are applied in each sampling period [20 26, 27]. The 1D-N3V modulation allows symmetrical duty cycle placement to be obtained for the seven (see Figure 23.6(a)) and five (see Figure 23.6(b)) output voltage forming states for lower and upper output voltage levels, respectively. Redundant switching states are applied for the appropriate part of the calculated time , which corresponds to the voltage ratio between DC-link capacitors and . It means that if is larger than , will be charged less than . The ratio of charging time division of and is inversely proportional to the ratio of the and voltages:

23.11

where . As a result, during the sampling period, both DC-link capacitors over the calculated time will be charged or discharged.

It should be noted that the self-balancing of the DC-link capacitors with a symmetrical distribution of _, even for balanced and voltages, is not possible in practice because of:

• nonlinear IGBT gate signal propagation,
• different IGBT ON/OFF times,
• DC-link capacitor equivalent series and parallel resistances,
• differences in electrical parameters, such as each leg's semiconductor devices and connection points.

Therefore, an additional controller (proportional or proportional-integral (PI)) should be used in order to determine the distribution of _, providing the equalization of the and voltages.

23.2.3 H-Flying Capacitor Converter (H-FCC)

Figure 23.7 presents the single-phase H-FCC [28–30], which has two legs, with IGBTs denoted , , and , where and are the negation of , respectively and is the leg indication: or . The so-called FC are parallel connected to and for each leg. The FCs are used to generate the intermediate H-FCC voltage levels, which can be obtained – in contrast to the H-DCC – separately for each leg from the other leg-switching states. Balancing of the FC voltages uses two redundant switching states for each H-FCC leg and is independent of the switching states in the other leg.

Four different switching states (including two redundant states for FC voltage balancing), generating three different output pole voltages can be distinguished for a single leg of the converter:

• 0, when and are turned OFF (output pole voltage equals 0),
• 1, when:
  • is tuned OFF and is turned ON,
  • is tuned ON and is turned OFF,

  where both generate the same output pole voltage (depending on the selected state, or ),

• 2, when and are turned ON (output pole voltage equals ).

Switch number	Levels of output voltage
												½
	0	0	0	0	1	0	0	1	1	0	1	0	1	1	1	1
	0	0	0	1	0	0	1	0	0	1	1	1	0	1	1	1
	1	0	1	1	1	0	0	0	1	1	1	0	0	0	1	0
	1	1	0	1	1	0	1	1	0	0	1	0	0	1	0	0

In the case of the single-phase H-FCC, it gives 16 possible switching state combinations. Thus, the H-FCC allows five levels of module output voltage to be obtained (Table 23.4): six redundant for , four redundant for whichever , and one for whichever . Which output voltage level is applied is dependent on (Equations 23.1 and 23.6). For every level, the switching state duration times are assigned as follows:

• for ,
• for , which can be divided – with respect to the modulation technique used – into two times: and (where ) assigned for leg and , respectively (in each sampling period only one or two FC capacitors can be used in order to fulfill the modulation objectives),
• for ,

and are calculated in the same way as for the H-DCC (Equations 23.7–23.9, 23.10).

As mentioned earlier, in order to provide proper H-FCC operation, the voltage on each FC capacitor should be stabilized on ½. The balancing of single FC voltage or is independent of the switching state in the other leg. Therefore, switching states – depending on the output voltage level and sign of the line current – used only for FC voltage balancing in leg (leg is similar) are shown in Table 23.5.

Output voltage level	DC-link voltages	Line current	Switching state
½			1	0	0	0
			0	1	0	0
			0	1	0	0
			1	0	0	0
			0	1	1	1
			1	0	1	1
			1	0	1	1
			0	1	1	1

For each sampling period:

• one (over the entire calculated time , when only one FC is used),
• two (each at time and , when both FCs are used),
• all four (each at the appropriate part of the calculated times and )

redundant states affecting the FC capacitor voltages can be used. Switching state selection and duration time depend on the applied PWM technique: 1D-N2V, 1D-N3V, or 1D-N(3 + 2R)V modulations, respectively.

1D-N2V modulation is based on the assumption that only two switching states are applied in each sampling period, when only one leg is pulse-width modulated [20 26]. Which leg is switched depends on the sign of , similar to the parallel-connected H-BC (Equation 23.5). As a consequence, for a positive sign of , only one of two, whichever , redundant states for each lower or upper voltage level is selected. The duration of redundant state in leg is equal to with proper and output voltage switching states. Leg is permanently in the state. The selection of one of two possible redundant states for leg depends on the conditions given in Table 23.5. If has a negative sign, the opposite situation occurs – leg is modulated and leg is permanently in the state. To reduce the number of switching between and redundant output voltage state, the state is chosen from six redundant output voltage states (Tables 23.4 and 23.6). The reduced switching states of the 1D-N2V modulation are presented in Table 23.6. Figure 23.8 presents the positive output voltage-switching patterns for the H-FCC with the 1D-N2V modulation. It allows symmetrical duty cycle placement to be obtained for the three forming states of the output voltage for all levels, with two different switching states used in each sampling period.

Switch number	Levels of output voltage
					½
	0	0	0	0	1	0	1
	0	0	0	0	0	1	1
	1	1	0	0	0	0	0
	1	0	1	0	0	0	0

The next type, the 1D-N3V modulation, is based on the assumption that both legs, and , are working in each sampling period to generate the output voltage level [20 26, 27]. However, for each leg only one of two, whichever _, redundant states for the lower or upper voltage level is selected over the calculated time equal to ½. Switching state selection for leg depends – similar to 1D-N2V modulation – on the conditions given in Table 23.5. Such a selection results in four possible combinations of switching states generating output voltage . To reduce the number of switching between output voltage and , for each aforementioned combination, only two (from six redundant output voltage states) are chosen:

• one permanently: or (for positive and negative voltage levels, respectively),
• one depending on the selected combination: for and , for and , for and and finally for and .

All lower and upper ½ positive output voltage level switching state combinations are shown in Figures 23.9 and 23.10, respectively.

The symmetrical duty cycle placement of the four different switching states used for the lower output voltage level gives seven forming states of output voltage (Figure 23.9), but the upper positive voltage level redundant states are placed nonsymmetrically with respect to the middle of the sampling period; however, the output pulses of are generated symmetrically (Figure 23.10). Three different switching states used for the generation of the upper levels (combination of redundant intermediate with the proper or state) gives five forming states of the voltage.

It is possible to increase the H-FCC output pulse frequency over the frequency generated by the 1D-N3V modulation, which is not possible for the H-DCC. This can be achieved by the method proposed in Ref. [31] the 1D-N(3 + 2R)V modulation. The 1D-N(3 + 2R)V modulation is based on the assumption that in every sampling period all four redundant output voltage switching states are used (Figure 23.11). As a result, both FCs are charged and discharged in each period, where the redundant switching state charging and discharging of the FCs are applied for the appropriate part of the calculated time (for and , respectively) equal to ½. It means, for example, that if is bigger than ½, will be more charged than discharged. The ratio of and between charging and discharging state time division is a proportional function of and FC voltages and :

23.12

where . Such an approach to the nonsymmetrical switching of each IGBTs allows the same output voltage waveform to be obtained as for the parallel-connected H-BC with UPWM – nine forming states of output voltage for all output voltage levels with:

• eight different switching states used per period for the lower output voltage,
• five different switching states used per period for the upper output voltage.

The self-balancing of the FC voltages (assuming and ) is not possible in practice, for reasons similar to the 1D-N3V modulation for H-DCC (in addition to the FC's equivalent series and parallel resistances).

23.2.4 Comparison

The reference for the comparison study of the single-phase VSC topologies and PWM techniques presented is the single-phase parallel-connected H-BC with unipolar modulation used in RTPSs. Such a converter, owing to interleaved modulation, provides an increased number of output voltage forming states and very low current harmonics distortion on the transformer high-voltage side.

Table 23.7 presents the number of output voltage forming states visible from the transformer high-voltage side and the number of total switching states used in the sampling period to generate the voltage waveform. The comparison of PWM techniques shows the clear advantage of the parallel-connected H-BC with the UPWM and the H-FCC with the 1D-N(3 + 2R)V modulation with respect to the highest number of forming states.

PC-H-BC		H-DCC		H-FCC
HPWM	UPWM	1D-N2V	1D-N3V	1D-N2V	1D-N3V	1D-N(3 + 2R)V
Lower levels of output voltage :
5/4	9/8	3/2	7/6	3/2	7/6	9/8
Upper levels of output voltage
5/4	9/8	3/2	5/4	3/2	5/4	9/8

Figures 23.13–23.15 present the steady-state operation of the 1 MW parallel-connected H-BC, H-DCC and H-FCC with the UPWM, 1D-N3V and the 1D-N(3 + 2R)V modulations, respectively. The simplified simulation model for the aforementioned cases is shown in Figure 23.12, with the main electrical parameters of the power circuits and control data given in Table 23.8. For all cases, the converter voltage harmonics distortion factor is similar. However, with respect to 1 kHz sampling frequency bands related to the output pulse's frequency:

• quadrupled for the parallel-connected H-BC (Figure 23.13(e-f)),
• doubled for the lower (Figure 23.14(e)) and tripled for the upper (Figure 23.14(f)) output voltage levels for the H-DCC,
• quadrupled for the H-FCC (Figure 23.15(e-f)),

Simulation parameter	Symbol	Value
Topology		PC-H-BC	H-DCC	H-FCC
Transformer power/primary side		1 MVA
Grid voltage/primary side		25 kV/50 Hz
Grid current/primary side		40 A
Transformer power/secondary sides	,	500 kVA	1 MVA
Line voltage/secondary sides	,	950 V/50 Hz	1900 V/50 Hz
Line current/secondary sides	,	526 A	1052 A
Primary leakage inductance		24 mH
Primary winding resistance		3 Ω
Magnetizing inductance		24 H
Core loss resistance		60 kΩ
Secondary leakage inductance	,	1.44 mH	0.72 mH
Secondary winding resistance	,	15 mΩ
Sampling frequency		1 kHz
Capacitance of DC-link capacitors	,	23.4 mF	46.8 mF	23.4mF
DC-link voltage		1800 V
Capacitance of flying capacitors				11.7 mF

shifting in the direction of higher harmonics can be observed:

• 4 kHz for the parallel-connected H-BC (Figure 23.13(g)),
• 2 kHz and 3 kHz for the H-DCC (Figure 23.14(g)),
• 4 kHz for the H-FCC (Figure 23.15(g)).

Thus, a similar voltage distortion factor for higher frequencies provides a lower harmonics distortion of the grid current.

PC-H-BC		H-DCC		H-FCC
HPWM	UPWM	1D-N2V	1D-N3V	1D-N2V	1D-N3V	1D-N(3 + 2R)V
1 MW output power, 100% load,
3.11%	2.03%	6.93%	3.61%	6.47%	3.46%	2.11%
0.33 MW output power, 33% load,
8.39%	5.30%	21.13%	9.78%	17.66%	9.56%	6.46%

Table 23.9 presents a comparison of the grid current distortion for all topologies and modulation techniques presented, with different load values. It can be observed that the parallel-connected H-BC with the UPWM, as well as the H-FCC with 1D-N(3 + 2R)V PWM modulation – thanks to the increased number of output voltage forming states – provides the lowest grid current distortion . However, if the H-FCC with 1D-N(3 + 2R)V modulation and parallel-connected H-BC with UPWM:

• provide similar harmonics injection into the power system,
• uses all switches in the sampling period to generate output voltage,
• uses the same voltage and current class semiconductors (which guarantees similar switching losses),

the advantages of the H-FCC solution are:

• a reduced number of transformer low-voltage side windings,
• a reduced transformer volume, size and weight,
• component price reductions due to the decreased voltage class semiconductors.

On the other hand, the parallel-connected H-BC has a high reliability in the case of one module failure – the VSC works with the same amplitude of but with twice reduced power and with an increased THD factor of . For the H-FCC in the case of one leg failure (as well as for the H-DCC), there is the possibility of switching off the broken leg and connecting the phase from the broken leg to the midpoint of the connection of the DC-link capacitors. The advantage of such a solution is that full power is delivered to the load, but of course at the cost of an increased THD factor of the However, it is necessary to modify the PWM strategy, which is not required with the parallel-connected H-BC.

23.3.1 Single-Phase Control Algorithm Classification

The current control should ensure a constant switching frequency with a specified switching pattern from a filter design point of view. This requirement can only be satisfied with PWM-based current control, allowing the implementation of modern PWM techniques [32]. Unless high dynamic requirements are given, a linear controller is the most suitable for PWM-based current control. Linear controllers are designed on an average model of the converter based on PWM, which is responsible for the transformation of continuous switching functions into discrete switching pattern functions. Two such systems, PI- and proportional-resonant (PR) based current control (PI-CC and PR-CC, respectively) schemes, have gained superior position [33–36].

PI-based current control is mainly used in synchronous reference frame rotating with the grid voltage, in which control variables become DC values. The PI controller – composed of proportional gain and an integrator – tracking DC reference is able to eliminate steady-state error. However, in natural reference frame, the PI controller exhibits two well-known drawbacks: the inability to track the AC reference without steady-state error and poor disturbance rejection capability.

The tracking of periodical signals and rejection of periodical disturbances problem in the natural reference frame can be solved by using PR-based current control. A PR controller – composed of proportional gain and a resonant integrator – achieves a very high gain around the resonance frequency and almost no gain outside this frequency. Therefore, the PR controller is capable of not only eliminating steady-state amplitude but also phase error. The implementation of a PR controller in natural reference frame is straightforward, and in comparison to PI-based control the complexity of the control algorithm is considerably reduced.

As far as PR-CC can be used directly, for PI-CC a transformation from a natural to synchronous reference frame is needed. In three-phase systems, coordinate transformation is straightforward. However, in single-phase, it is necessary to create a second quantity in-quadrature with the real one. There are a few mathematical methods available to achieve a set of in-quadrature signals based on the measured single-phase grid voltage [37 38]:

• transport delay technique, where is the fundamental grid frequency period,
• Hilbert transform,
• inverse Park transform.

These methods, while allowing for correct quadrature signal generation (QSG), are complex, nonlinear and significantly dependent on fundamental grid frequency changes. Algorithms that are able to eliminate these drawbacks are based on adaptive filtering, allowing in-quadrature generation based both on the phase and frequency synchronization: the second-order adaptive filter and the second-order generalized integrator (SOGI), of which SOGI is most suitable [39].

Synchronization with grid voltage for high (including unity) input power factor operation for both CC methods is also needed. The typical hardware solution with grid voltage zero crossing detection (discontinuous and dependent on the occurrence of the event) is based on line voltage measurement. Filtering of the measured signal in order to determine the zero crossing generates errors, because of the low speed of synchronization and possible distortions arising from the zero crossing detection under distorted voltage. Solutions based on mathematical algorithms – PLLs – allow for fast and accurate synchronization while eliminating the influence of interferences. PLL needs in-quadrature signals, which can be obtained for a single-phase system with SOGI. The SOGI-PLL detects the input phase-angle faster than conventional PLL without steady-state oscillations [39].

As mentioned, unlike PR-CC, a PI-CC transformation from natural to synchronous reference frame is needed. As for both solutions PLL is necessary, the SOGI does not increase the complexity of the control algorithm. However, coordinate transformation from to and then inverse transformation is necessary for PI-CC, which makes it more complicated.

Another important issue for current control is the ability to compensate grid harmonics in order to improve power quality. Power quality – beyond the control of amplitude and phase – is one of the responsibilities of current controllers. In , synchronous coordinates harmonics compensation is based on low-pass and high-pass filtering with PI regulators. For specific harmonic coordinates, frame rotating with harmonic frequency should be implemented. Filtered signals are controlled by two PI regulators in coordinates and again transformed to rotating coordinates with fundamental frequency. The obtained signals are added to signals referenced for the PWM modulator. In natural reference frame harmonics, compensation is based on a resonant controller. For specific harmonics, there is no need for additional coordinate transformation and filtering. For single harmonics, an additional resonant controller is parallel connected to a fundamental frequency PR controller. Thus, in coordinates, two PI controllers are needed, whereas in only one resonant part is used.

In this section, the basic structures of the synchronous reference frame current control, PI-CC, and the natural reference frame current control, PR-CC, are presented. Moreover, the development of current and DC-link voltage controllers with tuning methods for PI, PR, and PMR is discussed. Ultimately, the APFF algorithm used to improve the dynamics of the DC-link stabilization is presented.

23.3.2 DQ Synchronous Reference Frame Current Control – PI-CC

A characteristic feature for synchronous reference frame current control is coordinate transformation from stationary to synchronous rotating and opposite from , which is very natural for a three-phase system:

23.16

23.17

where an angle of the voltage vector is defined as

23.18

The line current vector is split into two rectangular components in voltage-oriented coordinates (Figure 23.19). The component determinates the reactive power, whereas determines the active power flow. Thus, the reactive and the active power can be controlled independently. Unity power factor operation can be achieved when the line current vector is aligned with the line voltage vector .

The situation is slightly more complicated in the case of a single-phase system, because the coordinates are virtual and need special algorithms to obtain the or system. Among the most attractive solutions is a method based on delaying the -axis by ¼ of a line voltage period to obtain the -axis (Figure 23.20(a)) or the use of notch filters with a narrow stop-band (e.g., second-order Butterworth) tuned at twice the line frequency [40 41] (Figure 23.20(b)).

The voltage equations (Equation 23.13) in the synchronous reference frame in accordance with the presented transformation (Equations 23.16 and 23.17) are as follows:

23.19

The block diagram of the control for the single-phase converter in the synchronous reference frame is shown in Figure 23.21. Measured and currents are compared with reference values and and the error is delivered to the PI controllers. Then, the decoupling terms and are applied according to Equation (23.19). Finally, based on Equation (23.17), converter reference voltages in the stationary coordinate system are calculated, where is used by the modulator and is discarded:

23.20

The control presented in Figure 23.21 can be significantly simplified, as shown in Figure 23.22 [42]. Thanks to the simple assumption that for a virtual -axis error of current control is equal to zero, the following equations:

23.21

23.22

can be simplified to form:

23.23

23.24

Thanks to this, only a simple PLL is needed to obtain the synchronous rotating coordinate system instead of using coordinate transformations from stationary to synchronous rotating (Equation 23.17), notch filters or storing samples to get a quarter cycle delay.

23.3.3 ABC Natural Reference Frame Current Control – PR-CC

Figure 23.23 presents the block scheme of the PR controller-based current control algorithm, which consists of two cascaded loops. The commanded DC-link voltage is compared with the measured value. The voltage is distorted by 100 Hz AC oscillations derived from the single-phase current with 50 Hz fundamental frequency. Because the has a constant DC value, the 100 Hz distortion will be visible in the DC-link voltage error signal . The signal is delivered to the PI controller, which generates the reference line current amplitude . As the PI regulator is not able to eliminate phase error, in order to prevent transmission of 100 Hz distortion on the current , a low-pass filter with 30 Hz cutoff frequency is applied on the measured voltage. The delay introduced by the filter causes a reduction in the voltage loop dynamics, and as a consequence the DC-link voltage transient error should be higher. In fact, for a low switching frequency, the step change response of the DC-link PI controller with and without a low-pass filter is similar. The reason is the limited bandwidth of the voltage loop, which is more restrictive than the bandwidth reduction introduced by the filter. However, for higher sampling frequencies, the dynamics of the voltage loop will be reduced. It should also be noted that for a low sampling frequency the time of the step response will be longer than in the case of a high sampling frequency. To improve the dynamics of the DC-link stabilization, the power feed-forward signal (containing information about the load changes) should be added to the output signal of the DC-link voltage controller (see Section 23.3.4). APFF provides very good stabilization of the DC-link voltage in transient states, and the DC-link voltage overshoot is significantly reduced.

The internal current loop is responsible for system power quality by controlling the grid current. In PR-CC, unity power factor operation can be achieved if the reference line current is given as:

23.25

The cosinus function is used because of the SOGI-PLL phase-angle generation – when the amplitude has the maximum positive value. The reference value of is compared with the measured line current and the error is delivered to the PR controller. The PR structure shown in Figure 23.24(a) is composed of proportional gain and a resonant integrator [33 36].

The core of the resonant integrator is the generalized integrator, which achieves a very high gain around the resonant frequency and almost no gain outside this frequency. The transfer function of an ideal PR controller is given by:

23.26

where is the proportional gain and is the gain of the resonant integrator. The transfer function of the PR controller contains a double imaginary pole adjusted to the fundamental frequency . Thus, the PR controller is able to track the input phase angle for without any steady-state error. Note that the voltage feed-forward is not needed. To avoid stability problems with infinite gain, the following transfer function can be used instead of Equation (23.26):

23.27

where cutoff frequency . For Equation (23.27), the gain is finite (but still high enough to track the input phase-angle with small steady-state error) and bandwidth can be set by .

The current controller has to be immune for most prominent harmonics in the current spectrum – typically, the third, fifth, and seventh and sometimes the ninth harmonics. In a single-phase system, it means that for each harmonic a separate compensator is needed. For the natural reference frame, three compensation loops are also needed, where each resonant controller works with the gain of the fundamental PR controller. Still, the individual design of compensator resonant parts should be considered; however, it is possible to use the resonant gain of the fundamental PR controller. As the proportional controller only compensates frequencies very close to the selected harmonics frequencies, the resonant compensator does not affect the dynamics of the fundamental PR controller. Such a structure is called a proportional multiresonant (PMR) controller [43–45]. Figure 23.24(b) shows an example of a PMR controller block diagram for the third, fifth, seventh and ninth harmonics compensation, where compensators are parallel connected to the fundamental PR controller. The transfer function of PMR is given by:

23.28

where is the harmonic order. The harmonics compensator can use the same gain as the fundamental PR controller for all loops.

The PR controller generates the amplitude of the converter output voltage , which is delivered to the pulse-width modulator.

23.3.4 Controller Design

23.3.4.1 Design of PI-Based Current Control Loop

Figure 23.25 presents a block diagram of a PI-CC loop. The one sampling delay introduced by the control algorithm as well as the statistical delay of the PWM generation should also be taken into account. Thus, the time delays in the S&H block of VSC are represented as – the sum of small time constants:

23.29

Also, the VSC gain and dead time should be included. In further considerations, the VSC will be assumed as an ideal amplifier with , with time constant .

With the assumption that disturbance the open-loop transfer function can be written as:

23.30

where is the line choke time constant and is the choke gain. With simplification the closed-loop transfer function can be written as [46]:

23.31

The design procedures for the PI current controllers have been presented in Refs. [47 48]. For good disturbance rejection performance in transient states, both use the symmetry optimum (SO) [49] design criterion. Therefore, for Equation (23.31), with the assumption that the disturbance , the PI controller proportional gain and time constant can be calculated as:

23.32

23.33

23.3.4.2 Design of PR-Based Current Control Loop

Figure 23.26 presents a block diagram of a PR-CC loop. The one sampling delay introduced by the control algorithm as well as the statistical delay of the PWM generation should also be taken into account. Thus, the time delays in the S&H block of VSC are represented as – the sum of small time constants:

23.34

Also, the VSC gain and dead time should be included. In further considerations, the VSC will be assumed as an ideal amplifier with with time constant .

With the assumption that disturbance the open-loop transfer function can be written as:

23.35

As shown in Ref. [39], the proportional gain of the PR controller – which determines the dynamics of the system in terms of bandwidth, phase and gain margins – can be tuned in the same way as the PI current controller [47 48]. According to the SO [49] design criterion, with the assumption that the disturbance , the PR controller proportional gain can be calculated as:

23.36

To tune the resonant gain of the PR controller , a graphical frequency response approach can be used. The objective is to guarantee a sufficient phase margin for the system, and to avoid high resonances in the closed loop [50–52]. Figure 23.27 presents an example of a closed-loop frequency response for the designed PMR current control with 3rd, 5th, 7th and 9th harmonic compensation. For the PMR controller, the same gain values can be used as for the PR-based current control with the gain of the harmonics compensator .

23.3.4.3 Design of DC-Link Voltage Control Loop

Figure 23.28 presents a block diagram of the DC-link voltage control loop with an internal current controller. The inner current control loop with SO design criterion [49] is represented as a first-order transfer function with an equivalent time constant:

23.37

To prevent 100 Hz distortion transmission on the reference current, a low-pass filter with a cutoff frequency is required on the voltage sensor. The time constant of the filter is expressed as:

23.38

The relation between the amplitude of the referenced current and DC-link current is described as . Taking this and the assumption that the current relation is included in the proportional gain , Figure 23.29 shows the modified block diagram of the DC-link voltage control loop.

The open-loop voltage control loop transfer function can be written as:

23.39

On the basis of the SO design criterion, the proportional gain and the integral time constant of the DC-link voltage control loop can be calculated as follows:

23.40

23.41

As the DC-link referenced voltage is assumed to be constant, no additional pre-filter on is needed.

23.3.5 Active Power Feed-Forward Algorithm

To prevent the transmission of 100 Hz distortion on the line current , a low-pass filter with a specified (typically 30 Hz) cutoff frequency is applied on the measured voltage. The delay introduced by the filter causes a reduction in the DC-link voltage loop dynamics. As a consequence, the DC-link voltage transient error is higher and the AC–DC–AC system's dynamic behavior has to be reduced. There are two methods to improve the dynamics of the DC-link stabilization:

• Adding a load feed-forward to the output signal of the DC-link voltage controller from the DC-link load current – in such a case, an additional DC-link current sensor is needed, and the AC–DC converter operates independently of the control of the drive.
• Adding a power feed-forward to the output signal of the DC-link voltage controller from the supplied active load (the DC–AC converter fed motor) – in such a case, the AC–DC converter operates depending on the control of the drive, but no additional sensor is needed.

Thus, for the control of the AC–DC–AC converter, the APFF (based on the control signals) seems to be attractive.

According to Refs. [31 48], two variants of the APFF based on the power consumed/produced by the DC–AC converter can be listed:

• Active power of the AC–DC converter is calculated from the mechanical speed, commanded torque, and DC–AC converter losses, .
• Active power of the AC–DC converter is calculated from the switching states reference converter voltages and actual stator currents, .

Typically, in HSR, an induction motor (IM) is used. The electromagnetic power of the IM is defined by:

23.42

where is the mechanical speed of the drive. Taking into account the electromagnetic torque equation:

23.43

where is the number of IM pole pairs, is the number of IM phases, is the IM stator flux and is the component of the IM stator current, the electromagnetic power of the IM can be expressed as:

23.44

The power delivered to the IM also includes the power losses, and the should be written as:

23.45

For nominal torque at mechanical speed , the electromagnetic power . However, will have a significant value. Thus, cannot be neglected. The estimation of the is difficult, because it requires an exact knowledge of the parameters of the IM. Hence, , calculated from the reference converter voltages and (reconstructed from the switching states) and actual stator currents, provides a simple estimation of the active power consumed/produced by the DC–AC converter:

23.46

The and voltages, reconstructed from switching states, contain additional information about the dead time and switching devices voltage drop compensation. Therefore, the includes the power losses .

If we assume that the losses of the AC–DC converter are neglected, the energy storage variation of the DC-link capacitor will be the integral of the difference between the average AC–DC input power and the power delivered to the IM [31 48]. Therefore, it can be written as:

23.47

where denotes the power of the DC-link voltage feedback control loop:

23.48

According to the block diagram of the DC-link control loop (Figure 23.29), can be written as:

23.49

The DC-link voltage controller generates the reference line current amplitude . If we assume that the AC–DC converter works with the unity power factor (phase shift between line current and line voltage is equal to ) the instantaneous AC–DC input power can be calculated as:

23.50

According to Equation (23.50), the average AC–DC input power can be calculated as:

23.51

Therefore, the reference line current amplitude should be:

23.52

If we assume that the power is delivered to the IM without any DC-link variation (which is the desired situation), then can be assumed to equal . In such a situation, Equation (23.46) can be written as:

23.53

Thus, combining Equation (23.52) with Equation (23.53), the reference line current amplitude from the APFF is obtained:

23.54

Figure 23.30 shows the block diagram of the AC–DC–AC converter feeding IM, where and are the reference and output powers of the DC–AC converter, respectively. Figure 23.31 presents the transient operation of the low-voltage AC–DC–AC converter: AC–DC five-level single-phase FCC and DC–AC three-level three-phase FCC without and with APFF in closed speed control mode under a step change of mechanical speed from −85% to 85% of the nominal speed. The AC–DC–AC converter control with the active APFF provides:

• very good stabilization to the DC-link voltage in transient states – the DC-link voltage overshoot is significantly reduced,
• no negative impact on the system's performance in steady states.

Thus, the APFF, by a reduction in the DC-link overvoltage in transients, can efficiently extend the lifetime of the DC-link capacitors.