Index

Note: Page numbers followed by f indicate figures, t indicate tables, b indicate boxes, and np indicate footnotes.

A

Access control list (ACL) e8
Active safety systems 249–250
Address space layout randomization (ASLR) e27
Advanced Encryption Standard (AES) e11, 66
Advanced persistent threat (APT) e30
Advance encryption standard (AED) 179
Air traffic control (ATC) 155
Algorithm-based fault tolerance (ABFT) 298
considerations for 323–325
detection and correction 312–313
on flip-flops 325, 325t
Amorphous processing elements (APEs) 79–81, 105
Analog to digital converter (ADC) 217–218, 242, 253
Anomaly detection (AD) 10, 68
Antilocking braking (ABS) 249
Antitamper technologies (AT) e32
Antivirus systems e39
Application benchmark dependence 325–328
Application-level fault injection (AFI) 25–26
high-level block diagram 23, 24f
Application programming interface (API) 29
Application-specific fault tolerance techniques 137–139
Application-specific integrated circuits (ASICs) 13–14
Architecturally correct execution (ACE) 22
Architectural vulnerability factor (AVF) 22
Arithmetic logic unit (ALU) 192, 195
ATM jackpotting 180–181
AURIX© Platform 253, 254f
Automated Measurement of Systems for Energy and Temperature Reporting (AMESTER) 30–32
Automotive embedded system 
lifecycle 238, 238f
rugged autonomous vehicles 237–242
automotive ECUs 239–240
ECU architecture 240–242, 240f, 242f
electronics in modern vehicles 237–239, 238f
environment constraints for 243–248
Automotive safety domain 249
active system 249–250
passive system 249–250
Automotive safety integrity (ASIL) 250
Autonomous aerial vehicles 210, 262–265

B

Bandgap effects 244–245
Bias temperature instability (BTI) 67–68
Bipolar-CMOS-DMOS (BCD) 216
Bistable cross-coupled dual modular redundancy (BCDMR) 314–315
BlackPOS e49
Block RAMs (BRAMs) 46
Bob’s public key e13
Borrowed code chunks e61
BrainSoC 214–219
architecture 217–219, 218f
RoboBee’s electronic subsystem 214–217, 215–217f
Buffer overflow attacks 
heap overflow attacks e58
real stack overflow attacks e58
secure code e59
stack protection e58
stack uses e53–e58
Built-in self-test (BIST) 60–61, 223–224, 227
fixed-vs. adaptive-frequency clocks 230, 230f
Built in soft error resilience (BISER) 314–315

C

Certificate authority (CA) 
Certificate deployment point (CDP) e19–e20
Certificate revocation lists (CRLs) e19
Certification practice statement (CPS) e18
Checkpointing 
definition 130
interval 130–131
privileged-level 133–137, 134–136f
and restart solutions 130–131
user-level 131–133, 132f
Check-summing 138
Chip power consumption 1–2, 9
Chip reliability 9
Chip ruggedness 1
Circuit under test (CUT) 68
Claimant’s public key e6
Classical Dennard’s rules 10–11
Clock gating 2
Coded MB indication (COD) 86–87
Code injection attacks e62–e63
Command & control (C&C) 156
Commercial off-the-shelf (COTS) 123–124, 275–276
Common vulnerabilities and exposures (CVE) e46, 161
Comparison diagnosis model 13–14
Competitive runtime reconfiguration (CRR) 58–60
Computing system resiliency 
common-mode failures (CMF) 13–14
comparison diagnosis model 13–14
concurrent error detection (CED) 13–14
error containment strategies 14
FI 13f, 14
PSNR 14
redundancy-based AD methods 13–14
resiliency-enabled processing phases 13, 13f
test vector strategy 14
triple modular redundancy (TMR) 13–14
Configuration logic blocks (CLBs) 60–61
Control and status registers (CSRs) 202–203
Control flow checking by software signatures (CFCSS) 300, 308
error coverage 311, 311t
static control flow graph 311
Conventional evolutionary refurbishment (CER) 96
Coreboot e71
Correct execution (CO) 127–128
Countermeasure e64–e65
Credential Service Provider (CSP) e1–e2
Cross-layer combinations 316–325
general-purpose processors 319–323, 319f
targeting specific applications 323–325, 325f
ABFT 323–325
Cross-layer exploration for architecting resilience (CLEAR) 
framework 296–299, 297f
execution time 301
physical design 301–302
reliability analysis 299–301, 301t
resilience library 302–316, 307f
harsh-environment-capable embedded systems 296
resilience techniques 316–319
Cross-layer optimization approach 4, 5f
Cross-layer resilience 295–296
Cryptography 
CA hierarchies e18–e20
certificates e18–e20
public key technologies e12–e18
shared key encryption e9–e11
SSL transport layer e20–e21
Cumulative distribution function (CDF) 287, 287f
Cyber 154
Cyber attack 
adversaries, changing nature 158
financial gain opportunities 158–159
industrial espionage 159–160
internet, opportunity scale 158
operation 
APT e49–e50
good vs. bad guys e48
insider e50–e51
multistage attacks e49
POS systems e52–e53
RSA attack e48–e49
SCADA controllers e51–e52
vulnerability timeline e48
zero-day exploits e47
ransomware 159
software mistakes 157–158
transformation 160
Cycles per instruction (CPI) 32–33

D

Data flow checking (DFC) 300
error coverage 308–309, 309t
Data-flow programming models 143
DCO  See Digitally controlled oscillator (DCO)
Defense Advanced Research Projects Agency (DARPA) 208–209
Defense in depth e67–e68
Denial of service (DoS) e40–e42
DDoS e41–e42
ICMP flood e40–e41
SYN flood e41
Dennard’s scaling rule 1–2
Detected but uncorrected error (DUE) 295, 300
Differential power analysis (DPA) e63
Diffused metal oxide semiconductor (DMOS) 216
Digital certificates e18
Digitally controlled oscillator (DCO) 226
adaptive-frequency 230, 230f
schematic and measured characteristics 227f
Digital signature e16f, e15
Direct numerical simulation 144–145
Discrete cosine transform (DCT) 66
Disk encryption e72
Distributed denial-of-service (DDoS) e41–e42
Divide-and-conquer approach 68 See also Task-based programming models
Domain name system (DNS) e36
Double-module redundancy (DMR) 123–124
DRFI 109–113
Dual interlocked storage cell (DICE) 314–315
Dual modular redundancy (DMR) 315
Dual priority model 48
Duqu 172–174
Dynamic replicas (DRs) 79–81, 105
Dynamic voltage and frequency scaling (DVFS) 2, 33

E

ECUs  See Electronic control units (ECUs)
Electric grid 184
Electromagnetic interference (EMI) 243, 268, 270
Electromigration (EM) 17, 67–68, 245
Electronic control units (ECUs) 237–239
architecture 240–242, 240f
automotive 239–240
internal architecture abstraction 242, 242f
Electronic digital computers 1
Elliptic curve cryptography e24
Elliptic curve Diffie–Hellman (ECDH) e24
Elliptic curve digital signature algorithm (ECDSA) e24
Email spoofing 186
Embedded systems 3–4
certification standards 42, 42–43t
characterizing aspects 39–41
definition 39
harsh environment 34, 41–44
low-power 2–3
ruggedization 41
Embedded system security 
access control 
accountability 154
authentication 154
authorization 154
identification 153
antitampering e30–e33
antivirus systems e39
ATM jackpotting 180–181
authentication 
level 1 e4
level 2 e4
level 3 e5
level 4 e5
multifactor e6
authorization e6–e9
blackouts 191–192
buffer overflow attacks e53–e59
code injection attacks e62–e63
cryptography 
CA hierarchies e18–e20
certificates e18–e20
public key technologies e12–e18
shared key encryption e9–e11
SSL transport layer e20–e21
cyber 154
cyber attacks 
adversaries, changing nature 158
financial gain opportunities 158–159
industrial espionage 159–160
internet, opportunity scale 158
operation e47–e51
ransomware 159
software mistakes 157–158
transformation 160
defense in depth e28–e29
denial of service e40–e42
diversity e26–e27
Duqu 174
elliptic curve cryptography e24
firewalls e35–e36
flame 172–173
fundamental principles 
availability 151
confidentiality 150–151
integrity 151
Gauss 173–174
heartbleed 188–190
identification and registration e1–e3
infrastructure 182–184
intrusion-detection systems e37–e38
IOT security 165–167
IPSEC e33–e35
military 181–182
minimal privilege e29–e30
MITM e42–e44
motivation 150–192
one-time pad e21–e23
one-way functions e23–e24
operating system architecture e65–e73
point-of-sale systems 184–185
root cause analysis e25–e26
ROP e59–e62
routers 174–180
secure operating systems e68–e73
security and computer architecture 
fully exploiting metadata tags 194–195
metadata, programmable unit 195
micro-policies 196–202
problem solving 193–194
processor architectures and security flaws 192–193
security approach 
architectural flaws 162–163
asymmetrical 161–162
complacence, fear, no regulatory pressure 165
lack of expertise 165
software complexity 163–165
security policy 154
self-protection 
dover processor 203
metadata 202–203
PUMP 203
shellshock 190–191
side-channel attacks e63–e65
SIM e39–e40
social engineering 
password guessing 187
phishing 186–187
spoofing email 186
software vulnerability and cyber attacks e46–e65
steganography e23
stuxnet 169–172
threat model 
assets 152
exposure 153
risk 152
safeguard 153
vulnerability 152
Energy savings and fault-handling capabality 
online recovery 109
in reconfigurable design 106–109
for TMR vs. DRFI 109–113
Environment constraints for, automotive embedded systems 243–248
platforms, lifecycles, and maintainability 248
supply and power consumption 247–248
temperature 243–246, 243f
vibration and environmental factors 246–247
Error-correcting code (ECC) 23, 254
Error detection and correction (EDC) 278–279, 299–300
Error detection by duplicated instructions (EDDI) 311–312, 312t
Error detection sequential (EDS) 302–305, 305np
Error-free execution time 301
Error resiliency and self-adaptability 10–11
Ethernet 248, 255
European Cooperation for Space Standardization (ECSS) 276
European Space Agency (ESA) 273, 274f, 279–280
Evolutionary algorithms 
fault isolation via back tracing 88–92
NDER 92–99
Exascale supercomputers 139–145
checkpoint/restart 140
flat I/O bandwidth 140–142, 141t
performance anomalies 143–145, 144–145f
task-based programming models 142–143, 142f
Extreme scale computing 
application-specific fault tolerance techniques 137–139
checkpointing 
privileged-level 133–137, 134–136f
user-level 131–133, 132f
resilience 
exascale supercomputers 139–145
scientific applications 124–129, 127–128f, 129t
system-level 130–137
Extreme-value theory (EVT) 287–288

F

Fail-operational systems 252
Fail-safe systems 252
Fail-silent systems 252
Fail-stop semantics 130
Failures in time (FIT) 22
Fault Demotion using Reconfigurable Slack (FaDReS) 61
anomaly detection, isolation, and recovery 71–74
FHME 79–87
hardware organization 71
PSNR 78
PURE algorithm and 74–79
Fault detection (FD) 10, 61, 78, 80t
Fault-handling motion estimation (FHME) 79–87
dynamic redundancy 85
energy savings and fault-handling capabality 
online recovery 109
in reconfigurable design 106–109
for TMR vs. DRFI 109–113
fault recovery 86–87
hardware fault detection 83–84
healthy APE 85
isolation 86
mitigation strategy 82–83
Fault injection 23–26, 24–26f
resilience analysis 127, 127f
Fault isolation (FI) 10, 13f, 14
Fault propagation speed (FPS) 129, 129t
Fault recovery (FR) 10
fundamental components 14
Faults 251–252
intermittent 252
permanent 251
tolerance 4, 23
transient 251
Federal Information Processing Standard (FIPS) e5
FI  See Fault isolation (FI)
Fibonacci algorithm 142–143, 142f
Field programmable gate array (FPGA) 45, 58, 60f, 123
execution time 301
prototype 44–45
realistic multiprocessor system 49
File transfer protocol (FTP) e36
Financial gain opportunities 158–159
Firewalls e35–e36
Flame 172–174
Flip-flop soft errors 296, 299–300
Floating-point representation 125–126
Floating point units (FPU) 286
Flush/reorder buffer (RoB) 313–314, 313t, 314f
Full checkpointing 130–131, 135–136
Fully exploiting metadata tags 194–195
Functional and timing verification 276–281
Functional constraints, automotive system 249–259, 249f
availability 257–259
safety 249–255, 254f
security 255–257, 256f
Functional diagnosis, of reconfigurable fabrics 
AES 66
anomaly detection 68
divide-and-conquer method 69–70
FaDReS 70–74
ICAP 66
NDER 65–66
pruned refurbishment 65–66
scrubbing 67–68
static redundancy 65
Functional verification and testing 277–279

G

General-purpose computer servers 123
General Purpose Input-Output (GPIO) 100
General-purpose processors 319–323, 319f
Global checkpoint/restart 140
Global ready queue (GRQ) 49
Global schedulers 45, 49, 49f
Aperiodic Ready Queue 50
Periodic Ready Queue 50

H

HardenedBSD e68–e69
Hard-error vulnerabilities 10–11, 139–140, 143–144, 252
analytical models 18, 20f
HCI testing 21
integrated circuits (ICs) 17
MTTF 21–22
NBTI-induced 18
reliability mechanisms 17–18
TDDB testing 20
wearout failure 18
Harsh computing 
functional verification and testing 277–279
on-board computing 
cost 275–276
high-performance architectures 272–273
performance requirements 271–272
security 276
semiconductor process technology 273–275
space environment 270–271
probabilistic approach 
anomaly detection, isolation, diagnosis, and recovery 290
degraded caches, operation 288–290
fault impact 290–291
MBPTA 285–291
randomization, handling system complexity 283–285
traditional wcet analysis techniques 282–283
timing verification 279–281
Harsh environmental conditions 2–3, 9, 11–12
Hash function e15–e17
Heap overflow attacks e58
Heartbleed 188–190
High-performance architectures 272–273, 278–279
High-performance computing 126
High-priority local ready queues (HPLRQ) 49
Host based intrusion-detection systems (HIDS) e37, e38
Hot carrier injection (HCI) 17
hard-error vulnerabilities 21
wearout modes 21
Hybrid timing analysis (HyTA) 282
Hypertext transfer protocol (HTTP) e36

I

Implantable cardioverter-defibrillators (ICDs) 178–179
In-band vs. out-of-band data collection 30–32
Incremental checkpointing 130–131, 134–136
vs. full 135–136, 135–136f
Industrial control systems (ICSs) 155, 183
Inertial measurement unit (IMU) 213
Infineon AURIX 272, 278
Information assurance e67–e68
Insect-scale aerial robot 211, 213
Insider attack e50–e51
Instruction replay (IR)/extended instruction replay (EIR) 313–314, 313t, 314f
Integrated voltage regulator (IVR) 217
switched-capacitor topology 217
Integrity e18
Intermittent faults 252
Internal Configuration Access Port (ICAP) 66, 112–113
Internet control message protocol (ICMP) e40–e41
Internet of Things (IoT) 2–3
architectural vision for 3, 3f
Internet protocol security (IPsec) 
TLS/SSL e34–e35
transport mode e33
tunnel mode e33–e34
VPN e34
Internet service provider (ISP) e44
Interrupt distribution 47
Introduction-based routing (IBR) e44–e45
Intrusion detection and prevention systems (IDPS) e37
Intrusion-detection system (IDS) e28
HIDS e38
limitations e38
NIDS e37

K

Key distribution centers (KDCs) e12–e13

L

Large eddy simulation (LES) 144–145
Larger-scale man-made aerial vehicles 211
Layered defense e67–e68
Least-privileged user account (LUA) e30
Line-edge roughness (LER) 114
Linux kernel module 134
Linux operating system 165–166
Local area network (LAN) e34
Local schedulers 45, 49, 49f
Look-up tables (LUTs) 109
Los Alamos National Laboratory (LANL) 123–124
LULESH 
corrupted memory locations (CML) 129
fault propagation analysis 128–129, 128f

M

Mandatory access controls (MAC) e69
address spoofing e29
Man-in-the-middle (MITM) attacks e4
MAVs  See Micro aerial vehicles (MAVs)
MBPTA 285–291, 289f
Mean time to failure (MTTF) 21–22, 103, 139–140
Mean-time-to-repair (MTTR) 103
Measurement-based timing analysis (MBTA) 282
Memory protection extensions (MPX) 194–195
Message authentication code (MAC) e18
Metal-oxide-semiconductor field effect transistors (MOSFETs) 1–2
MiBench benchmark 52
Micro aerial vehicles (MAVs) 6, 207
BrainSoC 214–219
architecture 217–219, 218f
electronic subsystem 214–217, 215–217f
challenges 210–211
definition 208–209
microrobotic SoC 219–233
prototype experimental evaluation 227–233, 228f
system implementation 223–227, 224f
timing slack analysis 222–223, 222f
unique reliability challenge 220–222, 221f
RoboBee 
design and implementation 212–213
global crisis 211
nature for inspiration 211
vision for future 213–214
Micro air vehicle 208
Microbenchmark generation framework 26–29
high-level description 27–29, 28f
sample script for 29, 30–31f
MicroBlaze soft-cores 46–47, 54
periodic and aperiodic tasks 51, 51f
Microelectromechanical system (MEMS) 208, 210, 212
Micro-policies 196–202
composite policies 201–202
control flow integrity 199–201
enforce security 197
memory safety 197–199
taint tracking 201
Microrobotic SoC 
prototype experimental evaluation 227–233, 228f
supply resilience in 219–233
conventional computing systems 220b
noise background 219b
system implementation 223–227, 224f
BIST 227
cortex-M0 and memory 226
DCO 226
SC-IVR 224–226, 225f
timing slack analysis 222–223, 222f
unique reliability challenge 220–222, 221f
Million operations per second (MOPS) 4, 4f
Modern automotive systems 
autonomous vehicles 262–265, 264f
modern car functions 259–261, 260–261f
Monitor vs. main core 309, 309t
Monte-Carlo method 115
Moore’s Law 162–163
Motion estimation (ME) 79–81
MTTF  See Mean time to failure (MTTF)
Multifactor authentication e6
multifunction control display unit (MCDU) 182
Multiprocessor dual priority (MPDP) algorithm 45
Aperiodic Ready Queue 50
kernel implementation 50
local and global scheduling 49, 49f
Periodic Ready Queue 50
real-time support 48–49
responsiveness 53
schedulability test 48
Multiprocessor interrupt controller 45–48

N

Nano air vehicle 210
National Institute of Standards and Technology (NIST) e1
NBTI  See Negative bias temperature instability (NBTI)
Near-threshold voltage (NTV) 9
NMR systems 114–115
power-performance impact 16–17
reliability, cost of 115–116
soft errors 113–114
Negative bias temperature instability (NBTI) 17
wearout modes 21
NEKBone 144–145, 145f
Netlist-driven evolutionary recovery (NDER) 65–66
large resource sharing 98
LUT 98
scalability evaluation 98–99
small number of primary outputs 98
Network based intrusion-detection systems (NIDS) e38, e37
New resilience techniques 329–330, 329f
Next Generation Multi Processor (NGMP) 273, 279–280
Node under test (NUT) 68
NP-Hard problem 45
N-version programming e27

O

On-chip controller (OCC) 30–32
On-chip peripheral bus (OPB) 46
One-time pad (OTP) e21–e23
One-way function e23–e24
Online certificate status protocol (OCSP) e19, e20
OpenSSL cryptography library 188
Operating system architecture e65–e73
defense in depth e67–e68
least privilege e65–e66
Original device manufacturers (ODMs) 166
Out-of-band vs. in-band collection 30–32
Output mismatch (OMM) 299–300

P

Partial reconfiguration modules (PRMs) 104–105
Partial reconfiguration region (PRR) 103
Passive recovery techniques 58
Password protection e73
Payload functions 269
Peak signal-to-noise ratio (PSNR) 14
Per-core power gating (PCPG) 33
Performance monitoring unit (PMU) 32–33
Permanent faults 251
Personal identity verification (PIV) e5
Phase locked loops (PLLs) 258
PI algorithm 241–242
Pico air vehicles 208
autonomous aerial vehicles 210
control challenge 210
Piezoelectric actuator 216, 216f
Piezoelectric bimorph 
layered structure 214, 215f
voltage-driven 214, 215f
Piezoelectric ceramics technology 212
Platform configuration registers (PCR) e72
Platform functions 269
Platform integrity e72–e73
Point-of-sale (POS) systems e49, 149, 184–185
Power and performance measurement 
in-band vs. out-of-band data collection 30–32
power modeling 33–34
processor performance counters 32–33
Power and reliability walls 2, 2f
Power-Aware Management of Processor Actuators algorithm (PAMPA) 33
Power electronics unit (PEU) 214
Power-performance impact, metrics on 16–17
Principle of least privilege 
Printed circuit board (PCB) 245–246
Priority Using Resource Escalation (PURE) 61
DCT module 100
divide-and-conquer 103
Privileged-level checkpointing 133–137, 134–136f
Proactive management techniques 16–17
Probabilistic Execution Time (pET) 287
Probabilistic WCET (pWCET) 288–290
Processor performance counters 32–33
Profiteers e47
Program counter (PC) 192
Programmable logic block (PLB) 60–61
Programmable logic controllers (PLCs) 160, 183, 187
Programmable unit for metadata processing (PUMP) 195
Prototype SoC experimental evaluation 227–233, 228f
adaptive-frequency clocking 230f, 231–233
fixed vs. adaptive clocking 229–231, 229f
frequency vs. voltage characterization 228, 229f
PSNR  See Peak signal-to-noise ratio (PSNR)
Public key encryption e17
Pulse frequency modulation (PFM) 216

Q

Quality of the service (QoS) 10
faults, errors, and failures 11
layered model 11, 11f
application layer 11f, 12
behavioral layer 11f, 12
resource layer 11–12, 11f
Qubes OS e69

R

Radio frequency identification (RFID) 156
Random dopant fluctuations (RDF) 114
Ransomware 159
Rapita’s Verification Suite (RVS) 286
Real stack overflow attacks e58
Real-time embedded systems (RTES) 267, 269, 272
Real-time multiprocessor system 
architecture 45–48
prototype 46
Real-time operation 39
Real-time scheduling algorithms, rugged embedded systems 
architecture 45–48
multiprocessor interrupt controller 47–48
prototype 46, 46f
automotive applications 46, 49
evaluation 52–54, 53f
FPGA 44–45
harsh environments 41–44, 42–43t
real-time support 
implementation details 50–52, 51f
MPDP algorithm 48–49, 49f
responsiveness 44
Real-time support 
implementation details 50–52, 51f
MPDP algorithm 48–49, 49f
Reconfigurable slacks (RSs) 61
Redundancy  See Faults
Redundancy-based AD methods 13–14
Redundant multi-threading (RMT) 315
Registration Authority (RA) e1–e2
Reliable and power-aware architectures 
computing system resiliency 13–15, 13f
fundamentals 9
hard-error vulnerabilities 17–22, 19–20f
measuring resilience 15–16
cost metrics 15–16
effectiveness metrics 16
microbenchmark generation 26–29
example of 29, 30f
overview 27–29, 28f
need for 9–15
power and performance measurement 
in-band vs. out-of-band data collection 30–32
power modeling 33–34
processor performance counters 32–33
power-performance impact 16–17
quality of service 11–12, 11f
soft-error vulnerabilities 22–26
fault injection 23–26, 24–26f
Reliable computer systems 
delivered service 9–10
functional specification 9–10
QoS 10
SER 10–11
technology scaling, per Moore's Law 10–11
Relying party (RP) e3
Remote attestation e72
Resilience library 302–316
Resilience measurement 15–16
cost metrics 15–16
effectiveness metrics 16
Resilience techniques 
autonomous hardware-oriented mitigation techniques 
evolutionary algorithms 87–99
functional diagnosis of reconfigurable fabrics 65–87
embedded real-time computation 
FaDReS  See (Fault Demotion using Reconfigurable Slack (FaDReS))
FHME, energy savings and fault-handling capabality  See (Fault-handling motion estimation (FHME))
NTV, reliability and energy tradeoffs  See (Near-threshold voltage (NTV))
extreme scale computing 
exascale supercomputers 139–145
scientific applications 124–129, 127–128f, 129t
system-level 130–137
static redundancy and traditional fault-tolerance techniques 
built-in self test 60–61
comparison of 59t
configuration logic blocks 60–61
CRR 58–60
desirable characteristics 63
FaDReS 61
FPGA 58
Self-Testing AReas 60–61
sustainability metrics 63–64
TMR 58
Resilient flip-flops 302–305, 305t
Retroreflective tracking markers 213
Return-into-library technique e60–e61
Return-oriented programming (ROP) e59–e62
attacks e61
borrowed code chunks e61
defenses e62
return-into-library technique e60–e61
x86 architecture e61–e62
Risk-based analysis 250
RoboBee  See also Micro aerial vehicles (MAVs)
BrainSoC electronic subsystem 214–217, 215–217f
design and implementation 212–213
actuation 212
fabrication 212
maneuver 212–213
sensing and control 213
global crisis 211
nature for inspiration 211
unique reliability challenge 220–222
vision for future 213–214
Root cause analysis (RCA) e25–e26
Router 174–180
automotive 177–178
aviation 176–177
diabetes glucose monitors and insulin pumps 179–180
medical 178
pace makers 178–179
RSA attack e48–e49
Rugged autonomous vehicles 
automotive embedded system 237–242
automotive ECUs 239–240
ECU architecture 240–242, 240f, 242f
electronics in modern vehicles 237–239, 238f
environment constraints for 243–248
functional constraints 249–259, 249f
availability 257–259
safety 249–255, 254f
security 255–257, 256f
modern automotive systems 
autonomous vehicles 262–265, 264f
modern car functions 259–261, 260–261f

S

Safety integrity 250
SAICs Adaptive Grid Eulerian (SAGE) 134–135
full vs. incremental checkpointing 135–136, 135f
Satellite data unit (SDU) 182
SCADA controllers e51–e52
SC-IVR  See Switched capacitor integrated voltage regulator (SC-IVR)
Script kiddie e46
Secure hardware extension (SHE) 257
Secure Hash Algorithm 1 (SHA-1) e17, e15
Secure operating systems e68–e73
boot and execution e70
coreboot e71
HardenedBSD e68–e69
platform integrity e72–e73
qubes OS e69
SELinux e69
trusted platform module e71–e72
UEFI e70
Secure Shell (SSH) e33
Secure Sockets Layer (SSL) e11, e21, e20
Security-Enhanced Linux (SELinux) e69
Security information management (SIM) e39–e40
Self-Testing AReas (STARs) 60–61
Semiconductor process technology 273–275
Shared key encryption e9–e11
Shellshock 190–191
Shifting function execution 261, 261f
Side-channel attacks e63–e65
countermeasures e64–e65
examples e63–e64
Signalto-noise ratio (SNR) 68
Signature verification e17
Silent data corruption (SDC) 25, 139–140, 295, 300
Silicon on insulator (SOI) 244
Simple power analysis (SPA) e64
Single error correction double error detection (SECDED) 278
Single-event effects (SEE) 271, 274
Single-event multiple upsets (SEMUs) 296
Single event upsets (SEUs) 23, 113, 296
Smart composite microstructure (SCM) 212
SoC  See System-on-chip (SoC)
Social engineering 185–187
password guessing 187
phishing 186–187
spoofing email 186
Soft error rate (SER) 10–11, 113
hotspots 23, 23np
Soft errors 139–140, 143–144, 252
fault injection 23–26, 24–26f
vulnerabilities 10–11, 22–26
Software vulnerability and cyber attacks 
common weakness enumeration e46
CVE e46
profiteers e47
script kiddies e46
vandals e47
Source of execution time variability (SETV) 283–284
Space exploration 1
Space/Time Analysis for Cybersecurity (STAC) e42
Sporadic tasks 45, 48, 50–51
SSL transport layer security e20–e21
Stack e53–e58
protection e58
Stateful packet inspection e36
Static redundancy and traditional fault-tolerance techniques 
built-in self test 60–61
comparison of 59t
configuration logic blocks 60–61
CRR 58–60
desirable characteristics 63
FaDReS 61
FPGA 58
Self-Testing AReas 60–61
sustainability metrics 63–64
TMR 58
Static timing analysis (STA) 282
Steganography e23
Stuxnet 169–172
Sum of absolute difference (SAD) 81
Supercomputers 123
Supervisory control and data acquisition (SCADA) 155, 183–184
Supply and power consumption 247–248
Suspect, Faulty, and Healthy (SFH) 69
Sustainability metrics 
critical components 64
fault 
capacity 64
coverage 64
exploitation 63
recovery granularity 64
Switched capacitor integrated voltage regulator (SC-IVR) 220, 221f
microrobotic SoC 224–226, 225f
SYN flood e40–e41
Synthesis and place-and-route (SP&R) 301–302
System-level fault-tolerance techniques 130
System-level resilience techniques 
privileged-level checkpointing 133–137, 134–136f
user-level checkpointing 131–133, 132f
System-on-chip (SoC) 214, 296
fully integrated prototype 223–224, 224f
prototype experimental evaluation 227–233, 228f

T

Tamper 
detection e32
evidence e32
resistance e32
resistant microprocessors e31
response e32
Task-based programming models 142–143, 142f
TDDB  See Time-dependent dielectric breakdown (TDDB)
Technology scaling, per Moore’s Law 10–11
Test vector strategy 14
Thermal-aware design 16–17
Threat model, embedded system security 
assets 152
exposure 153
risk 152
safeguard 153
vulnerability 152
Time-dependent dielectric breakdown (TDDB) 11–12, 103, 244–245
back-end (intermetal dielectric) 20–21
failure modes 18
hard-error vulnerabilities 17
progressive breakdown 18
Time-to-live (TTL) 173–174
Timing slack analysis 
on adaptive clocking 222–223
pipeline circuits 222, 222f
Total ionizing dose (TID) 11–12
Transient faults 251
Transparent Incremental Checkpointing at Kernel level (TICK) 134, 136
checkpointing 134–135, 134f
Transport layer security (TLS) e33, 188
Transport mode e33
Triple-Data Encryption Standard (3DES) e11
Triple modular redundancy (TMR) 13–14, 58, 61f, 109–113, 123–124, 315
fault detection latency 14
Trusted platform module (TPM) e71–e72
Tunnel mode e33–e34

U

UEFI e70
Unexpected termination (UT) 299–300
User-level checkpointing 131–133, 132f
US National Security Agency (NSA) e24

V

Vehicle ECUs 240
Vehicle-to-vehicle communication 259
Vibration and environmental factors 246–247
Virtual machine manager (VMM) 133
Virtual machines (VM) solutions 136–137
Virtual private network (VPN) e11, e34
Voice-over-IP (VoIP) e34
Von Neumann processor architecture 162–163, 162f

W

Wide area network (WAN) e34
Worst-case execution time (WCET) 279–282

X

x86 architecture e61–e62
Xilinx Embedded Developer Kit (EDK) 46
Xilinx toolchain 47–48
Xilinx Virtex-4 FPGA device 96
Xilinx XPower Estimator (XPE) 104–105
XML schema e9

Z

Zero-day exploits e47
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