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by Peter J. Ashenden
The Designer's Guide to VHDL, 2nd Edition
Cover
Title Page
Copyright
Dedication
Foreword
Foreword to the First Edition
Preface
Table of Contents
Chapter 1: Fundamental Concepts
1.1 Modeling Digital Systems
1.2 Domains and Levels of Modeling
1.3 Modeling Languages
1.4 VHDL Modeling Concepts
1.5 Learning a New Language: Lexical Elements and Syntax
Chapter 2: Scalar Data Types and Operations
2.1 Constants and Variables
2.2 Scalar Types
2.3 Type Classification
2.4 Attributes of Scalar Types
2.5 Expressions and Operators
Chapter 3: Sequential Statements
3.1 If Statements
3.2 Case Statements
3.3 Null Statements
3.4 Loop Statements
3.5 Assertion and Report Statements
Chapter 4: Composite Data Types and Operations
4.1 Arrays
4.2 Unconstrained Array Types
4.3 Array Operations and Referencing
4.4 Records
Chapter 5: Basic Modeling Constructs
5.1 Entity Declarations
5.2 Architecture Bodies
5.3 Behavioral Descriptions
5.4 Structural Descriptions
5.5 Design Processing
Chapter 6: Case Study: A Pipelined Multiplier Accumulator
6.1 Algorithm Outline
6.2 A Behavioral Model
6.3 A Register-Transfer-Level Model
Chapter 7: Subprograms
7.1 Procedures
7.2 Procedure Parameters
7.3 Concurrent Procedure Call Statements
7.4 Functions
7.5 Overloading
7.6 Visibility of Declarations
Chapter 8: Packages and Use Clauses
8.1 Package Declarations
8.2 Package Bodies
8.3 Use Clauses
8.4 The Predefined Package Standard
8.5 IEEE Standard Packages
Chapter 9: Aliases
9.1 Aliases for Data Objects
9.2 Aliases for Non-Data Items
Chapter 10: Case Study: A Bit-Vector Arithmetic Package
10.1 The Package Interface
10.2 The Package Body
10.3 An ALU Using the Arithmetic Package
Chapter 11: Resolved Signals
11.1 Basic Resolved Signals
11.2 IEEE Std_Logic_1164 Resolved Subtypes
11.3 Resolved Signals and Ports
11.4 Resolved Signal Parameters
Chapter 12: Generic Constants
12.1 Parameterizing Behavior
12.2 Parameterizing Structure
Chapter 13: Components and Configurations
13.1 Components
13.2 Configuring Component Instances
13.3 Configuration Specifications
Chapter 14: Generate Statements
14.1 Generating Iterative Structures
14.2 Conditionally Generating Structures
14.3 Configuration of Generate Statements
Chapter 15: Case Study: The DLX Computer System
15.1 Overview of the DLX CPU
15.2 A Behavioral Model
15.3 Testing the Behavioral Model
15.4 A Register-Transfer-Level Model
15.5 Testing the Register-Transfer-Level Model
Chapter 16: Guards and Blocks
16.1 Guarded Signals and Disconnection
16.2 Blocks and Guarded Signal Assignment
16.3 Using Blocks for Structural Modularity
Chapter 17: Access Types and Abstract Data Types
17.1 Access Types
17.2 Linked Data Structures
17.3 Abstract Data Types Using Packages
Chapter 18: Files and Input/Output
18.1 Files
18.2 The Package Textio
Chapter 19: Case Study: Queuing Networks
19.1 Queuing Network Concepts
19.2 Queuing Network Modules
19.3 A Queuing Network for a Disk System
Chapter 20: Attributes and Groups
20.1 Predefined Attributes
20.2 User-Defined Attributes
20.3 Groups
Chapter 21: Miscellaneous Topics
21.1 Buffer and Linkage Ports
21.2 Conversion Functions in Association Lists
21.3 Postponed Processes
21.4 Shared Variables
A: Synthesis
B: The Predefined Package Standard
C: IEEE Standard Packages
D: Related Standards
E: VHDL Syntax
F: Differences among VHDL-87, VHDL-93 and VHDL-2001
G: Answers to Exercises
References
Index
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Copyright
The Designer’s Guide to VHDL
Second Edition
Morgan Kaufmann
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