F.l Lexical Differences

VHDL-87 uses the ASCII character set, rather than the full ISO character set. ASCII is a subset of the ISO character set, consisting of just the first 128 characters. This includes all of the unaccented letters, but excludes letters with diacritical marks.

VHDL-87 only allows basic identifiers, not extended identifiers. The rules for forming basic identifiers are the same as those for VHDL-93 and VHDL-2001.

The following identifiers, introduced in VHDL-93, are not used as reserved words in VHDL-87. They may be used as identifiers for other purposes, although it is not advisable to do so, as this may cause difficulties in porting the models to VHDL-2001.

In addition, the identifier protected was introduced as a reserved word in VHDL-2001. It may be used for other purposes in VHDL-87 and VHDL-93, but again, it is not advisable to do so.

Bit-string literals may only be used in VHDL-87 as literals for array types in which the elements are of type bit. The predefined type bit_vector is such a type. However, the standard-logic types std_ulogic_vector and std_logic_vector are not.

F.2 Syntactic Differences

The only sequential statements that may be labeled in VHDL-87 are loop statements. The remaining sequential statements, which may not be labeled, are variable assignment, signal assignment, wait, if, case, null, exit, next, assertion, procedure call and return statements. Other syntactic restrictions in VHDL-87 are

An alias declaration in VHDL-87 must include a subtype indication.

The VHDL-87 syntax for file declarations is not a subset of the VHDL-93 and VHDL-2001 syntax. The syntax rule in VHDL-87 is

An attribute specification in VHDL-87 may not name a character literal as an item to be decorated, nor specify the entity class literal, units, group or file. An attribute specification may not include a signature after an item name.

F.3 Semantic Differences

In VHDL-87, the range specified in a slice may have the opposite direction to that of the index range of the array. In this case, the slice is a null slice.

The VHDL-87 language definition does not disallow the keyword bus in the specification of a signal parameter. However, it does not specify whether the kind of signal, guarded or unguarded, is determined by the formal parameter specification or by the actual signal associated with the parameter. Implementations of VHDL-87 make different interpretations. Some require the formal parameter specification to include the keyword bus if the procedure includes a null signal assignment to the parameter. The actual signal associated with the parameter in a procedure call must then be a guarded signal. Other implementations follow the approach adopted in VHDL-93, prohibiting the keyword bus in the parameter specification and determining the kind of the parameter from the kind of the actual signal.

In VHDL-87, files are of the variable class of objects. Hence file parameters in subprograms are specified as variable-class parameters. A subprogram that reads a file parameter should declare the parameter to be of mode in. A subprogram that writes a file parameter should declare the parameter to be of mode out.

In VHDL-87 and VHDL-93, the declarative part of an architecture body is conceptually a continuation of the declarative part of the corresponding entity declaration. Thus it is not permitted to declare two items of the same name, one in the entity declarative part and the other in the architecture declarative part (unless the items can be overloaded). In VHDL-2001, however, the architecture body is conceptually declared inside and at the end of the entity declarative part. This means that, if two items are declared with the same name as described above, the declaration in the architecture body hides the declaration in the entity, according to the normal VHDL visibility rules. One consequence of this change is that the expanded name of an item X declared in an architecture A of entity E is work.E.A.X. In VHDL-87 and VHDL-93, the rules determining the expanded name for X are ill-defined. A further consequence of the change is that it is no longer permissible to declare a subprogram specification without a corresponding body in an entity declaration in VHDL-2001. In VHDL-87 and VHDL-93, the subprogram specification can be declared in the entity, and a corresponding subprogram body can be provided in an architecture body. Again, however, the expanded name for the subprogram is ill-defined.

In VHDL-2001, the default binding rule for component configurations specifies that if no entity is specified, an entity with the same name as the component is sought in the same design library as the design unit in which the instantiated component is declared. The default binding rules in VHDL-87 and VHDL-93 do not specify where the entity should be sought, so different tool vendors have implemented different approaches, compromising the portability of designs.

In VHDL-93, character-literal aliases need not denote enumeration literals, and operator-symbol aliases need not denote functions.

In VHDL-93, the rules governing incremental binding are somewhat unclear and ambiguous. They are clarified in VHDL-2001. A model that is correct in VHDL-2001 should be correct in VHDL-93 (depending on a particular tool vendor’s interpretation of the rules). Some unusual cases that may have worked in VHDL-93 are illegal in VHDL-2001.

In VHDL-93, the predefined function now is declared to be impure. As a consequence, it cannot be used in static expressions, so its value during elaboration is not defined. In VHDL-2001, now is declared to be pure, allowing it to be used in static expressions. Its value is defined to be 0 fs during elaboration of a model. In VHDL-87, all functions are implicitly pure.

In VHDL-87 and VHDL-93, an event on a signal occurs when the value of the signal changes. In VHDL-2001, an event occurs when the old value is not equal to the new value using the predefined “=" operator for the type of the signal. This difference is evident if the signal is of a floating-point type, in which +0.0 and –0.0 are different values but are equal.

VHDL-87 and VHDL-93 do not specify the representation to be used for floatingpoint types, other than to specify the minimum range of –1.0E38 to +1.0E38 and the minimum precision of six decimal digits. VHDL-2001 specifies that 64-bit IEEE format representation be used.

In VHDL-93, the values of the ‘path_name and ‘instance_name attributes are ambiguously defined. Different tools may return different values. In VHDL-2001, the values of the attributes are clarified and augmented to include signatures for subprograms.

In VHDL-87 and VHDL-93, there are significant restrictions on use of buffer-mode ports. These restrictions are summarized on page 617. In VHDL-2001, buffer-mode ports are similar to inout-mode ports, except that the effective value of the port seen within an architecture body is the same as the driving value from that architecture body. This makes buffer-mode ports much more usable.

F.4 Differences in the Standard Environment

The types fiIe_open_kind and file_open_status, the subtype delay_length and the attribute ‘foreign are not declared in std.standard in VHDL-87. The function now returns a value of type time.

Since VHDL-87 uses the ASCII character set, the type character includes only the 128 ASCII characters.

The predefined attributes ‘ascending, ‘image, ‘value, ‘driving, ‘driving_value, ‘simple_name, ‘path_name and ‘instance_name are not provided in VHDL-87.

The logical operator xnor and the shift operators sll, srl, sla, sra, rol and ror are not provided in VHDL-87 and so cannot be declared as overloaded operators. Thus, the VHDL-87 version of the standard-logic package std_logic_164 does not define the xnor operator for standard-logic types.

In VHDL-87, the ‘last_value attribute for a composite signal returns the aggregate of last values for each of the scalar elements of the signal, as opposed to the last value of the entire composite signal.

The VHDL-87 version of the textio package declares the function endline, which is not included in the VHDL-93 or VHDL-2001 versions of the package.

F.5 VHDL-93 Facilities Not in VHDL-87

VHDL-87 does not include report statements, labeled sequential statements (and hence decoration of sequential statements with attributes), postponed processes, shared variables, group templates or groups, aliases for non-data objects, declarative parts in generate statements or file open and close operations.

VHDL-87 does not allow specification of a pulse rejection interval in the delay mechanism part of a signal assignment. Transport delay can be specified using the keyword transport. If it is omitted, inertial delay is assumed, with a pulse rejection interval equal to the inertial delay interval.

VHDL-87 does not allow association of an expression with a port in a port map. VHDL-87 does not allow type conversions in association lists.

VHDL-87 does not allow direct instantiation of an entity or a configuration. Only declared components can be instantiated. They must be bound to design entities using configuration specifications or using component configurations in configuration declarations.

VHDL-87 does not allow incremental binding. It is an error if a design includes both a configuration specification and a component configuration for a given component instance.

F.6 VHDL-2001 Facilities Not in VHDL-87 or VHDL-93

VHDL-87 and VHDL-93 do not include protected types. Shared variables in VHDL-93 can be of any type, but there is no mutual exclusion between processes for reading and writing shared variables. Shared variables are not permitted in VHDL-87.

VHDL-87 and VHDL-93 only allow graphic (printable) characters and format effectors (vertical tab, carriage return, line feed and form feed) in VHDL models, including in comments. VHDL-2001 relaxes this restriction, allowing any characters except format effectors to appear within comments. This permits implementations to interpret characters within comments as other than ISO Latin-1 characters. For example, they may be interpreted as multibyte characters in an Asian character set.

F.7 Features under Consideration for Removal

All versions of VHDL include linkage-mode ports and replacement characters. These features may be removed from the language in subsequent revisions. Designers should avoid using the features in new models.

The replacement characters are alternate characters that may be used in a model if the host computer does not use the ASCII or Latin-1 character set. We do not mention them in this book, on the assumption that such computers are no longer in use.