Cover image for Dedicated Digital Processors: Methods in Hardware/Software Co-Design

Dedicated Digital Processors: Methods in Hardware/Software Co-Design

Author F. Mayer-Lindenberg
Release Date: 2004/02/01
ISBN: 9780470092828
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Book Description

The recent evolution of digital technology has resulted in the design of digital processors with increasingly complex capabilities. The implementation of hardware/software co-design methodologies provides new opportunities for the development of low power, high speed DSPs and processor networks. Dedicated digital processors are digital processors with an application specific computational task.

Dedicated Digital Processors presents an integrated and accessible approach to digital processor design principles, processes, and implementations based upon the author's considerable experience in teaching digital systems design and digital signal processing. Emphasis is placed on presentation of hardware/software co-design methods, with examples and illustrations provided throughout the text. System-on-a-chip and embedded systems are described and examples of high speed real-time processing are given. Coverage of standard and emerging DSP architectures enable the reader to make an informed selection when undertaking their own designs.

  • Presents readers with the elementary building blocks for the design of digital hardware systems and processor networks

  • Provides a unique evaluation of standard DSP architectures whilst providing up-to-date information on the latest architectures, including the TI 55x and TigerSharc chip families and the Virtex FPGA (field-programmable gate array)

  • Introduces the concepts and methodologies for describing and designing hardware

  • VHDL is presented and used to illustrate the design of a simple processor

  • A practical overview of hardware/software codesign with design techniques and considerations illustrated with examples of real-world designs

Fundamental reading for graduate and senior undergraduate students of computer and electronic engineering, and Practicing engineers developing DSP applications.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Contents
  5. Preface
  6. 1: Digital Computer Basics
    1. 1.1 DATA ENCODING
    2. 1.2 ALGORITHMS AND ALGORITHMIC NOTATIONS
    3. 1.3 BOOLEAN FUNCTIONS
    4. 1.4 TIMING, SYNCHRONIZATION AND MEMORY
    5. 1.5 ASPECTS OF SYSTEM DESIGN
    6. 1.6 SUMMARY
    7. EXERCISES
  7. 2: Hardware Elements
    1. 2.1 TRANSISTORS, GATES AND FLIP-FLOPS
    2. 2.2 CHIP TECHNOLOGY
    3. 2.3 CHIP LEVEL AND CIRCUIT BOARD-LEVEL DESIGN
    4. 2.4 SUMMARY
    5. EXERCISES
  8. 3: Hardware Design Using VHDL
    1. 3.1 HARDWARE DESIGN LANGUAGES
    2. 3.2 ENTITIES AND SIGNALS
    3. 3.3 FUNCTIONAL BEHAVIOR OF BUILDING BLOCKS
    4. 3.4 STRUCTURAL ARCHITECTURE DEFINITIONS
    5. 3.5 TIMING BEHAVIOR AND SIMULATION
    6. 3.6 TEST BENCHES
    7. 3.7 SYNTHESIS ASPECTS
    8. 3.8 SUMMARY
    9. EXERCISES
  9. 4: Operations on Numbers
    1. 4.1 SINGLE BIT BINARY ADDERS AND MULTIPLIERS
    2. 4.2 FIXED POINT ADD, SUBTRACT, AND COMPARE
    3. 4.3 ADD AND SUBTRACT FOR REDUNDANT CODES
    4. 4.4 BINARY MULTIPLICATION
    5. 4.5 SEQUENTIAL ADDERS, MULTIPLIERS AND MULTIPLY-ADD STRUCTURES
    6. 4.6 DISTRIBUTED ARITHMETIC
    7. 4.7 DIVISION AND SQUARE ROOT
    8. 4.8 FLOATING POINT OPERATIONS AND FUNCTIONS
    9. 4.9 POLYNOMIAL ARITHMETIC
    10. 4.10 SUMMARY
    11. EXERCISES
  10. 5: Sequential Control Circuits
    1. 5.1 MEALY AND MOORE AUTOMATA
    2. 5.2 SCHEDULING, OPERAND SELECTION AND THE STORAGE AUTOMATON
    3. 5.3 DESIGNING THE CONTROL AUTOMATON
    4. 5.4 SEQUENCING WITH COUNTER AND SHIFT REGISTER CIRCUITS
    5. 5.5 IMPLEMENTING THE CONTROL FLOW
    6. 5.6 SYNCHRONIZATION
    7. 5.7 SUMMARY
    8. EXERCISES
  11. 6: Sequential Processors
    1. 6.1 DESIGNING FOR ALU EFFICIENCY
    2. 6.2 THE MEMORY SUBSYSTEM
    3. 6.3 SIMPLE PROGRAMMABLE PROCESSOR DESIGNS
    4. 6.4 INTERRUPT PROCESSING AND CONTEXT SWITCHING
    5. 6.5 INTERFACING TECHNIQUES
    6. 6.6 STANDARD PROCESSOR ARCHITECTURES
    7. 6.7 SUMMARY
    8. EXERCISES
  12. 7: System-Level Design
    1. 7.1 SCALABLE SYSTEM ARCHITECTURES
    2. 7.2 REGULAR PROCESSOR NETWORK STRUCTURES
    3. 7.3 INTEGRATED PROCESSOR NETWORKS
    4. 7.4 STATIC APPLICATION MAPPING AND DYNAMIC RESOURCE ALLOCATION
    5. 7.5 RESOURCE ALLOCATION ON CROSSBAR NETWORKS AND FPGA CHIPS
    6. 7.6 COMMUNICATING DATA AND CONTROL INFORMATION
    7. 7.7 THE π -NETS LANGUAGE FOR HETEROGENEOUS PROGRAMMABLE SYSTEMS
    8. 7.8 SUMMARY
    9. EXERCISES
  13. 8: Digital Signal Processors
    1. 8.1 DIGITAL SIGNAL PROCESSING
    2. 8.2 DSP ALGORITHMS
    3. 8.3 INTEGRATED DSP CHIPS
    4. 8.4 INTEGER DSP CHIPS – INTEGRATED PROCESSORS FOR FIR FILTERING
    5. 8.5 FLOATING POINT PROCESSORS
    6. 8.6 DSP ON FPGA
    7. 8.7 APPLICATIONS TO UNDERWATER SOUND
    8. 8.8 SUMMARY
    9. EXERCISES
  14. References
  15. Index
3.144.42.196