References

[1] R.K. Brayton, G.D. Hachtel, C.T. McMullen and A.L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984.

[2] J.F. Wakerly, Digital Design, Prentice Hall, 2001.

[3] L. Wanhammer, DSP Integrated Circuits, Academic Press, 1999.

[4] S. Sze, Physics of Semiconductor Devices, John Wiley and Sons Inc., 1982.

[5] C. Mead, Analog VLSI and Neural Systems, Addison-Wesley, 1989.

[6] R.I. Hartley and Keshab K. Parhi, Digit-Serial Computation, Kluwer Academic Publishers, 1995.

[7] K. van Berkel, Handshake Circuits, Cambridge University Press, 1993.

[8] M.A. Nielsen and Isaac L. Chuang, Quantum Computation and Quantum Information, Cambridge University Press, 2000.

[9] H.W. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice-Hall, 1993.

[10] J.P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic Publishers, 1999.

[11] I. Wegener, The Complexity of Boolean Functions, Tübner-Verlag, 1987.

[12] H.F. Mattson, Discrete Mathematics, John Wiley & Sons Ltd, 1993.

[13] A.V. Aho and J.D. Ullman, Foundations of Computer Science, Computer Science Press, 1992.

[14] J.G. Proakis and D.G. Manolakis, Digital Signal Processing, Prentice Hall, 1996.

[15] J. Nievergelt and K. Hinrichs, Algorithms and Data Structures, Prentice Hall, 1993.

[16] R.H. Morelos-Zaragoza, The Art of Error Correcting Coding, Wiley, 2002.

[17] A.M.K. Cheng, Real-Time Systems, Wiley, 2002.

[18] A.W. Appel, Modern Compiler Implementation in Java, Cambridge University Press, 1998.

[19] B.H. Vassos and G.W. Ewing, Analog and Computer Electronics for Scientists, Wiley, 1993.

[20] J. Gruska, Foundations of Computing, Thomson Computer Press, 1997.

[21] ANSI/TIA/EIA-644 (LVDS) and IEEE 1596.3 standards.

[22] A. Sheikholeslami and P.G. Gulag, A survey of circuit innovations in ferroelectric random-access memories, Proc. IEEE, 88 (5), May 2000.

[23] A. Marshall et al., A Reconfigurable Arithmetic Array for Multimedia Applications, HP Laboratories Bristol, [email protected]

[24] S. Hauck, S. Burns, G. Borriello and C. Ebeling, An FPGA for implementing asynchronous circuits, IEEE Design and Test of Computers, 11 (3), 1994.

[25] F. Mayer-Lindenberg, A heterogeneous parallel system employing a configurable interconnection network, PDCS'97, Washington, 1997.

[26]A. Grama, A. Gupta, G. Karypis and V. Kumar, Introduction to Parallel Computing, Addison-Wesley, 1994.

[27] F. Mayer-Lindenberg, Crossbar design for a super FPGA architecture, PACT'1998, Paris, available via [55].

[28] IEEE std 1149.1 (JTAG) testability primer, available from Texas Instruments, www.ti.com

[29] I. Page, Constructing hardware/software systems from a single description, Journal of VLSI Signal Processing, 12 (1), 1996.

[30] P.J. Ashenden, The Designers Guide to VHDL, Morgan Kaufmann Publishers Inc., 1996.

[31] R.H. Perrott, Parallel Programming, Addison-Wesley, 1987.

[32] C.A.R. Hoare, Communicating Sequential Processes, Prentice Hall, 1985.

[33] T. Murata, Petri nets: properties, analysis, applications, proceedings of the IEEE 77 (4), 1989.

[34] G. Berry and G. Gonthier, The ESTEREL Programming Language: design, semantics, implementation, Science of Computer Programming, 19 (2), 87–152, Nov. 1992.

[35] G. de Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

[36] P. Michel, U. Lauther and P. Duzy, The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, 1992.

[37] L. Svensson, Adiabatic switching, in A.P. Chandrakasan and R.W. Brodensen (eds), Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.

[38] S. Kim and M.C. Papaefthymiou, True single-phase adiabatic circuitry, IEEE Transactions on VLSI Systems 9 (1), 2001.

[39] C.J. Myers, Asynchronous Circuit Design, Wiley & Sons, 2002.

[40] F. Kroupa, Phase Lock Loops and Frequency Synthesis, Wiley & Sons, 2003.

[41] E.A. Hall, Internet Core Protocols, O'Reilly Inc., 2000.

[42] Electronic Design Interchange Format, Version 2.0.0, Electronic Indistries Association, Washington, DC, 1987.

[43] Standard 1076.6 for VHDL Register Transfer Level Synthesis, IEEE Standards Departement, New York, 1999.

[44] M.J. Flynn and S.F. Oberman, Advanced Computer Arithmetic Design, Wiley & Sons, 2001.

[45] S. Furber, ARM System-on-a-Chip Architecture, Addison-Wesley, 2000.

[46] O. Mencer, L. Semeria, M. Morf and J.M. Delosme, Application of reconfigurable CORDIC architectures, Journal of VLSI Signal Processing, Kluwer, March 2000.

[47] J.F. Hart, Computer Approximations, Wiley & Sons, 1968.

[48] J.L. Hennessy and D.A. Petterson, Computer Architecture, 3rd edition, Morgan Kaufmann, 2003.

[49] M.M. Mano and C.R. Kime, Logic and Computer Design Fundamentals, Prentice Hall, 2000.

[50] ANSI/VITA26–1998 standard, available from www.myri.com

[51] E. Waingold et al., Baring t all to software: RAW machines, IEEE Computer, 1997.

[52] C.A. Moritz, Hot pages: Software Caching for RAW Microprocessors, MIT/LCS Tech. Memo. LCS-TM-599, August 1999.

[53] S.S. Muchnik, Advanced Compiler Design and Implementation, Morgan Kaufmann, 1997.

[54] D.E. Knuth, The Art of Computer Programming, Vol. 2, Seminumerical Algorithms, 2nd edition, Addison-Wesley, 1981.

[55] www.ti6.tuhh.de

[56] J. Teich, Digital Hardware/Software-Systeme, Springer-Verlag, 1997.

[57] D.H. West, Approximate solution of the quadratic assignment problem, ACM Transactions on Mathematical Software, 9 (4), 461–466, 1983.

[58] J. Castro and N. Nabona, An Implementation of Linear and Nonlinear Multi Commodity Network Flows, European Journal of Operations Research, 92, 37–53, 1996.

[59] C. Ebeling, L. McMurchie, S.A. Hauck and S. Burns, Placement and Routing Tools for the Triptych FPGAs, IEEE Transactions on VLSI, Dec., 473–482, 1995.

[60] S.K. Nag and R.A. Rutenbar, Performance-Driven Simultaneous Placement and Routing for FPGAs, IEEE Trans. on CAD of Integrated Circuits and Systems, 16 (5), May 1997.

[61] S. Haykin, Adaptive Filter Theory, Prentice Hall, 1996.

[62] S.M. Kuo and B.H. Lee, Real-Time Digital Signal Processing, Wiley, 2001.

[63] www.bdti.com

[64] R.O. Nielsen, Sonar Signal Processing, Artech House, Norwood, 1991.

[65] K. Mai, T. Paaske, N. Jayasena, R. Ho, W.J. Dally and M. Horowitz, Smart Memories: A Modular Reconfigurable Architecture, ISCA, 2000.

[66] C. Kozyrakis et al., Scalable processors in the billion-transistor era: IRAM, IEEE Computer, Sept. 1997, 75–78, 1997.

[67] N. Efford, Digital Image Processing Using Java, Addison-Wesley, 2000.

[68] W.W. Peterson and E.J. Weldon, Error Correcting Codes, MIT Press, 1971.

[69] J.D. Morrison and A.S. Clarke, ELLA2000, McGraw-Hill, 1994.

[70] www.SystemC.org

[71] IEEE1284–1994 standard.

[72] J.E. Hopcroft and J.D. Ullman, Introduction to Automata Theory, Languages and Computation, Addison-Wesley, 1979.

[73] PCI Local Bus Specifications, Revision 2.1, PCI Special Interest Group, 1995.

[74] J.D. Foley, A. van Dam, S.K. Feiner and J.F. Hughes, Computer Graphics, Addison-Wesley, 1997.

[75] V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards, Kluwer Academic Press, 1997.

[76] www.eembc.com

[77] F.T. Leighton, Introduction to Parallel Architectures and Algorithms, Morgan Kaufmann, 1992.

[78] N. Biggs, Algebraic Graph Theory, Cambridge University Press, 1974.

[79] M. Garzon, Analysis of Models of Massive Parallelism, Springer-Verlag, 1995.

[80] T. Toffoli and N. Margolus, Cellular Automata Machines, MIT Press, 1987.

[81] K. Dieffendorff, P.D. Dubey, R. Hochsprung and H. Scales, AltiVec extension to PowerPC accelerates media processing, IEEE Micro, March/April 2000.

[82] I. Koren, Computer Arithmetic Algorithms, Prentice Hall, 1993.

[83] S.W. Golomb, Shift Register Sequences, Aegean Park Press, 1982.

[84] P.M. Athanas and H.F. Silverman, Processor reconfiguration through instruction-set metamorphosis, IEEE Computer, March 1993.

[85] H.-O. Peitgen and P.H. Richter, The Beauty of Fractals, Springer-Verlag, 1986.

[86] F. Mayer-Lindenberg, A parallel computer based on simple DSP modules, Microprocessing and Microprogramming 41, 1995.

[87] A. Goscinski, Distributed Operating Systems, Addison-Wesley, 1991.

[88] G. Tel, Introduction to Distributed Algorithms, Cambridge University Press, 2000.