Contents
1.1.2 Code Conversions and More Codes
1.2 Algorithms and Algorithmic Notations
1.2.1 Functional Composition and the Data Flow
1.2.2 Composition by Cases and the Control Flow
1.3.1 Sets of Elementary Boolean Operations
1.3.2 Gate Complexity and Simplification of Boolean Algorithms
1.3.3 Combined and Universal Functions
1.4 Timing, Synchronization and Memory
1.4.1 Processing Time and Throughput of Composite Circuits
1.4.2 Serial and Parallel Processing
1.5.1 Architectures for Digital Systems
2.1 Transistors, Gates and Flip-Flops
2.1.1 Implementing Gates with Switches
2.1.2 Registers and Synchronization Signals
2.1.3 Power Consumption and Related Design Rules
2.1.4 Pulse Generation and Interfacing
2.2.2 Semiconductor Memory Devices
2.2.3 Processors and Single-Chip Systems
2.2.4 Configurable Logic, FPGA
2.3 Chip Level and Circuit Board-Level Design
2.3.1 Chip Versus Board-Level Design
2.3.3 Configurable Boards and Interconnections
3.3 Functional Behavior of Building Blocks
3.4 Structural Architecture Definitions
3.5 Timing Behavior and Simulation
4.1 Single Bit Binary Adders and Multipliers
4.2 Fixed Point Add, Subtract, and Compare
4.3 Add and Subtract for Redundant Codes
4.5 Sequential Adders, Multipliers and Multiply-Add Structures
4.8 Floating Point Operations and Functions
5.2 Scheduling, Operand Selection and the Storage Automaton
5.3 Designing the Control Automaton
5.4 Sequencing with Counter and Shift Register Circuits
5.5 Implementing the Control Flow
6.1 Designing for ALU Efficiency
6.1.1 Multifunction ALU Circuits
6.2.1 Pipelined Memory Accesses, Registers, and the Von Neumann Architecture
6.2.2 Instruction Set Architectures and Memory Requirements
6.2.3 Caches and Virtual Memory, Soft Caching
6.3 Simple Programmable Processor Designs
6.3.1 CPU1 – The Basic Control Function
6.3.2 CPU2 – An Efficient Processor for FPGA-based Systems
6.4 Interrupt Processing and Context Switching
6.5.1 Pipelining Input and Output
6.5.2 Parallel and Serial Interfaces, Counters and Timers
6.5.4 Interfaces and Memory Expansion for the CPU2
6.6 Standard Processor Architectures
6.6.1 Evaluation of Processor Architectures
6.6.3 A High-Performance Processor Core for ASIC Designs
6.6.4 Super-Scalar and VLIW Processors
7.1 Scalable System Architectures
7.1.1 Architecture-Based Hardware Selection
7.1.2 Interfacing Component Processors
7.1.3 Architectures with Networking Building Blocks
7.2 Regular Processor Network Structures
7.3 Integrated Processor Networks
7.4 Static Application Mapping and Dynamic Resource Allocation
7.5 Resource Allocation on Crossbar Networks and FPGA Chips
7.6 Communicating Data and Control Information
7.7 The π-Nets Language for Heterogeneous Programmable Systems
7.7.1 Defining the Target System
7.7.2 Algorithms and Elementary Data Types
7.7.3 Application Processes and Communications
7.7.4 Configuration and Reconfiguration
7.7.7 Architectural Support for HLL Programming
8.1.1 Analog-to-Digital Conversion
8.2.3 Fast Convolution and Correlation
8.2.4 Building Blocks for DSP Algorithms
8.4 Integer DSP Chips – Integrated Processors for FIR Filtering