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by F. Mayer-Lindenberg
Dedicated Digital Processors: Methods in Hardware/Software Co-Design
Cover Page
Title Page
Copyright
Contents
Preface
1: Digital Computer Basics
1.1 DATA ENCODING
1.2 ALGORITHMS AND ALGORITHMIC NOTATIONS
1.3 BOOLEAN FUNCTIONS
1.4 TIMING, SYNCHRONIZATION AND MEMORY
1.5 ASPECTS OF SYSTEM DESIGN
1.6 SUMMARY
EXERCISES
2: Hardware Elements
2.1 TRANSISTORS, GATES AND FLIP-FLOPS
2.2 CHIP TECHNOLOGY
2.3 CHIP LEVEL AND CIRCUIT BOARD-LEVEL DESIGN
2.4 SUMMARY
EXERCISES
3: Hardware Design Using VHDL
3.1 HARDWARE DESIGN LANGUAGES
3.2 ENTITIES AND SIGNALS
3.3 FUNCTIONAL BEHAVIOR OF BUILDING BLOCKS
3.4 STRUCTURAL ARCHITECTURE DEFINITIONS
3.5 TIMING BEHAVIOR AND SIMULATION
3.6 TEST BENCHES
3.7 SYNTHESIS ASPECTS
3.8 SUMMARY
EXERCISES
4: Operations on Numbers
4.1 SINGLE BIT BINARY ADDERS AND MULTIPLIERS
4.2 FIXED POINT ADD, SUBTRACT, AND COMPARE
4.3 ADD AND SUBTRACT FOR REDUNDANT CODES
4.4 BINARY MULTIPLICATION
4.5 SEQUENTIAL ADDERS, MULTIPLIERS AND MULTIPLY-ADD STRUCTURES
4.6 DISTRIBUTED ARITHMETIC
4.7 DIVISION AND SQUARE ROOT
4.8 FLOATING POINT OPERATIONS AND FUNCTIONS
4.9 POLYNOMIAL ARITHMETIC
4.10 SUMMARY
EXERCISES
5: Sequential Control Circuits
5.1 MEALY AND MOORE AUTOMATA
5.2 SCHEDULING, OPERAND SELECTION AND THE STORAGE AUTOMATON
5.3 DESIGNING THE CONTROL AUTOMATON
5.4 SEQUENCING WITH COUNTER AND SHIFT REGISTER CIRCUITS
5.5 IMPLEMENTING THE CONTROL FLOW
5.6 SYNCHRONIZATION
5.7 SUMMARY
EXERCISES
6: Sequential Processors
6.1 DESIGNING FOR ALU EFFICIENCY
6.2 THE MEMORY SUBSYSTEM
6.3 SIMPLE PROGRAMMABLE PROCESSOR DESIGNS
6.4 INTERRUPT PROCESSING AND CONTEXT SWITCHING
6.5 INTERFACING TECHNIQUES
6.6 STANDARD PROCESSOR ARCHITECTURES
6.7 SUMMARY
EXERCISES
7: System-Level Design
7.1 SCALABLE SYSTEM ARCHITECTURES
7.2 REGULAR PROCESSOR NETWORK STRUCTURES
7.3 INTEGRATED PROCESSOR NETWORKS
7.4 STATIC APPLICATION MAPPING AND DYNAMIC RESOURCE ALLOCATION
7.5 RESOURCE ALLOCATION ON CROSSBAR NETWORKS AND FPGA CHIPS
7.6 COMMUNICATING DATA AND CONTROL INFORMATION
7.7 THE π -NETS LANGUAGE FOR HETEROGENEOUS PROGRAMMABLE SYSTEMS
7.8 SUMMARY
EXERCISES
8: Digital Signal Processors
8.1 DIGITAL SIGNAL PROCESSING
8.2 DSP ALGORITHMS
8.3 INTEGRATED DSP CHIPS
8.4 INTEGER DSP CHIPS – INTEGRATED PROCESSORS FOR FIR FILTERING
8.5 FLOATING POINT PROCESSORS
8.6 DSP ON FPGA
8.7 APPLICATIONS TO UNDERWATER SOUND
8.8 SUMMARY
EXERCISES
References
Index
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