Embedded and fan‐out wafer‐level packaging (FO‐WLP) are new electronic packaging technologies that have entered the market over the last 10 years due to a drive for low cost, high reliability, and large‐scale integration of semiconductor devices for mobile, automotive, Internet of things (IoT), and medical markets. These new packaging technologies also address other electronic packaging challenges, including mechanical, materials, thermal, and electrical performance.

When designing an electronic package, there are many material challenges to consider, both in the semiconductor die and in the package. The die may have fragile low dielectric and extreme low dielectric constant interlayer dielectric (ILD) materials that must be taken into account. The stress on these layers must be minimized to prevent cracking or delamination of the passivation. One solution to avoiding these potential failure modes is to eliminate the interconnection between the device and substrate, reducing the stress on the semiconductor die. The pitch of the interconnects on the die is another consideration. For traditional packaging solutions such as wire bond and flip chip, the pitch of the wire bonds or flip‐chip solder interconnects can be limited, such as in wire‐bond packaging; the ability to wire bond or route the interconnection in the substrate, for example, can limit the minimum pitch. In flip‐chip packaging, the ability to chip attach at fine pitch, to underfill fine‐pitch interconnects, and to route the substrate at fine pitches can be a limiter. Again, it is best to eliminate the interconnections altogether to minimize the pitch. Flip‐chip packaging also has the challenge of introducing low coefficient of thermal expansion (CTE) and high modulus substrate materials. These materials are required in order to minimize warpage in a package. Also, low CTE mold materials must be used to mitigate the stress introduced due to the CTE mismatch between the device, the substrate, and the interconnect material. A solution that eliminates the substrate and the interconnect, such as embedded and FO‐WLP, is preferred. These material challenges have led to the development of substrate‐ and interconnect‐free embedded packages.

The continued demand for ever thinner electronic packages has led to mechanical challenges. A simple method of thinning a package is to start with a thinner die. However, the latest wafer technologies are strain‐engineered, so any bending of thin devices (<80 μm) can impact device performance. Furthermore, the handling of thin die can be difficult and costly, so it is often preferable to avoid the use of thinned die. Packaging technologies like embedded and FO‐WLP enable a low package height by eliminating the substrate while still being able to use die thicker than 80 μm.

Modern electronic packages must also be highly reliable. The CTE mismatch between the materials in a package, including the mold compound, substrate, and interconnect, can induce mechanical stress. Minimizing this mismatch is one key to good package reliability; however, the elimination of interconnects and substrates can also eliminate these stresses. Warpage control is another important consideration. Warpage can be managed through the properties of the materials that make up the package, such as CTE, glass transition temperature (T_g), and modulus. The adjustment of core, prepreg, and solder resist layer thicknesses and copper density can also help manage warpage. However, elimination of the substrate altogether can eliminate the risk of warpage. Thus, these and other mechanical challenges can be addressed with embedded and FO‐WLP packaging.

During the electrical design of an electronic package, signal integrity, power distribution, and any functional partitioning must be taken into account. The package should not degrade the electrical performance of the device. Thus, interconnect lengths must be short to minimize parasitics in the package, a low resistance is required to support the on‐chip power network, voltage drops (V = IR) must be small, multiple parallel power and ground pins are necessary, and dummy metal planes are introduced for grounding. Since embedded and FO‐WLP packaging can eliminate substrates and interconnects allowing for shorter packaging routing circuitry from die to solder ball, these electrical concerns are addressed.

In packaging, poor thermal paths, no airflow, closed systems, and 3D integration all exacerbate thermal issues. The thermal resistances of the epoxy mold compound, device, interconnect, substrate, and the ball grid array (BGA) for BGA and chip‐scale packages (CSP) must be taken into account. The junction temperature or operating temperature of the device (T_j) must be minimized for a given power to prevent device failure. The thermal paths of embedded and FO‐WLP packages are minimized by elimination of the substrate.

In embedded and FO‐WLP packaging, a device is embedded into an organic laminate substrate or mold compound, respectively. There are many types of embedded and FO‐WLP packages offered in the market today, such as extended wafer‐level ball grid array (eWLB), redistributed chip package (RCP), M‐Series, integrated fan‐out (InFO), embedded chip package (ECP), and semiconductor embedded in substrate (SESUB), to name a few. In eWLB, RCP, M‐Series, and InFO, the dies are molded into a wafer form, and then wafer‐level packaging (WLP)‐like buildup technologies are used to create the redistributed copper circuitry. These types of packages are generally referred to as fan‐out wafer‐level packages (FO‐WLP) because the BGA is fanned out from the original device’s footprint, unlike WLP where the BGA pins are constrained by the area of the die. In ECP and SESUB packages, the device is placed on a sheet of copper, and the substrate layers are built up onto the die using traditional organic laminate substrate technologies. These types of packages will be referred to here as embedded packaging.

FO‐WLP and embedded packages differ from wire‐bond and flip‐chip packages because they do not require a wire‐bond or solder bump interconnect to the die. Embedded and FO‐WLP also do not require a lead frame or organic laminate substrate, because the substrate is built onto the device to create the circuitry that connects the device to the outside world. By eliminating the interconnects, these packages provide excellent electrical performance because the shorter circuitry in the embedded and fan‐out wafer‐level package has lower parasitics. Also, eliminating the interconnects eliminates the interconnect stress and thus avoids ILD crack and delamination issues.

FO‐WLP not only eliminates the die interconnect and substrate, resulting in better electrical performance and lower cost, but also provides finer lines and spaces in the buildup circuitry, allowing for better routability. The lines and spaces are finer than typical substrate technologies because the FO‐WLP process uses wafer back‐end fabrication (fab)‐like processes, materials, and equipment, as used in WLP. This is a significant advantage that FO‐WLP has over embedded, as embedded packaging technology uses traditional organic substrate buildup processes, materials, and equipment, resulting in coarser lines and spaces. Also, since FO‐WLP uses fab‐like processes, the yields are much higher than those expected in embedded organic substrate laminate technologies. This is because organic laminate substrates can typically be tested before chip attach, so known good substrates can be identified. However, when building a substrate onto the device, the process must be robust enough to have >99.5% yield; otherwise both the substrate and the package are scrapped. The organic laminate substrate industry processes, materials, and equipment were not designed to provide such high yields. However, the one advantage embedded has over FO‐WLP is its low cost, as it does not utilize high‐end fab‐like processes or materials.

Embedded and fan‐out wafer‐level packaging serve the same purpose as traditional electronic packaging such as flip‐chip or wire‐bond packaging: they provide a method to connect a device to the outside world as well as mechanical and environmental protection, and they allow the device to be handled and tested before shipping. One critical advantage embedded and fan‐out wafer‐level packaging have over WLP is the ability to perform testing in singulated package form. Since a WLP is a true chip‐sized package made of entirely silicon, it cannot be tested using a traditional handler kit and automated tester. WLP is typically tested in wafer form with a prober, and thus the singulation process may introduce defects that cannot be screened out. Another advantage of embedded and fan‐out wafer‐level packaging is that the footprint of an embedded or fan‐out wafer‐level package can be smaller than that of a flip‐chip and wire‐bond package due to the finer design rules (narrower lines and spaces) provided by the fab‐like processing. The thickness can also be reduced. Finally, as discussed above, embedded and fan‐out wafer‐level packaging offer many other advantages, such as improved electrical and thermal performance, good warpage control, and improved reliability due to lack of CTE mismatch.

This book consolidates much of the past 15 years’ activity within this amazing new field of packaging technology, starting with a “History of Embedded and Fan‐Out Packaging Technology” by Michael Töpper et al. of Fraunhofer IZM, followed by “FO‐WLP Market and Technology Trends” by E. Jan Vardaman of TechSearch International. Sections are dedicated to chip‐first FO‐WLP, chip‐last FO‐WLP, embedded die packaging, material challenges, equipment challenges, and resulting technology fusions.

The chip‐first FO‐WLP section begins with a chapter on the first chip‐first FO‐WLP in the market, called eWLB, by Thorsten Meyer of Infineon Technologies and our coeditor Steffen Kroehnert of Amkor Technology Holding B.V. The section continues with the extension of eWLB to package‐on‐package (PoP) solutions by S. W. Yoon of STATS ChipPAC. Further chip‐first FO‐WLP chapters include nepes Corporation’s fan‐out packaging technology by Jay Kim and Deca Technologies’ M‐Series™ technology by Tim Olson et al. A new technology called chip‐last, represented by Amkor Technology’s silicon wafer integrated fan‐out technology (SWIFT®), is then presented by Ron Huemoeller and Curtis Zwenger.

The embedded die packaging section describes the embedding of die using printed circuit board processes and materials technology represented by Schweizer Electronic (i²Board and p²Pack) in chapters by Thomas Gottwald et al., J‐Devices (fan‐out panel‐level package [FO‐PLP]) by Akio Katsumata et al., and Infineon Technologies (Blade) by Boris Plikat and Thorsten Scharf. This section also includes a novel idea of embedding a die in a silicon wafer by Daquan Yu of Huatian Technology Electronics Co.

The emergence of FO‐WLP required innovation in both epoxy mold compound materials and low temperature cure dielectric materials. Chapters regarding these challenges are included in the materials section of the book. Katsushi Kan et al. from Nagase describe the complexity of liquid mold compounds for the FO‐WLP market. Low cure dielectric material development is addressed by Ioan Matthews et al. of HD MicroSystems and Stefan Vanclooster et al. of Fujifilm Electronic Materials.

In the equipment section, pick and place equipment challenges are discussed by Hugo Pristauz et al. of BESI and Nelson Fan et al. of ASM Pacific Technology. Then, Edward Fuergut of Infineon Technologies and Hirohito Oshimori et al. of Apic Yamada Corporation describe the difficulties in creating a compression mold solution for FO‐WLP. ASM Pacific Technology also describes their compression mold challenges in their chapter. Chris Jones of SPTS Technologies Ltd. and Ricardo Gaio et al. of Amkor Technology Portugal S.A. also describe the challenges of designing a physical vapor deposition (PVD) (or sputtering) machine for FO‐WLP in which epoxy‐molded wafers instead of silicon wafers are placed into high vacuum chambers. Additional equipment chapters describing unique solutions for embedded and FO‐WLP packaging are also included. Habib Hichri et al. of SUSS MicroTec Photonic Systems, Inc. describe “excimer laser ablation for patterning of ultrafine routings,” and Thomas Uhrmann and Boris Považay of EV Group give details about “temporary carrier technologies for eWLB and RDL‐first fan‐out wafer‐level packages.”

Finally, technology fusions resulting from research in the embedded and FO‐WLP market are described in the last section, including S. W. Yoon’s chapter on encapsulated wafer‐level chip‐scale package (eWLCSP) technology currently in production at STATS ChipPAC. Ravi Mahajan et al. of Intel then describe their embedded multi‐die interconnect bridge (EMIB) for high‐end applications. Finally, Muhannad Bakir at the Georgia Institute of Technology writes “Interconnection Technology Innovations in 2.5D Integrated Electronic Systems.”

We hope you find this book on embedded and FO‐WLP technologies – the first of its kind – educational and enjoy reading it as much as we enjoyed writing it.