© Jiewen Yao and Vincent Zimmer 2020
J. Yao, V. ZimmerBuilding Secure Firmwarehttps://doi.org/10.1007/978-1-4842-6106-4_5

5. Firmware Resiliency: Recovery

Jiewen Yao1  and Vincent Zimmer2
(1)
Shanghai, China
(2)
Issaquah, WA, USA
 

This chapter describes a critical aspect of platform resiliency – recovery. This supports the availability aspect of the CIA triad of confidentiality, integrity, and availability. If the platform detects that the integrity of components, including code or data, is broken, the platform needs to restore the components to a known good state. This process is called recovery. It is the last element in firmware resiliency. The recovery process is a variant of the update process. It updates the system to an old state. As such, all guidelines for the update should be followed in the recovery process, such as signature checking and version checking.

Image Recovery

The recovery process is performed by the root-of-trust for recovery (RTRec) or the Chain-of-Trust for recovery (CTRec). The RTRec and CTRec shall be the immutable code or the known good code. If the RTRec or CTRec cannot be established, then the end user must perform a manual recovery. For example, if the whole flash chip is corrupt or erased, even the first CPU instruction fetched is an invalid opcode. In this case, the end user might have to attach a flash programmer to the flash chip and burn a new image or be required to ship the machine back to the manufacturer for repair.

RTRec Selection and Recovery Policy

The RTRec and CTRec may be the same as the root-of-trust for detection (RTD) and Chain-of-Trust for detection (CTD), or they may be different. Based upon the relationship between the RTRec and RTD, the platform may use different ways to perform the recovery (see Table 5-1).
Table 5-1

Recovery Policy

Mechanism

RTRec/RTD Relationship

Detail

Example

Immediate recovery

The RTRec and RTD are the same.

Once the RTD detects the unauthorized change, the RTD invokes the RTRec, and the RTRec starts doing recovery immediately.

EDK II signed recovery.

coreboot recovery.

HP Sure Start.

Project Cerberus.

Intel PFR cold reboot.

Reset recovery

The RTRec runs before the RTD/CTD.

Once the RTD/CTD detects the unauthorized change, the RTD/CTD sets the platform state to be “recovery mode” and resets the system. On the next boot, the RTRec detects the “recovery mode” and does the recovery.

Intel PFR warm reboot.

Downgrade boot and late recovery

The RTRec runs after the RTD/CTD.

Once the RTD/CTD detects the unauthorized change, the RTD/CTD continues booting the system with a detectable indicator on the verification failure, such as a TPM measurement. The platform RTRec may have a chance to recover the system to a normal state later.

Intel Boot Guard with the enforcement policy set as timeout shutdown.

Halt and out-of-band recovery

The RTD and RTRec are in different domains.

Once the RTD/CTD detects the unauthorized change, the RTD/CTD halts the system immediately without any in-band recovery capability. As such, only out-of-band (OOB) RTRec can recover the system.

Intel Boot Guard with the enforcement policy set as immediate shutdown.

Recovery Image Selection

The recovery image might be an immutable ROM on the system, a last known good image on the system provided by the manufacturer vendor, or an image saved by the end user. If the recovery image is mutable, the recovery image update must follow the same process as the normal image update, such as image protection, signature check, version check, and so on (see Table 5-2).
Table 5-2

Recovery Image Selection

Mechanism

Pros

Cons

Immutable ROM

There is no way to break the immutable ROM.

If immutable ROM has a vulnerability, this vulnerability is permanent.

Last known good image

The platform keeps the recovery image up to date automatically, and the platform ensures there is no known security vulnerability in the recovery image.

It is hard to define what the “good” means. Maybe the platform saves an image which has some functional issue.

End user saved image

End user has the freedom to decide which image to use for recovery.

End user interaction is required. The end user may select a vulnerable image.

The solution to automatically save the last known good image poses a challenge because the definition of “good” cannot be precisely defined. Can we say the new image is “good” when the firmware successfully transfers to the OS loader? Or when the OS is fully booted up? Or when the OS device drivers are all started up? Or when the business application starts working in the OS? Or when the OS has passed a certification test? There is no universal answer, and the platform designer needs to make a decision to balance the OS functionality needed to prove the system is in a good state.

Recovery Image Location

The recovery image might be in the system ROM such as a flash device, on a non-removable disk such as a hard drive, or on a removable disk such as a USB key or CDROM/DVDROM or transmitted from a remote location via a transport such as a serial port or network or even from an out-of-band management device (see Table 5-3).
Table 5-3

Recovery Image Location

Mechanism

Pros

Cons

Example

Flash ROM

The recovery image is always present.

The cost is higher.

On the same flash device or a different flash device.

Non-removable disk

There is no cost increase.

The recovery image itself needs to be protected, and only allow authorized recovery image update.

Hard drive (hard disk drive (HDD) , solid-state disk (SSD), NVMe, and so on) – hidden partition or system partition.

Removable disk

The recovery image cannot be attacked because it is not attached to the system in a normal boot.

User interaction is required. End user guarantees the correctness of the recovery image.

CDROM/DVDROM, USB key.

Transmitted from remote

There is no need to touch the local machine.

The network driver stack must be in the RTRec. A recovery server needs to be set up.

Network (Ethernet, Wi-Fi, Bluetooth, and so on), serial port.

Transmitted via out-of-band (OOB)

It is easy for remote management.

The OOB engine needs to have flash access.

Baseboard Management Controller (BMC), Manageability Engine (ME).

Case Study

Now, let’s take a look at some real cases for the image recovery.

PCH: Top Swap (TS)

During a normal boot, the silicon will map the two 64 KB top boot blocks of the flash chip to the address [0xE0000, 0xFFFFF). When the CPU starts from the reset vector – 0xF000:0xFFF0 – the CPU can execute the instruction directly on the flash. These same boot blocks are also mapped to [0xFFFE0000, 0xFFFFFFFF) because the typical 16-bit real mode boot block code switches to the 32-bit protected mode immediately to access the whole flash region, which may be bigger than 1 MB. See Figure 5-1.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig1_HTML.png
Figure 5-1

Flash Chip Mapping

Top Swap (TS) is a feature which swaps the top block of the Firmware Hub or SPI flash (also known as boot block) with another location (see Figure 5-2). This is designed to allow safe update of the boot block. When it is enabled, the PCH will invert the address for cycles going to the two top blocks of the flash. For example, if the block size is 64 K, accessing FFFF_0000h–FFFF_FFFFh MMIO address becomes accessing FFFE_0000h–FFFE_FFFFh flash address and vice versa.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig2_HTML.jpg
Figure 5-2

Top Swap Register (Source: Intel 9 Series Chipset PCH Datasheet)

The secure boot block update can be used in the following ways:
  1. 1.

    The firmware backs up the top block to the block below the top (the swap block).

     
  2. 2.

    The firmware enables Top Swap. This will invert the appropriate address bits for the cycles going to the Low Pin Count (LPC) or Serial Peripheral Interface (SPI) bus. This bit is stored in the RTC well.

     
  3. 3.

    The firmware erases the top block and writes the new top block.

     
  4. 4.

    The firmware disables Top Swap.

     
If there is any power failure reset during step 3, the system will boot from the boot block backed up in step 1 and perform the recovery. See Figure 5-3.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig3_HTML.png
Figure 5-3

Flash Chip Mapping with Top Swap Enabled

The BIOS may implement different ways for Top Swap–based recovery to work because the boot block B may control the different code flows. For example, the RTD (such as an ACM or Embedded Controller) may check the boot block A before transferring control. If the RTD finds there is something wrong, the RTD may choose to set the Top Swap and reset the system. On the next boot, the RTD may check the boot block B. If the check passes this time, the boot block B owns the reset vector. It is in recovery mode now. The boot block B may launch the main block B1 from the flash image. The main block B1 may include an external storage driver and load the main block B2 from there. Finally, the main block figures out a way to flash a known good image to boot block A and main block A, clears the Top Swap, and resets the system. Now the next boot becomes the normal boot again. See Figure 5-4 for the flash image layout to support Top Swap recovery.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig4_HTML.png
Figure 5-4

Flash Image Layout to Support Top Swap Recovery

PCH: Boot BIOS Strap (BBS)

Boot BIOS Strap (BBS) is a feature to select where the BIOS boots from (see Figure 5-5). It could be from the LPC bus or SPI bus. The platform manufacturer may choose to connect the flash via the LPC bus or SPI bus. Previous generations even had the capability to boot the BIOS from the PCI bus. If the PCI bus is selected, the top 16 MB of the memory below 4GB (FF00_0000h to FFFF_FFFFh) is accepted by the primary side of the PCI-to-PCI bridge and forwarded to the PCI bus. This allows the system recovery from a plug-in PCI card. For example, if the platform owner finds the whole BIOS region is corrupt, they can set a jumper and plug in a PCI card with a known good BIOS on the card. The jumper may route BIOS accesses to the PCI bus. Once the system boots, the platform owner may update a new image to the BIOS connected to the LPC or SPI bus. This boot from the PCI feature is not present in more recent chipsets.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig5_HTML.jpg
Figure 5-5

Boot BIOS Strap Register (Source: Intel 9 Series Chipset PCH Datasheet)

coreboot Recovery

The coreboot firmware has two partitions – read-only one (including boot block, verstage, and a recovery image) and read-write one (including romstage + ramstage + payload). The read-only partition is the RTD and RTRec. After the boot block sets up the temporary RAM, the verstage tries to verify and load read/write firmware A. If it fails, the firmware tries to verify and load firmware B. If it fails again, it tries to verify and load the recovery firmware. The recovery image is included in the read-only portion; and it has a full copy of romstage, ramstage, and payload for the recovery mode. See Figure 5-6 for the coreboot recovery flash image layout.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig6_HTML.png
Figure 5-6

coreboot Recovery Flash Image Layout

EDK II Signed Recovery

In the EDK II signed recovery solution, the Pre-EFI Initialization (PEI) firmware volume (FV) works as the RTRec. The PEI components check the Driver Execution Environment (DXE) main FV and decide the boot mode. The PEI FV may load a recovery version of the DXE main FV in the recovery boot mode. The recovery DXE main FV can be loaded from external storage, such as HDD, USB key, CDROM, and so on. See Figure 5-7 for EDK II signed recovery flow.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig7_HTML.png
Figure 5-7

EDK II Signed Recovery Flow

Step 0: During system boot, a platform PEI module detects the boot mode and sets BOOT_IN_RECOVERY_MODE if recovery is required. It also installs the EFI_PEI_BOOT_IN_RECOVERY_MODE_PPI so that modules with the recovery dependency are dispatched in recovery mode.

Step 1: As the final step of the PEI phase, the DxeIpl tries to load the recovery image via EFI_PEI_RECOVERY_MODULE_PPI.LoadRecoveryCapsule if the system boot mode is in BOOT_IN_RECOVERY_MODE.

Step 2: A RecoveryModule is the producer of EFI_PEI_RECOVERY_MODULE_PPI. It consumes EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.

Step 3: The PEI file system driver is the producer of the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI. In EDK II, these modules include CDROM/DVDROM (CdExpressPei) and FAT file system (FatPei). They consume the EFI_PEI_RECOVERY_BLOCK_IO2_PPI.

Step 4: The PEI block I/O storage driver is the producer of EFI_PEI_RECOVERY_BLOCK_IO2_PPI. In EDK II, these modules are USB (UsbBotPei), HDD (IdeBusPei), eMMC (EmmcBlockIoPei), and UFS (UfsBlockIoPei). These PEIMs are the modules to load the recovery capsule image from a storage device into memory.

Step 5: Once the RecoveryModule retrieves the recovery image, it will parse and verify the recovery image to check the integrity and extract the firmware volume for the DXE phase.

Step 6: Finally, the RecoveryModule installs the extracted firmware volume (FV) for DXE. It builds EFI_HOB_FIRMWARE_VOLUME and installs EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI.

Then DxeIpl can find the DXE core and DXE main FV and transfer control to DXE. Later, the DXE phase flash update driver updates the DXE FV in the flash region to finish the recovery.

HP Sure Start

The coreboot recovery and EDK II signed recovery solution assume that the RTD/RTRec and other mutable images are in one single device. It simplifies the board design and lowers the cost. However, in some cases, there is no guarantee that the boot block is really read-only. It can still be updatable. As such, the previous solution does not work.

HP Sure Start technology includes a standalone chip as the root-of-trust for protection, detection, and recovery. This chip has the self-healing capability, which provides automatic recovery from the corruption of the whole BIOS as well as firmware protection against permanent denial of service (PDoS) attacks. After power-on, the HP Sure Start chip checks the boot block. If the boot block is corrupted, the HP Sure Start chip recovers it from a known good image. The boot block then checks the rest of the system BIOS image. See Figure 5-8 for the flow.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig8_HTML.png
Figure 5-8

HP Sure Start Detection and Recovery Flow

Project Cerberus

Cerberus Security Architecture is a server platform solution for protection, detection, and recovery defined by Open Compute Project (OCP). Its scope extends from the host firmware to the baseboard management controller (BMC) firmware. As discussed in Chapter 4, the Cerberus chip connects to the BIOS flash chip and the BMC flash chip. Each flash chip includes three areas: active image, recovery image, and staging image (see Figure 5-9). If the active firmware cannot boot, the Cerberus chip can trigger the recovery process to load the image from the recovery image to overwrite the corrupted active firmware. The recovery can be triggered via the “Recover Image” command as well. See Table 5-4. Of course, the Cerberus chip needs to protect the recovery image from tampering by the active image.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig9_HTML.png
Figure 5-9

Cerberus Image Layout

Table 5-4

Cerberus RoT Command List

Register Name

RoT

Description

Recovery firmware

Platform Active (PA) RoT/Active Component (CA) RoT

Restore Firmware Index using backup.

Prepare Recovery Firmware

Platform Active (PA) RoT/Active Component (CA) RoT

Prepare storage for recovery image.

Update Recovery Firmware

Platform Active (PA) RoT

Updates the recovery image.

Activate Recovery Firmware

Platform Active (PA) RoT

Activates the received recovery image.

Table 5-5

Recovery Configuration Selection

Mechanism

Pros

Cons

Manufacture default

There is no way to break the manufacturer default value, which should be stored in the immutable region or within the recovery image region.

If the manufacturer default value is not a secure configuration, it has to be updated together with the whole recovery image update.

Last known good configuration

The platform keeps the last configuration data automatically.

Similar to the last known good image, it is hard to define what the “good” means.

End user saved configuration

End user has freedom to decide which configuration to recover.

End user may save a non-bootable configuration by mistake.

Besides the BIOS and BMC firmware, the Cerberus root-of-trust (RoT) commands can be used to support device firmware update and recovery image update, once the Cerberus finds the device component firmware has been corrupted.

ARM Trusted Boot Firmware

The recovery implementation in ARM Trusted-Firmware-A is platform specific. A platform may choose to boot to a valid flash image saved in the other position of the flash image, if a recovery boot is required. This action may be combined with a firmware update flow to use the recovery image to overwrite the active image region.

ARM Trusted-Firmware-M uses the swap mechanism for update, as we discussed in Chapter 3. This swap mechanism is also used for recovery. If the new image boots fail, the system does a reboot, reverts to an old stable image, and sets the rollback flag. See Figure 5-10.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig10_HTML.png
Figure 5-10

ARM Trusted-Firmware-M Swap Mechanism for Update and Recovery

Attack and Mitigation

Now, let’s take a look at some real cases for the attacks to the image recovery and mitigation of those attacks.

Recovery Image Attack

Since the recovery image is another BIOS image, all hardware attack for the working image may also be applied to the recovery image. If the recovery image is in flash, the flash region must be protected. If the recovery image is on the system partition of the non-removable disk, it is more challenging. This partition must be a protected partition or a hidden partition.

Updating the recovery image is another attack surface. All the rules applied to active image update must be applied to recovery image update too, such as authentication check, version check, non-bypassability, and so on.

Image Downgrade Attack

The recovery image must not have any known security vulnerability. It might be different from the active image and not have the same full functionality as the active image since the major function of the recovery image is to recover the system to a state that can update to a new active image.

When an active image is updated, the platform owner must decide if the vulnerability exists in the recovery image too. If the recovery image has a similar security issue, the recovery image must also be updated along with the active image. Without that, the attack may just trigger the recovery process and activate a vulnerable environment.

Hardware Configuration Attack

The hardware configuration, such as Top Swap (TS) or Boot BIOS Strap (BBS), may help the recovery process. However, the improper usage of this advanced setting may become an attack surface. If those registers are not locked, the attacker can switch the TS or BBS to let the system boot from the other source controlled by the malware. All hardware settings related to security must be locked before the system exits the platform manufacturer authentication phase.

Configuration Recovery

Besides the executable code, the configuration data may also be tampered with or corrupted. If that is detected, the configuration data also needs to perform recovery.

Recovery Configuration Selection

The configuration might be the manufacturer default, a last known good configuration saved by the manufacturer/vendor, or a configuration saved by the end user. If the recovery configuration is mutable, the recovery configuration update must follow the same process as the normal configuration update process. See Table 5-5.

Usually, a manufacturer provides the default configuration value. If the configuration is not end user changeable such as Vital Production Data (VPD), it should be treated as a part of the recovery image instead of the recovery configuration. If the configuration is end user changeable, such as setup variable policy data or secure boot configuration data, there could be two sets of default values – one is platform manufacturer default, and the other is the end user saved configuration in the setup page. The end user may choose to load the end user saved configuration in the setup page or to load the platform manufacturer default. Figure 5-11 shows the flow.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig11_HTML.png
Figure 5-11

Configuration Recovery

Attack and Mitigation

Now, let’s take a look at some real cases for the attacks to the configuration recovery and mitigation of those attacks.

Configuration Data Attack

Most of the attacks to the recovery configuration are similar to the attacks to the recovery image. The configuration data itself shall be protected.

Configuration Rollback Attack

If the default configuration is not secure enough and the current configuration updates that, the attacker may choose to trigger a recovery to load the default insecure configuration. For example, the default image may include a secure boot forbidden database – dbx1. If the platform appends the new secure boot forbidden database into dbx1, then the current forbidden database – dbx2 – includes more entries than the default forbidden database, dbx1. In order to allow the vulnerable signed image to run, the attacker needs to figure out a way to remove the new entry from the secure boot forbidden database. With recovery enabled, they may trigger a platform recovery to load the manufacturer’s default configuration – dbx1. Figure 5-12 shows the concept.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig12_HTML.png
Figure 5-12

Configuration Rollback Attack

In order to mitigate such an attack, if a platform needs any configuration update to a secure state, the platform must update the current configuration, the saved configuration, and the default configuration.

Watchdog

In the case of a normally operating environment, we expect that the root-of-trust for detection (RTD) can detect instances of firmware corruption and subsequently trigger or initiate the recovery process. However, in some special cases, the firmware may hang due to a configuration data attack which is not detected by the RTD. In the latter scenario, we still want to have an auto recovery mechanism. A watchdog is a hardware device to assist the recovery process in such a case to resist the denial-of-service attack. See Figure 5-13 for a typical watchdog design.
../images/488723_1_En_5_Chapter/488723_1_En_5_Fig13_HTML.png
Figure 5-13

Watchdog

In the resiliency solution, the watchdog should be part of the resiliency engine, such as the platform Root-of-Trust. The watchdog should be started during the platform root-of-trust and should not be stopped or tampered by any exposed vulnerability in the system. In a normal scenario, the system should rearm the watchdog periodically to prevent it from timing out. If the system runs into a corrupted state or hangs, then the system will fail to rearm the watchdog. When the timer elapses, the watchdog will generate a reset signal to initiate the recovery action. This is the firmware equivalent of a “dead man’s switch.”

Currently, the watchdog is widely adopted in computer platforms, such as X86 systems or ARM systems. However, not all of them can be used in the resiliency usage because of the special requirement that the watchdog should be tamper-resistant against a vulnerable resiliency target. A cyber resiliency watchdog should be a latchable watchdog or authenticated watchdog. Only the root-of-trust for resiliency (RTRes) can control it.

Summary

In this chapter, we discussed the third part of the firmware resiliency – recovery. We covered both image recovery and configuration recovery. In the next chapter, we will discuss the OS/loader resiliency.

References

Conference, Journal, and Paper

[P-1] Jiewen Yao, Vincent Zimmer, “A Tour Beyond BIOS- Capsule Update and Recovery in EDK II,” Intel whitepaper, 2016, available at https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Security-White-Papers

[P-2] Jim Mann, “System Firmware – The Emerging Malware Battlefront,” NIST Computer Security Resource Center, 2015, available at https://csrc.nist.gov/CSRC/media/Presentations/System-Firmware-The-Emerging-Malware-Battlefront/images-media/day1_trusted-computing_100-150.pdf

[P-3] Andrew Thoelke, “ARM Trusted Firmware for ARMv8-A,” Linaro Connect US 2013, available at www.slideshare.net/linaroorg/arm-trusted-firmareforarmv8alcu13

[P-4] Andrew Thoelke, “Adopting ARM Trusted Firmware,” Linaro Connect Asia 2014, available at www.slideshare.net/linaroorg/lca14-102-adoptingarmtrustedfirmware

[P-5] Dan Handley, “ARM Trusted Firmware – from Enterprise to Embedded,” Linaro Connect Las Vegas 2016, available at http://s3.amazonaws.com/connect.linaro.org/las16/Presentations/Thursday/LAS16-402%20-%20Arm-TF%20From%20Embedded%20To%20Enterprise%20v1.0%20%281%29.pdf

[P-6] Dan Handley, Charles Garcia-Tobin, “Trusted Firmware Deep Dive,” available at www.linaro.org/app/resources/Connect%20Events/Trusted_Firmware_Deep_Dive_v1.0_.pdf

[P-7] Sun Bing, “BIOS Boot Hijacking and VMware Vulnerabilities Digging,” in Power Of Community 2007, available at http://powerofcommunity.net/poc2007/sunbing.pdf

[P-8] Alexander Ermolov, “Safeguarding Rootkits: Intel Boot Guard,” in Zeronights 2016, available at https://github.com/flothrone/bootguard/blob/master/Intel%20BootGuard%20final.pdf

[P-9] Alexander Ermolov, “Safeguarding Rootkits: Intel Boot Guard, (part2),” in DC 2017, available at https://github.com/flothrone/bootguard/blob/master/Intel%20BG%20part2.pdf

[P-10] Ronald Aigner, Paul England, Andrey Marochko, Dennis Mattoon, Rob Spiger, Stefan Thom, “Cyber-Resilient Platform Requirements,” Microsoft Whitepaper, 2017, available at www.microsoft.com/en-us/research/publication/cyber-resilient-platform-requirements/

[P-11] Frank Stajano, Ross Anderson, “The Grenade Timer: Fortifying the Watchdog Timer Against Malicious Mobile Code,” in Proceedings of 7th International Workshop on Mobile Multimedia Communications, 2000 available at www.cl.cam.ac.uk/~rja14/Papers/grenade.pdf

Specification and Guideline

[S-1] NIST SP800-193, “Platform Firmware Resiliency Guidelines,” 2018, available at https://csrc.nist.gov/publications/sp800

[S-2] OCP, “Project Cerberus Architecture Overview Specification,” 2018, available at https://github.com/opencomputeproject/Project_Olympus/blob/master/Project_Cerberus

[S-3] OCP, “Project Cerberus Firmware Challenge Specification,” 2019, available at https://github.com/opencomputeproject/Project_Olympus/blob/master/Project_Cerberus

[S-4] OCP, “Project Cerberus Firmware Update Specification,” 2019, available at https://github.com/opencomputeproject/Project_Olympus/blob/master/Project_Cerberus

[S-5] OCP, “Project Cerberus Processor Cryptography Specification,” 2018, available at https://github.com/opencomputeproject/Project_Olympus/blob/master/Project_Cerberus

[S-6] Intel, “Intel® 9 Series Chipset Platform Controller Hub (PCH) Datasheet,” 2015, available at www.intel.com/content/www/us/en/products/docs/chipsets/9-series-chipset-pch-datasheet.html

Web

[W-1] Google, “Firmware Boot and Recovery,” www.chromium.org/chromium-os/chromiumos-design-docs/firmware-boot-and-recovery?tmpl=%2Fsystem%2Fapp%2Ftemplates%2Fprint%2F&showPrintDialog=1

[W-2] Checkm8, https://github.com/axi0mX/ipwndfu

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