In the Doherty amplifier at a low power operation, the input power is divided by a 3 dB coupler, and the 3 dB lower input power is delivered to the carrier, producing a 3 dB loss. Therefore, the overall gain of Doherty amplifier is equivalent to the gain with R_OPT load. At the peak power operation, the carrier and peaking amplifiers become a two-way current power combining structure with R_OPT load, and the gain is the same as at a low-power level. In between the two power levels, due to the nice asymmetrical power combining, the gain is maintained as we have described in Section 1.2.2. Due to the constant gain characteristic, the Doherty amplifier is a linear amplifier. However, in the practical design of the Doherty power amplifier using an HBT, the ideal gain characteristic is not produced.

5.2.1.1 Gain Modulation of Carrier Amplifier

Fig. 5.1 shows the nonlinear equivalent circuit model of an HBT. In the HBT model, C_be, g_be, and g_m are strong nonlinear components, varying as an exponential function of V_be. But their responses are canceled out since the output current g_mV_be is proportional to g_m/(jωC_be + g_be). And the main nonlinear component of an HBT is C_bc.

C_bc is the base-collector depletion layer capacitance, and it is decreased with V_bc because of the increased depletion size. The injected collector current also reduces the capacitance since the injected electron neutralizes the collector depletion donor and extends the depletion layer size. The capacitance variation is shown in Fig. 5.2. Since the current level is larger for the R_OPT operation than the 2R_OPT operation, the feedback capacitance C_bc is larger for 2R_OPT operation with similar V_bc swing. Therefore, the gain at 2R_OPT is reduced significantly by the strong feedback capacitance C_bc.

Fig. 5.3 shows the simulation results of the power gains for various output loads using the real device model. As shown in the figure, the power gains for both cases with the R_OPT and 2R_OPT are almost the same value regardless of the HBT size. The gain characteristic of the carrier amplifier makes it difficult to get a good AM-AM characteristic from the Doherty amplifier, but still linear Doherty amplifier operation is possible.

5.2.1.2 Flat Gain Operation of Doherty Amplifier Based on HBT

Under the ideal condition, the carrier amplifier operation with 2R_OPT load, at a low power region, has 3 dB higher power gain than the amplifier operation with the R_OPT, but there is 3 dB input power loss, compensating the gain. At the higher power operation, the gain reduction of the carrier amplifier with the R_OPT load is compensated by the peaking amplifier. Therefore, the constant gain is maintained. However, in real device implementation, the gain reduction cannot be compensated by the peaking amplifier because it requires the g_m of the peaking amplifier two times larger than that of the carrier amplifier as described in Section 1.2. It means that the peaking transistor should be two times larger than that of the carrier amplifier, wasting the power generation capability of the peaking amplifier. Moreover, the gain of the peaking amplifier is a lot lower than that of the carrier amplifier due to the class C bias. Therefore, the total gain of the Doherty power amplifier is distorted as shown in Fig. 5.4 (Gain_ideal case). This distortion can be compensated somewhat by the uneven driving as discussed in Section 2.1.

In the real device operation, the gains of the carrier amplifier with the R_OPT and 2R_OPT loads are almost the same value. Therefore, to get the proper Doherty load modulation characteristic, the carrier amplifier should be saturated in the modulation region with about 3 dB gain compression at the maximum output power by driving the carrier amplifier with a higher power. Due to the lower saturated gain of the carrier amplifier, the peaking amplifier can compensate the low gain, assisting for the proper Doherty operation with a constant gain as shown in Fig. 5.4. In the low-power region, only the carrier amplifier operates and should be linear. Therefore, the carrier amplifier should be designed as a linear amplifier at 2R_OPT load with a class AB bias. At the higher-power region, the IM3 components generated by the carrier amplifier and peaking amplifier should be canceled.

5.2.2 IMD3 Cancellation With Proper Harmonic Load Conditions

At the load modulation region with the quasisaturated operation of the carrier amplifier, the cancellation of the third-order intermodulation distortions (IMD3s) generated by the carrier and peaking amplifiers is the most important design issue in realizing a linear Doherty power amplifier. In a simple power series expression of the gain using a two-tone signal, the fundamental output power is expressed as

$v_{\text{Fund}}=\left\{a_{1}v+\frac{9}{4}{a}_3{v}^3+\frac{25}{4}{a}_5{v}^5\right\}cos\left({\omega }_{1,2}t\right)$

The output of the third-order intermodulation (IM3) is given by

$v_{\mathrm{IM}3}=\left\{\frac{3}{4}{a}_3{v}^3+\frac{25}{8}{a}_5{v}^5\right\}cos\left(2{\omega }_{1,2}-{\omega }_{2,1}\right)t$

Here, a₁ is the linear gain coefficient, and the other terms a_i represent the higher-order harmonic generation coefficients as described in Section 4.1.3. In Eq. (5.1), the linear gain is distorted by the higher-order harmonic generation.

The gain expansion occurs for a class C biased amplifier since a₃/a₁ and a₅/a₁ are positive. Therefore, the IM3 and fundamental signals of the peaking amplifier are in-phase. On the other hand, the gain compression occurs in the class AB biased carrier amplifier with negative a₃/a₁ and a₅/a₁, and the IM3 and fundamental signals are in antiphase. By using the complementary gain characteristics of the carrier and peaking amplifiers, the IMD3s of the two amplifiers can cancel each other, thereby improving the linearity of the Doherty power amplifier. These coefficients are strongly bias-dependent, and the gate biases of the carrier and peaking amplifiers should be properly adjusted for the cancellation.

In Eq. (5.2), the IMD3s at the lower and higher frequencies of the two-tone signal are the same magnitude, and the symmetrical IMD3 can be canceled. However, the different phased IM3s having different magnitudes are produced by the interactions of the fundamental and the feedback even-order intermodulation harmonic terms. This nondirectly generated IM3 terms, not included in the power series equations, cannot be canceled, deteriorating the IMD3 cancellation. The IM2, which is the most important even harmonic, should be suppressed by a second-harmonic termination, thereby alleviating the IM3 generation.

Fig. 5.5 shows the ideal simulation of the IM2 generation according to the conduction angle. As shown, the class AB and C amplifiers generate significant IM2s with different magnitudes according to the conduction angle. To investigate the harmonic suppression behavior, a two-tone simulation is conducted. In this simulation, an ideal second-harmonic short termination shown in Fig. 5.6 is attached under the condition that it doesn't affect the fundamental and other harmonic loads. The second-harmonic short at the output of peaking amplifier provides the same short condition at the output of the carrier amplifier because the quarter-wave line at a fundamental frequency turns into a half-wave line at the second-harmonic frequency.

Fig. 5.7A shows the magnitude and phase differences between the IM3s of the carrier and peaking amplifiers, I_C.IM3 and I_P.IM3. With the second-harmonic short, I_C.IM3 and I_P.IM3 are in near antiphase condition because the additional components produced by the even-order harmonics are suppressed. Also, the magnitude difference is in near zero. Therefore, the Doherty power amplifier with the second-harmonic short has a lower IMD3, through the IM3 cancellation, than the other case as shown in Fig. 5.7B. Moreover, the power amplifier with the second-harmonic short delivers a higher power-added efficiency (PAE) because it produces a class F waveform. The second-harmonic short circuit generates a half-sinusoidal shaped current waveform with the in-phase second-harmonic current, and the high third-harmonic load is easily produced internally for a rectangular-shaped voltage waveform.

The efficiency and linearity at the 6 dB power back-off (PBO) region are closely related to the turn-on timing of the peaking amplifier. Since the peaking amplifier cannot be abruptly turned on, it should be turned on early to compensate the AM-AM and AM-PM distortions of the carrier amplifier for achieving high linearity at the 6 dB PBO, but the early turn-on means that the load modulation starts early, before the carrier reaches to the saturated operation, and the efficiency at the 6 dB PBO is reduced.

Fig. 5.8 shows the effect of the turn-on timing of the peaking amplifier. The lower bias of the peaking amplifier boosts the efficiency of the 6 dB PBO, but the peak efficiency is decreased since the output power of the peaking amplifier is reduced due to the deeper class C bias. Moreover, the AM-AM and AM-PM are deteriorated leading to a poor linearity. For a linear Doherty power amplifier, therefore, the base bias of the peaking amplifier should be chosen properly to make the linear AM-AM and AM-PM responses.

5.3.1 Input Power Dividing Circuit

Fig. 5.10 shows the two input-power-dividing circuits: coupler divider and direct power divider. For mobile applications, a bulky input power divider can be removed by a direct input-power-dividing technique shown in Fig. 5.10B. For the ideal input power driving, the carrier amplifier should receive more power in the low-input-power region when the peaking amplifier is turned off, compensating the low gain at 2R_OPT operation, and the peaking amplifier gets more power in the high-input-power region to increase the gain and output power of the class C biased peaking amplifier.

The uneven power dividing can be realized using the power-level-dependent input impedance variations of the carrier and peaking amplifiers. The input capacitance C_in of an HBT shown in Fig. 5.1 is determined by C_be and miller capacitance C_bc. The capacitance is expressed as.

$C_{\text{in}}=C_{\mathit{be}}+C_{\mathit{bc}}\left(1+g_m\left(R_0‖R_L\right)\right)\left(\text{where}{R}_0\gg R_L\right)$

where R_L is the output load impedance. Fig. 5.11 shows the C_in variations for the carrier and peaking amplifiers.

Because of the class C bias of the peaking amplifier, the large-signal transconductance (g_m) and C_be of the peaking amplifier vary significantly, while those of the carrier amplifier remain almost constant. The input capacitance of the peaking amplifier increases over 200% as the input power increases, while that of the carrier amplifier varies less than 10%. The power-level-dependent input impedances can be matched to 50 Ω at a high-power region using either low-pass filter (LPF) or high-pass filter (HPF) type circuit as shown in Fig. 5.12. The carrier amplifier could be matched to 50 Ω for all power levels, since its impedance variation is small. For the same matching, the peaking amplifier shows significant mismatches at a low-power region.

As depicted in Fig. 5.12, the LPF-type circuit converts the input admittance of the peaking to higher than 1/50 ℧ at a low-power operation, while the HPF-type circuit converts it to lower than 1/50 ℧. The trace in Fig. 5.12 with the HPF matching indicates that the carrier amplifier receives more power at a low-input-power region because of its higher admittance, and the peaking amplifier can get more power at a high-input-power region. This HPF-type matching can provide the desired uneven input drive.

5.3.1.1 Input Power Dividing Using a Coupler

Wilkinson power dividers or 90° hybrid couplers are normally used for the input divider of a Doherty amplifier. With the power divider shown in Fig. 5.10A, the ports of the carrier and peaking amplifiers are isolated, and the input drive powers to the carrier and peaking amplifiers are determined by the coupler. The coupled powers to the amplifiers are related to the reflection coefficients (S₁₁) of the carrier and peaking amplifiers. The coupled power to the carrier amplifier is given by

$\begin{array}{c}{P}_{\text{in},c}=\frac{1}{2}{P}_{\mathrm{AVS}}\left(1-{\left|S_{11}\right|}^2\right)\\ =\frac{1}{2}{P}_{\mathrm{AVS}}\left(1-{\left|\frac{Z_{\text{in},c}-Z_0}{Z_{\text{in},c}+Z_0}\right|}^2\right)\end{array}$

  (5.4)

The coupled power to the peaking amplifier is the same as Eq. (5.4) but is determined by Z_in,p. The coupled power contours to the ports according to Z_in,c and Z_in,p are depicted in Fig. 5.13A. Because of the isolation property, the powers delivered to the two ports are independent.

If the input impedances of the carrier and peaking amplifiers are matched to Z₀ at the maximum output power using the HPF-type circuit and the input is divided by the coupler, the input power is driven in the two ports as shown in Fig. 5.14A. Because Z_in,p is mismatched at a low-power operation region due to the impedance variation as depicted in Fig. 5.12, the power delivered to the peaking amplifier at the power region is lower than that at the high-power region. The carrier amplifier is matched always, and the input power is constant. This input drive is similar to the even input drive and is not the optimum condition for the Doherty operation. For the proper Doherty amplifier operation, the input power driving should be an uneven drive as shown in Fig. 5.14B. When the input impedance of the peaking amplifier is matched to Z₀ and that of carrier amplifier to − 3.5 dB circle of Fig. 5.13A, the carrier input power is reduced by 1 dB, and 1 dB more power is delivered to the peaking amplifier at the maximum output power, realizing the uneven drive for optimum operation of the Doherty amplifier. Of course, this uneven drive can be realized using a coupler with the proper coupling ratio instead of mismatch at the carrier amplifier as described in Section 2.1.

5.3.1.2 Direct Input Dividing Without Coupler

A direct input dividing can be realized using the impedance variations of the carrier and peaking amplifiers. Unlike the power dividers, the direct input power divider does not have isolation between the carrier and peaking amplifier inputs since the carrier and peaking amplifiers share the same voltage node at the input as shown in Fig. 5.10B.

When the input impedances of the amplifiers are assumed to be Z_in,c and Z_in,p, respectively, the power at the junction is given by

$\begin{array}{c}{P}_{\mathrm{in}}=P_{\mathrm{A}\mathrm{V}\mathrm{S}}\left(1-{\left|S_{11}\right|}^2\right)\\ =P_{\mathrm{A}\mathrm{V}\mathrm{S}}\left(1-{\left|\frac{Z_{\mathrm{in},c}||Z_{\mathrm{in},p}-Z_0}{Z_{\mathrm{in},c}||Z_{\mathrm{in},p}+Z_0}\right|}^2\right)\end{array}$

  (5.5)

Here, P_AVS is the source power. At the node, the input voltage is identical, but the input current is divided to the carrier amplifier and the peaking amplifier by the ratio of their admittances. The divided currents and the voltage at the junction determine the input powers to the carrier and peaking amplifiers, respectively. The divided powers are given by

$P_{\text{in},c}=\frac{1}{2}\mathit{Re}\left[V_{\text{in}}·{I_{\text{in},c}}^{\ast }\right]=\frac{1}{2}\mathit{Re}\left[\frac{{\left|V_{\text{in}}\right|}^2}{{Z_{\text{in},c}}^{\ast }}\right]$

  (5.6)

$P_{\text{in},p}=\frac{1}{2}\mathit{Re}\left[V_{\text{in}}·{I_{\text{in},p}}^{\ast }\right]=\frac{1}{2}\mathit{Re}\left[\frac{{\left|V_{\mathit{in}}\right|}^2}{{Z_{\mathit{in},p}}^{\ast }}\right]$

  (5.7)

The matched impedances of the carrier and peaking amplifiers are given by

$Z_{\text{in},c}=R_{\text{in},c}+j{X}_{\text{in},c},Z_{\text{in},p}=R_{\text{in},p}+j{X}_{\text{in},p}$

  (5.8)

The power-dividing ratio is equal to the ratio of the input admittances of the amplifiers:

$\begin{array}{l}{P}_{\text{in},c}:P_{\text{in},p}=\frac{1}{2}\mathit{Re}\left[\frac{{\left|V_{\text{in}}\right|}^2}{{Z_{\text{in},c}}^{\ast }}\right]:\frac{1}{2}\mathit{Re}\left[\frac{{\left|V_{\text{in}}\right|}^2}{{Z_{\text{in},p}}^{\ast }}\right]\\ =\frac{R_{\text{in},c}}{{R_{\text{in},c}}^2+{X_{\text{in},c}}^2}:\frac{R_{\text{in},p}}{{R_{\text{in},p}}^2+{X_{\text{in},p}}^2}\end{array}$

  (5.9)

The input impedance of the carrier amplifier remains almost constant for the input power variation, while that of the peaking amplifier changes significantly because of the class C bias. For 1: N power dividing, with the matched carrier amplifier, the transformed input impedance of the peaking amplifier is given by

$1:N=1:\frac{r_{\text{in},p}}{{r_{\text{in},p}}^2+{x_{\text{in},p}}^2}$

  (5.10)

where r_in and x_in are normalized by Z₀. Eq. (5.10) becomes

${\left(r_{\text{in},p}-\frac{1}{2N}\right)}^2+{x_{\text{in},p}}^2={\left(\frac{1}{2N}\right)}^2$

  (5.11)

which is an equation of a circle centered at r = 1/(2N) and x = 0, with radius of 1/(2N), and is represented by a conductance circle on the Smith chart. In the case of N = 1, r_in,p and x_in,p are on the Z₀ conductance circle on the Smith chart. Fig. 5.13B shows a power-dividing ratio contours according to the trace of Z_in,p, where Z_in,c is matched to Z₀. Fig. 5.15 shows the input impedances of the peaking amplifier for 1:1 dividing for the even drive and 1:2 dividing for the uneven drive. When Z_in,p is located inside of the 1:1 circle, the uneven drive is realized, delivering more power to the peaking amplifier. Following Z_in,p matched by the HPF circuit shown in Fig. 5.12, the trace of the uneven P_in drive is depicted in Fig. 5.15. The trace indicates that the carrier amplifier receives more power at a low-input-power region and the peaking amplifier gets more power at a high-input-power region, which is the desired input drive.

5.3.1.3 Realization of the Input Power Dividing Circuit

The phase compensation network of the quarter-wavelength line at the input of the peaking amplifier as shown in Fig. 5.9A can perturb the proper input power dividing. Alternatively, the phase compensation network is employed at the input of the carrier amplifier using a HPF-type circuit with negative angle as shown in Fig. 5.16. A quarter-wavelength line for the phase compensation is implemented in a lumped π-type network using two shunt inductors considering the rearrangement. The amplifiers are matched using the HPF-type matching circuit for the uneven drive. The five inductors shown in Fig. 5.16 can be merged into two inductors, and both the number and size of the inductors are reduced owing to the parallel structure. L_m1 and L_m2 are easily implemented by a collector bias line of the drive stage and a bond wire, respectively. Overall, two capacitors (C_ip1 and C_ic2) and one π-circuit are needed to drive the Doherty stage along with the interstage matching.

5.3.2 Output Circuit Implementation

Fig. 5.6 shows a Doherty amplifier using a quarter-wave inverter. The output capacitances of the carrier (C_out,c) and peaking (C_out,p) are resonated out at the drain by the inductances of the bias lines L_c1 and L_p1, respectively. Therefore, the matching circuits do not need to transfer the imaginary part of impedance, and the offset lines are not needed, achieving a smaller size circuit. The phase compensation circuit at the input of the carrier amplifier and the quarter-wave inverter at the output have phase delays of − 90° and 90°, respectively, and the phase delay between the two amplifiers are adjusted.

To implement the amplifier on a single chip for a handset application, the bulky quarter-wave inverter should be replaced by an equivalent lumped LC network as shown in Fig. 5.17. The lumped network type should be chosen carefully by considering the compact design and the harmonic load condition. In the size aspect, (A) and (B) types can share a single collector bias line, but (C) and (D) require two collector bias lines due to the DC blocking capacitor. The shunt inductors of (C) can be used for collector bias lines of the carrier and peaking amplifiers, respectively, but the inductance should be large to compensate the output capacitors C_out,c and C_out,p.

With the high-pass π type (C), both the number and values of the lumped components can be significantly reduced, similarly to the elaborated matching technique at the input that is explained in Section 5.3.1.3. However, (A) and (B) circuits have a size advantage at the output. Since the shunt capacitors of the low-pass π type (A) can be merged with the output capacitors C_out,c and C_out,p, their values and sizes are reduced. In general, an output matching circuit of a power amplifier for a handset is implemented by off-chip components on the package module to reduce the output matching circuit loss. Due to the low characteristic impedance of R_OPT at ~ GHz band, the inductance of the lumped inverter is lower than 1 nH (for R_OPT = 8 Ω device, L_c1 = 0.67 nH). Therefore, a series inductor of (A) can be implemented by a bond-wire inductance that is employed to connect the chip to a package module.

The lumped inverter of (A) is the most suited structure to reduce the size of the network, but the size of the harmonic load should also be considered. To analyze the circuit in detail, harmonic balance simulation with the schematic shown in Fig. 5.18 is conducted, and the results are shown in Fig. 5.19. With the lumped inverter, the second-harmonic shorts at the outputs of the carrier and peaking amplifiers have a minor effect on linearity since the large shunt capacitors C_c1 and C_c2 provide near short second-harmonic load conditions for the carrier and peaking amplifiers, respectively. Therefore, the amplifier can deliver a good IMD3 characteristic without the second-harmonic shorts.

However, the second-harmonic shorts at the outputs of the carrier and peaking amplifiers show different effects on the PAE. When the second-harmonic short is provided at the carrier amplifier, it reduces the PAE because the out-of-phase second-harmonic current is increased and bifurcated current waveforms is generated, reducing the ratio of I_{c.Carrier.Fund}/I_c.Carrier.DC as shown in Fig. 5.20A. On the other hand, when the second-harmonic short is provided at the peaking amplifier, it improves the PAE because the in-phase second-harmonic current is increased and the half-sinusoidal peaked current waveform is generated, increasing the ratio of I_{c.Peaking.Fund}/I_c.Peaking.DC as shown in Fig. 5.20B. Consequently, the peaking amplifier with the second-harmonic short delivers a higher PAE in contrast to the carrier amplifier. Therefore, the short circuit is employed only at the peaking amplifier.

5.5.1 Implementation of Linear CMOS Doherty Power Amplifier

The schematic of the CMOS Doherty power amplifier including the output transformer is shown in Fig. 5.24. The carrier and peaking amplifiers are cascode amplifiers, and they are voltage-combined using the transformer. Thick-oxide 0.4 μm gate transistors are used in the common-gate (CG) stages for reliable high-power operation, and thin-oxide 0.18 μm gate transistors are used in the common-source (CS) stages to enhance transconductance and gain. The total gate widths of the thin and thick devices are 4800 and 9600 μm, respectively. The second-harmonic short circuits implemented by metal-insulator-metal (MIM) capacitors and the inductances of a down-bonding wires are provided at the sources of the CS stages to improve linearity by providing the proper second-harmonic grounding and suppressing the second-harmonic term as described before. The R_CG-C_CG bias circuits are inserted to control the voltage swings at the gates of the CG stages. The L_in,c and L_in,p of the input matching networks transform the input impedances of the transistors to pure resistance of 12 Ω. A 90° high-pass T-type lumped quarter-wave transformer is inserted at the input path of the peaking amplifier to compensate the phase of the output quarter-wave inverter. A transformer is used for the balanced input drive.

At the output, the output capacitances of the devices are de-embedded in the Doherty network components without using the offset line similarly to the current combining case. Fig. 5.25A shows the output matching network of the practical CMOS Doherty power amplifier, and Fig. 5.25B illustrates how to manipulate the output capacitances of the transistors without using the offset lines.

The output capacitance of the peaking transistor, $\overline{C_{\text{out}..p}}$ is merged into the quarter-wave inverter, a low-pass π type, considering the compact implementation. Thus, the first shunt capacitor (C_p1) is the lumped inverter capacitance subtracted by the$\overline{C_{\text{out}.p}}$. The output transformer with C₁ and C₂ provides impedance matching for the output. Since the center tap of the output transformer is used as a biasing point for compact implementation, the output capacitance of the carrier amplifier $\overline{C_{\text{out}.c}}$ should be 2C₁ for a simple merged structure without offset line for the carrier amplifier. The C₁ and C_inverter determine the second shunt capacitor (C_p2) of the lumped inverter as shown in Fig. 5.25B. A printed-circuit-board (PCB) transformer is designed using two-layer metal lines. The use of the two metal layers generates stronger coupling and has an advantage in size. The L_p1 and C_p2, which are parts of the lumped inverter, are also implemented on the PCB using the metal line and the external capacitor, respectively. The external capacitor C₂ is used for the impedance matching with the small inductance of the secondary trace. The insertion loss of the output transformer including the C₂ is 0.32 dB at 880 MHz.

5.5.2 Measurement Results

The power amplifier is fabricated using a 0.18 μm CMOS process, and the total chip area including the pads is 1.2 × 1.1 mm² as shown in Fig. 5.26. The total amplifier module including the output combining transformer on an FR4 PCB board is 5.0 × 2.9 mm². Fig. 5.27 shows the measured two-tone performance of the power amplifier with a supply voltage of 4.0 V at the 880 MHz. The first peak efficiency at the 6 dB PBO can be maximized by adjusting the CS gate bias voltage of the peaking amplifier. However, the amplifier at the gate bias with the maximized efficiency produces a gain distortion, deteriorating the linearity as shown in Fig. 5.27A. For the linear Doherty power amplifier, the CS gate bias of the peaking amplifier is chosen to make a linear AM-AM and AM-PM characteristics. With the proper CS gate biases and the additional phase delay line merged into the input phase compensation network, the Doherty power amplifier achieves low IMDs as shown in Fig. 5.27B.

The linear power amplifier is tested at 880 MHz using a 10 MHz BW, 16-quadrature amplitude modulation (QAM) and 7.5 dB PAPR LTE signal, and the results are shown in Fig. 5.28. The power amplifier delivers a gain of 13.3 dB, a PAE of 47.4%, an error vector magnitude (EVM) of 3.85%, and an E-UTRA_ACLR of − 33 dBc at an average output power of 27 dBm. Without using any complex circuitry, the CMOS Doherty power amplifier based on a voltage-combining method could deliver the very good performance for the LTE signal with large PAPR.

5.6.1 Adaptive Base Bias Control Circuit for Average Power Tracking

Fig. 5.29A shows the schematic of the two-stage Doherty power amplifier. A direct input-power-dividing technique is employed to optimize the load modulation through a proper input drive and to reduce number of circuit components at the input. Flat AM-AM and AM-PM responses are achieved at all power levels by analysis of the gain modulation and selection of proper base biases. To improve the linearity and reduce the size, the lumped quarter-wave transformer of a low-pass π type is selected at the output of the carrier amplifier, and the second-harmonic short circuit is employed at the peaking amplifier only.

Fig. 5.30 shows the measurement results with a two-tone signal at 1.9 GHz having 10 MHz tone-spacing. The Doherty power amplifier delivers a good linearity under − 30 dBc with 3.4 V V_cc. However, the linearity is worsen as V_cc is decreased. With the voltage lower than 2.4 V V_cc, the power amplifier does not meet the − 30 dBc linearity specification. This means that the IM3 can be cancelled optimally only at the fixed V_cc, and the circuit should be retuned for proper IM3 cancellation at the different V_cc.

Since the load is fixed, as the collector bias of the carrier and peaking amplifiers is decreased, the peak output power of the Doherty power amplifier is decreased. Therefore, the input power should be reduced as the peak output power is decreased. Therefore, the carrier amplifier is operated in the low-current region with the low base current, and the base bias of the carrier amplifier should be reduced. To maintain the good linearity with the V_cc variation, the turn-on time of the peaking amplifier should be properly adjusted since the linearity at the 6 dB back-off region is closely related to the cancellation of the IM3 components generated by the carrier and peaking amplifiers. The peaking amplifier should be turned on at a 6 dB back-off level from the lower input power. To maintain the turn-on timing at the optimum back-off level, the base bias of the peaking amplifier needs to be increased because the threshold voltage of a transistor does not change much with the collector bias sweep.

The simulated optimum base currents of the carrier and peaking amplifiers to maintain the linearity at the high-power region with the V_cc sweep are depicted in Fig. 5.31. As shown, the carrier current should be reduced linearly as the collector bias is reduced. However, the peaking current is increased with the reduced voltage. The adaptive circuits suitable to control the base current levels of the carrier and peaking amplifiers are shown in Fig. 5.32. The control voltage of the adaptive bias circuits is supplied from the output voltage of the multi-level DC-DC converter (V_out.APT). The adaptive bias circuits automatically generate the extracted optimum base bias points of the carrier and peaking amplifiers, respectively, as shown in Fig. 5.31. As explained, the optimum bias point of the carrier amplifier is decreased and that of the peaking amplifier is increased, as the collector bias is decreased.

5.6.2 Implementation and Measurement

The Doherty power amplifier is fabricated using an InGaP/GaAs HBT and the chip area is 1.25 × 0.95 mm², as shown in Fig. 5.29B. Texas Instruments' LM3290 product is used for the multilevel DC-DC converter. Its output voltage ranges are from 0.4 to 3.81 V, and the highest efficiency is 95% with V_out.APT of 3.81 V. Fig. 5.33 shows the measured performance of the Doherty power amplifier with various V_out.APT at 1.9 GHz for a 10 MHz BW 16-quadrature amplitude modulation (QAM) 7.5 dB PAPR LTE signal. The power amplifier with V_out.APT of 3.8 V delivers a gain of 24.4 dB, a PAE of 45.7%, an error vector magnitude (EVM) of 2.65%, and an evolved universal terrestrial radio access adjacent channel leakage ratio (E-UTRA_ACLR) of − 35.3 dBc at an average output power of 27.5 dBm. The Doherty power amplifier with the APT shows a high efficiency at overall dynamic ranges for various V_out.APT from 1.0 to 3.8 V. The E-UTRA_ACLR specifications are satisfied for all V_out.APT having more than − 5 dBc margin. In comparison with the Doherty power amplifier with the ideal APT, the efficiency of the power amplifier with the APT is slightly lower due to the limited efficiency of the multilevel DC-DC converter as shown in Fig. 5.34. However, the efficiency at the whole back-off regions is significantly improved from the Doherty power amplifier with a fixed bias.