Index
Note: Page numbers followed by f indicate figures.
A
carrier amplifier 38
efficiency analysis 34–35
load impedances 35
optimum condition 36–38
RF power and DC power 35–36
Average power tracking (APT) 93–94
base station amplifier 93–94
drain bias voltage and output power derivation 95–96
fixed gate and drain control 94–95
gate bias voltage derivation 96
handset power amplifier 93–94
adaptive base bias circuit 165–167
B
Back-off output power (BO) 68–69
Bias adaptation See Gate-bias adaptation technique
C
AM-AM, AM-PM, and IMD3 distortions 107–108
coupled power 110
definition 2
efficiency and gain behaviors 40–41
first peak input matched carrier amplifier 73–74
fundamental matching impedances 74f
gain modulation 141–143
input second harmonic load 78–80
knee effect Doherty amplifier 50
low-power operation 8
output impedance trajectory 24–26
output-matching circuit 24
saturated mode 31
saturation state, at input voltage 38
second-harmonic shorts 117
6dB back-off power region 45
3dB back-off power 43
unsaturated state 89
CMOS process 20–22
differential power amplifier 159
voltage and low power density 17
voltage-combined Doherty power amplifier 87
voltage-controlled current source (VCCS) 3
voltage-controlled voltage source (VCVS) 3
D
Direct power-dividing approach 147–149
back-off output power (BO) control 68–69
carrier amplifier efficiency 67
6dB back-off point 65
efficiency degradation 69f
load impedances and fundamental drain currents 70
load modulation 70
output power 66–67
output power degradation 68–69
peaking amplifiers, load lines 66f
peak output power (PEP) level 68–69
base station 93–96
conventional Doherty amplifier 94–95
first peak efficiency region match 23–29
back-off region 73
conventional design 73–74
CW characteristics 73–74
fundamental impedance matching points 73
LC parallel network circuits 73–74
operation of 75–76
simulated CW characteristics 76f
optimized design 70–76
optimized peaking amplifier design 77–83
knee voltage effect See Knee voltage effect
load modulation methods 15–29
offset line technique 10–15
operational diagram 4f
efficiency 8–9
gain characteristics 9
load modulation behavior 6–7
saturated Doherty amplifier See Saturated Doherty amplifier
schematic diagram 10f
Doherty, William H. 1
Drain efficiency (DE) 107
E
Efficiency analysis 34–35
Efficiency degradation 69f
F
G
Gain modulation, of carrier amplifier 142–143
GaN HEMT Doherty power amplifier 70
back-off region 73
conventional design 73–74
CW characteristics 73–74
fundamental impedance matching points 73
LC parallel network circuits 73–74
operation of 75–76
simulated CW characteristics 76f
source-pull simulation results 73
Gate-bias adaptation technique 31–32
carrier amplifier 40–41
continuous wave (CW) simulation 41
controlled bias voltage shapes 42f
performance of 41f
real implementation 38–39
uncontrolled Doherty amplifier 42f
H
average power tracking 165–167
CMOS Doherty amplifier 159–164
functional blocks 147–149
gain modulation of carrier amplifier of HBT 142–143
input power divider 147–155
with coupler 150–151
input circuit realization 154–155
without coupler 152–154
linearity 145–147
offset lines 147–149
lumped inverter 156
lumped low-pass π -type quarter-wave inverter 156f
quarter-wave inverter and delay line 155
second-harmonic shorts 156
I
Input power dividing circuit 147–155
with coupler 150–151
input circuit realization 154–155
without coupler 152–154
Inverted Doherty amplifier 95–96
Inverted load modulation 22–23
K
Cree GaN HEMTCGH40045 device 46–47
6dB back-off power region 45
load impedance 46
conventional Doherty amplifier and knee effect Doherty amplifier 48–49
fundamental and dc currents 49
fundamental voltages 52
offset line control 52
L
IMD3 cancellation, proper harmonic load conditions 145–147
flat gain operation 144
gain modulation, of carrier amplifier 142–143
fifth-order intermodulation distortion (IMD5) current 109
gate-bias voltages 114
harmonic cancellation mechanism 109–110
IM3 and IM5 cancellations 112–113
nonlinear output current 109
one-carrier and two-carrier downlink signal 113f
third-order intermodulation distortion (IMD3) current 109
load impedance modulation 3–5
modulated loads 7
of peaking amplifier 23
conventional Doherty amplifier and Doherty amplifier 48–49
conventional efficiencies 52f
fundamental and DC currents 49
fundamental voltages 52
offset line control 52
voltage, current, and load impedance profiles 6–7
inverted load modulation 22–23
series-connected load 15–16
transformer based power amplifier 17–18
transformer based voltage 18–22
N
carrier amplifier and peaking amplifier 105
drain efficiency (DE) 107
power generation distribution (PGD) 107–108
first peak-efficiency power point 101
linearity 109–114
fifth-order intermodulation distortion (IMD5) current 109
gate-bias voltages 114
harmonic cancellation mechanism 109–110
IM3 and IM5 cancellations 112–113
nonlinear output current 109
one-carrier and two-carrier downlink signal 113f
third-order intermodulation (IM3) current 109
drain current 104f
three-way Doherty amplifier 103
unit cells, load impedance 104f
O
carrier amplifier 11–14
operations of 11–15
peaking amplifier 14–15
phase compensation of peaking amplifier 58–60
realization of, Doherty amplifier 10–11
P
Peaking amplifier (PA) 2
carrier amplifier 38
efficiency analysis 34–35
load impedances 35
optimum condition 36–38
RF power and dc power 35–36
uneven drive through coupler 32–38
carrier load impedances 31
direct dividing technique 32
external voltage control circuitry 32
gate-bias adaptation technique 31–32
carrier amplifier adaptation 40–41
continuous wave (CW) simulation 41
controlled bias voltage shapes 42f
performance of 41f
real implementation 38–39
and uncontrolled Doherty amplifier 42f
low fundamental current generation 31
additional peaking offset lines 56–58
maximum efficiency points 53–54
Phase compensation network 154–155
Power-added efficiency (PAE) 70–72
Power back-off (PBO) point 20
Power generation distribution (PGD) 73–74
Q
Quarter-wave inverter 155
R
RF choke inductor 76
S
class F amplifier 84–88
efficiency 88–91
harmonic control circuit 91–93
linearity 91
operational principle 84–88
saturated amplifier 91–93
T
Third-order intermodulation distortion (IM3) 91
3dB coupler 9–11
implementation, problems in 138–139
fundamental design approach 115–118
ideal operational behavior 122–124
load modulation, efficiency and output power 118–122
with asymmetric size ratio 133–136
efficiency profiles 136
linear gain response 136–138
load modulation behavior and efficiency 129–133
load modulation circuit 127–128
peak efficiency points 126
V
Voltage-controlled current source (VCCS) 3
Voltage-controlled voltage source (VCVS) 3
W
Wilkinson power divider 97–98
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