The simplest illustration of the load modulation concept is shown in Fig. 1.1, where a voltage-controlled voltage source (VCVS) is in parallel with a voltage-controlled current source (VCCS) and a load resistor R. The impedance seen by the VCVS, Z₁, is modulated by the current I₂, as given by

$Z_1=\frac{V_1}{I_1}=\frac{V_1}{I_R-I_2}$

Varying the current I₂ from zero to I_R = V₁/R, Z₁ is varied from R to ∞. In this circuit, the VCCS modulates the load impedance of the VCVS. In Doherty amplifier, the ability to modulate Z₁ using I₂ is properly employed to track the optimal impedances for the amplifier to operate efficiently at the back-off power levels. An important property of the setup in Fig. 1.1 is that the linearity of the overall system is solely determined by the linearity of the VCVS because the voltage V_out across the load is always equal to V₁. Therefore, linearity is guaranteed regardless of the value of I₂, as long as V₁ is linearly proportional to V_in. For this purpose, the impedance Z₁ should track a given impedance profile versus V_in by specifying the I₂ versus V_in profile. Although mathematically simple to define it, realizing a given I₂ versus V_in profile in practice can be a challenge.

In the load modulation technique, the VCVS and VCCS have their important roles. The former ensures the linearity of the amplifier, while the latter acts as the load modulating device, whose I₂ versus V_in profile determines the impedance Z₁ seen by the VCVS. These two properties are important in derivation of the Doherty circuit configuration.

The Doherty amplifier uses a different circuit topology for the load modulation. It consists of two amplifiers (two current sources) and an impedance-inverting network, which converts the one current source to a voltage source. This converted amplifier is called a carrier amplifier, and the other current source amplifier is a peaking amplifier. Fig. 1.2 shows an operational diagram to analyze the Doherty amplifier circuit. The output load is connected to the carrier amplifier through the impedance inverter (a quarter-wave transmission line) and directly to the peaking amplifier. In this figure, the optimum power-matching impedance of the carrier and peaking amplifiers at the peak power is R₀, and the load of the carrier amplifier, when the peaking amplifier is off, becomes R₀/2 due to the parallel connection of the two amplifiers. It is assumed that the output capacitor of the device is resonated out and the phase delay of the quarter-wave line is compensated at the input.

The impedance inverter has a characteristic impedance of R₀ also. The load impedances of the carrier amplifier at Z₁′ and Z₁, shown in Fig. 1.2, are given by

${\mathrm{Z}}_1^{\prime }=\frac{{\mathrm{V}}_0}{{\mathrm{I}}_1^{\prime }}=\frac{R_0}{2}\bullet \left[\frac{I_1^{\prime }+I_2}{I_1^{\prime }}\right]$

${\mathrm{Z}}_1=\frac{{R_0}^2}{{\mathrm{Z}}_1^{\prime }}=\frac{2R_0}{\left(1+\frac{I_2}{I_1^{\prime }}\right)}=\frac{2R_0}{\left(1+\alpha \right)}$

where $\alpha =\raisebox{1ex}{$I_2$}\!\left/ \!\raisebox{-1ex}{$I_1^{\prime }$}\right.$. Eq. (1.3) shows that the carrier amplifier represented by a current source I₁ sees the load impedance modulated by the second current source I₂, representing the peaking amplifier. It should be noticed that I₁′ is different from I₁ due to the impedance change. Also, in the normal Doherty operation, the current level of the peaking amplifier varies from 0 to I₁ = I_max, the maximum current of the two amplifiers, and α changes from 0 to 1. Normally, I₁ and I₂ can handle the same amount of current, that is, the same size devices for the two amplifiers, and Z₁ is R₀ when I₂ = I₁ = I_max at the peak power, because I₁ is equal to I₁′ at the power. Z₁ is 2R₀ when I₂ = 0 and Z₁ is in between the two values for the I₂ current between 0 and I_max. This is the Doherty load modulation behavior, which is depicted in Fig. 1.3C.

The peaking amplifier provides the open load until it is turned on because the current I₂ is zero. After turned on, the impedance Z₂ is also modulated similarly, which is given by

$Z_2=\frac{V_0}{I_2}=\frac{R_0}{2}\bullet \frac{\left(I_1^{\prime }+I_2\right)}{I_2}=\frac{R_0}{2}\bullet \frac{\left(1+\alpha \right)}{\alpha }$

The load modulation behavior is also depicted in Fig. 1.3C. The carrier impedance is modulated from 2R₀ to R₀ and the peaking from infinity to R₀. In this figure, it is assumed that each current source is linearly proportional to the input voltage and R₀ is equal to R_OPT of the transistor, the optimum power matching resistance. As shown in Fig. 1.3A, I₂ is turned on at the midpoint due to the class C bias of the peaking amplifier and is increased to the maximum value. I₁ is linearly increased from the zero gate voltage due to the class B bias. In this operation, the transconductance of the peaking amplifier should be twice larger than that of the carrier amplifier due to a half of the input voltage swing for the maximum current generation. To get the two times larger transconductance, the peaking amplifier should be two times larger than the carrier amplifier. But in the case, only a half of the peaking current is utilized, wasting the power generation capability. To solve the problem, uneven driving technique is developed, which will be introduced in Chapter 2.

1.2.1.2 Voltage, Current, and Load Impedance Profiles

Under the load modulation described in Section 1.2.1.1, the current and voltage profiles of the carrier and peaking amplifiers are depicted in Fig. 1.3. Fig. 1.3A shows the fundamental currents of the carrier and peaking amplifiers, I_C and I_P, respectively. The two devices generate the same maximum current as shown in the figure. The currents are given by

$I_1=I_{\text{max}}\left[\frac{V_{\text{in}}}{V_{\text{in},\max }}\right]0<V_{\text{in}}<V_{\text{in},\text{max}}$

$I_2=\left\{\begin{array}{cc}0& 0<V_{\text{in}}<V_{\text{in},\text{m}\text{a}\text{x}}/2\\ I_{\max }\left[\frac{V_{\text{in}}-V_{\text{in},\text{m}\text{a}\text{x}}/2}{V_{\text{in},\text{m}\text{a}\text{x}}/2}\right]& V_{\text{in},\text{m}\text{a}\text{x}}/2<V_{\text{in}}<V_{\text{in},\text{m}\text{a}\text{x}}\end{array}\right.$

By introducing the current profiles to Eqs. (1.3), (1.4), the load impedances of the carrier and peaking amplifiers, Z₁ and Z₂, can be calculated:

$Z_1=\left\{\begin{array}{cc}2R_0& 0<V_{\text{in}}<V_{\text{in},\max }/2\\ \frac{2R_0}{1+\alpha }& V_{\text{in},\text{m}\text{a}\text{x}}/2<V_{\text{in}}<V_{\text{in},\text{m}\text{a}\text{x}}\end{array}\right.$

$Z_2=\left\{\begin{array}{cc}\infty & 0<V_{\text{in}}<V_{\text{in},\text{m}\text{a}\text{x}}/2\\ \frac{R_0}{2}\cdot \frac{\left(1+\alpha \right)}{\alpha }& V_{\text{in},\text{m}\text{a}\text{x}}/2<V_{\text{in}}<V_{\text{in},\text{m}\text{a}\text{x}}\end{array}\right.$

$\text{with}\mathrm{\alpha }=\raisebox{1ex}{$I_2$}\!\left/ \!\raisebox{-1ex}{$I_1^{\prime }$}\right.=\frac{2R_0}{Z_1}⌈\frac{V_{\text{in}}-V_{\text{in},\text{m}\text{a}\text{x}}/2}{V_{\text{in}}}⌉$

The voltage profiles of the carrier and peaking amplifiers can be calculated using the current profiles and load impedances of Z₁ and Z₂, respectively, which are given by

$V_1=\left\{\begin{array}{cc}2R_0\cdot \left(\frac{I_{\max }}{V_{\text{in},\max }}\right)\cdot V_{\text{in}}& 0<V_{\text{in}}<V_{\text{in},\max }/2\\ R_0\cdot I_{\max }& V_{\text{in},\max }/2<V_{\text{in}}<V_{\text{in},\max }\end{array}\right.$

$V_2=\left\{\begin{array}{cc}{R}_0\cdot \left(\frac{I_{\max }}{V_{\text{in},\max }}\right)\cdot V_{\text{in}}& 0<V_{\text{in}}<V_{\text{in},\max }\end{array}\right.$

Because the load impedance of the carrier amplifier is 2R₀ at a low-power operation, the voltage approaches the peak level when the peaking is turned on. After that, the voltage remains at the peak level because the load resistance decreases accordingly as the current increases. The voltage across the peaking amplifier increases linearly and reaches to the peak level when the input voltage is at the maximum. In $0<V_{\text{in}}<\frac{V_{\text{in},\max }}{2},$the voltage of the peaking amplifier is not defined because the peaking amplifier is turned off. But the voltage should be V₀, which is converted from V₁ in Eq. (1.10). Overall, the voltage profile is given by Eq. (1.11), which is determined by the current of the input voltage multiplied by 2 ∙ G_m, the effective transconductance, and the load impedance of R₀/2.

1.2.1.3 Load Lines for the Modulated Loads

The load lines of the two amplifiers can be calculated from the voltage and current profiles shown in Fig. 1.3 and are presented in Fig. 1.4. Due the load modulation, the load line for the carrier amplifier follows 2R₀ until the peaking amplifier is turned on. After the peaking is turned on, the load of the carrier is reduced following Eq. (1.7). Due to the reduced load impedance according to the current level, the load line follows the knee region as shown in the figure, maintaining the high efficiency of the class B amplifier. The peaking amplifier is off at the low power with the open load. As soon as it is turned on, the voltage is built on fast with the transconductance of 2Gm and load impedance of Ro/2 and reaches to the peak voltage at the peak input voltage following Eq. (1.11), which is shown in Fig. 1.4.

1.2.2.1 Efficiency

Generally, a power amplifier, with a specific optimum load impedance, delivers the maximum efficiency only at the peak power since the full output voltage and current swings are achieved only at the peak output power defined by the fixed load. On the other hand, the load of the Doherty power amplifier is dynamically modulated, providing the peak efficiency at the different power level determined by the modulated load. For the Doherty load modulation, the carrier amplifier provides the maximum efficiency at a half of the maximum input voltage, and the maximum efficiency is maintained through the load modulation at a higher power as shown in Fig. 1.5. The peaking amplifier achieves the maximum efficiency only at the peak power.

In the low-power region (0 < V_in < V_{in, max}/2), the peaking amplifier remains in the cutoff state, and the load impedance of the carrier amplifier is two times larger than that of the conventional amplifier. Thus, the carrier amplifier reaches to the saturation state at the input voltage of V_{in, max}/2 since the maximum voltage swing reaches to V_dc with a half of the maximum current level. As a result, the maximum power level is a half of the carrier amplifier's allowable power level (a quarter of the total maximum power or 6 dB down from the total maximum power), and the efficiency of the Doherty amplifier is equal to the maximum efficiency of the class B carrier amplifier.

In this low-power operation, only the carrier amplifier with a half of the total power cell produces power, and the efficiency at a given power level is twice higher than that of the two times bigger power cell amplifier.

In the higher-power region (V_{in, max}/2 < V_in < V_{in, max}), where the peaking amplifier is conducting, the carrier amplifier generates power with the peak efficiency since the saturated operation is maintained due to the load modulation. The peaking amplifier operates with very large load at the turn-on stage, and the efficiency increases very fast but is still lower than the peak efficiency. Thus, the total efficiency of the Doherty amplifier is degraded. But the second maximum efficiency point is reached when the peaking amplifier provides the maximum efficiency at the peak power with saturated operation. Therefore, it has two maximum efficiency points, enhancing the efficiency at the backed-off output power level as shown in Fig. 1.5. The efficiency of the Doherty amplifier at the maximum input voltage is equal to the maximum efficiency of the conventional amplifiers. Therefore, the Doherty amplifier provides higher efficiency over the whole power ranges compared with a conventional class B amplifier. The resulting Doherty amplifier can solve the problem of low efficiency for amplification of a large PAPR signal.

1.2.2.2 Gain

To drive the carrier and peaking amplifiers with an equal power, the input power of the Doherty amplifier is divided using a 3 dB coupler. Therefore, the input power level to the carrier is 3 dB lower than the total input power. However, the load of the carrier is two times higher than R_OPT at a low-power operation, and the gain is increased by 3 dB by the 2R_OPT load, recovering the gain loss due to the 3 dB lower input power. At the peak-power operation, the carrier and peaking amplifiers become a two-way current power-combining structure with R_OPT load, and the gain is the same as at a low power level. In between the two power level, due to the nice asymmetrical power combining with the load modulation, the gain is maintained at the constant value.

The power gain at the intermediate-drive region can be calculated from Fig. 1.2:

$I_1^{\prime }=I_1\bullet \sqrt{\frac{Z_1}{Z_1^{\prime }}}=I_1\frac{2}{1+\alpha }$

The current flowing through the load R₀/2, I_L, is given by

$I_L=I_1^{\prime }+I_2=I_1^{\prime }+\alpha I_1^{\prime }=2\cdot I_1$

The 2 ∙ I₁ current flows through R₀/2 load during the load modulation. Under the condition that the input voltage generates linear currents I₁ as shown in Fig. 1.3A, the constant gain is maintained during the load modulation. Due to the constant gain characteristic, the ideal Doherty amplifier is a linear amplifier, if the nonlinearity of the transistor is not considered.

1.3.2.1 Offset Line at Carrier Amplifier

The offset lines for the carrier amplifier and peaking amplifiers are shown in Fig. 1.7. The functions of the two lines are identical. Let's consider the output section of the carrier amplifier. The matching network compensates the device reactive and parasitic elements and transforms a load R_C = R₀ to the desired Z_IN,c = R_OPT at the current source. However, for the load of R₀ to 2R₀, Z_IN,c is not converted to the resistive impedance but becomes a complex impedance. Without the offset line, the input reflection coefficient of the scattering matrix S of the cascade of the device reactive part and matching network (Fig. 1.7B) is given by

${\mathit{\Gamma }}_{\mathit{IN},c}\triangleq \frac{Z_{\mathit{IN},c}-R_{\mathrm{OPT}}}{Z_{\mathit{IN},c}+R_{\mathrm{OPT}}}=\frac{S_{11}-{\mathrm{\Delta }}_S{\mathit{\Gamma }}_C}{1-S_{22}{\mathit{\Gamma }}_C}$

where ΔS is the determinant of the S-parameter with a characteristic impedance of R_OPT and Γ_C is the reflection coefficient of R_C with respect to R_OPT, which is always a real number. The matching network is designed to ensure Γ_IN,c = 0 when Γ_C = Γ₀ (load of R₀). Since the network represented by S can be considered as purely reactive, we have S₂₂ = Γ₀. The lossless nature of the network implies also that S is Hermitian; thus,

$S_{11}{S}_{21}^{\ast }+S_{12}{S}_{22}^{\ast }=0\text{and}{\left|S_{22}\right|}^2+{\left|S_{21}\right|}^2=1$

Since the network is reciprocal (S₁₂ = S₂₁ ) and S⁎₂₂ = S₂₂, Eq. (1.15) leads to

$S_{21}^2=-\frac{S_{11}{S}_{21}^{\ast }}{S_{22}}{S}_{21}\Rightarrow \frac{S_{11}}{S_{22}}=-\frac{S_{21}^2}{{\left|S_{21}\right|}^2}=-e^{j2\angle S_{21}}$

Using Eqs. (1.15), (1.16), the determinant S can be represented as

$\mathrm{\Delta }S=S_{11}{S}_{22}-S_{21}^2=\frac{S_{11}}{S_{22}}\left(S_{22}^2+{\left|S_{21}\right|}^2\right)=\frac{S_{11}}{S_{22}}$

Eq. (1.14) can be rearranged as

${\mathit{\Gamma }}_{\mathit{IN},c}=\frac{S_{11}}{S_{22}}\frac{S_{22}-{\mathit{\Gamma }}_C}{1-S_{22}{\mathit{\Gamma }}_C}=\frac{{\mathit{\Gamma }}_C-S_{22}}{1-S_{22}{\mathit{\Gamma }}_C}{e}^{j2\angle S_{21}}$

Note that

$\frac{{\mathit{\Gamma }}_C-S_{22}}{1-S_{22}{\mathit{\Gamma }}_C}=\frac{{\mathit{\Gamma }}_C-{\mathit{\Gamma }}_0}{1-{\mathit{\Gamma }}_0{\mathit{\Gamma }}_C}=\frac{R_C-R_0}{R_C+R_0}={\mathit{\Gamma }}_{\left.C\right|R_0}$

where Γ_C | R0is the reflection coefficient of R_C with respect to R₀. Therefore, we can rewrite Eq.(1.18) as

${\mathit{\Gamma }}_{\mathit{IN},c}=e^{j2\angle S_{21}}{\mathit{\Gamma }}_{\left.C\right|R_0}$

In other words, Γ_IN,c corresponds to Γ_C | R0 except for a phase factor of e^{j2 ∠ S₂₁}. As an example, the triangle symbols in Fig. 1.8 show the values of Γ_IN,c corresponding to a possible load modulation of Γ_c along the real axis. The trajectory of Γ_IN,c still is a straight line but tilted with respect to the real axis following Eq. (1.20).

We insert an offset line with characteristic impedance R₀ and electric length θ_c = ∠ S₂₁ between the matching network and R_C. The modified network, represented by $\tilde{S}$ (see Fig. 1.7), still matches R₀ to R_OPT, and the offset line introduces a delay θ_c, compensating e^{j2 ∠ S₂₁}. Invoking the reciprocity of $\tilde{S}$ and S, we have

$\angle {\tilde{S}}_{12}=\angle S_{12}-{\theta }_C=\angle S_{21}-{\theta }_C=\angle {\tilde{S}}_{21}$

Eq. (1.20) can therefore be rewritten as

${\mathit{\Gamma }}_{\mathit{IN},c}=e^{j2\angle S_{21}}{\mathit{\Gamma }}_{\left.C\right|R_0}=e^{j2\left(\angle S_{21}-{\theta }_C\right)}{\mathit{\Gamma }}_{\left.C\right|R_0}$

Hence, whatever load modulation acts on R_C, we set

${\theta }_c=\angle S_{21}+\mathit{n\pi },n\in \mathrm{\mathbb{N}}$

Then, the exactly same modulation is applied on Z_IN,c. In fact, in this case, we have

${\mathit{\Gamma }}_{\mathit{IN},c}={\mathit{\Gamma }}_{\left.C\right|R_0}\Rightarrow \frac{Z_{\mathit{IN},c}}{R_{\mathrm{OPT}}}=\frac{R_C}{R_0}=\alpha$

Fig. 1.8 (circle symbol) shows the behavior described by Eq. (1.24). When an offset line with electric length chosen according to Eq. (1.23) has been inserted, the modulation experienced by the reflection coefficient Γ_C is now exactly reproduced on Γ_IN,c. It should be noticed that the impedance is calculated before the impedance inverter and 2R₀ ~ R₀ load is converter to 2R_OPT~ R_OPT at the current source.

If the offset line introduces a loss A, Eq. (1.24) can be rewritten as

${\mathit{\Gamma }}_{\mathit{IN},c}={\mathit{\Gamma }}_{\left.C\right|R_0}{e}^{-2A}\Rightarrow \frac{Z_{\mathit{IN},c}}{R_{\mathrm{OPT}}}=\frac{\alpha +tanh\left(A\right)}{1+\alpha tanh\left(A\right)}$

In this case also, an offset line of length given in Eq. (1.23) ensures purely real load modulation but with reduced dynamic range when R_C ≠ R₀.

1.3.2.2 Offset Line at Peaking Amplifier

Similar considerations can be applied to the offset line of the peaking amplifier, for which analogous expression of Eq. (1.18) can be derived from Fig. 1.7, where the parameters are changed to those of the peaking amplifier. Since the peaking amplifier should be open at a low power operation, the flow direction is reversed. But we can derive exactly the same equation as follows:

${\mathit{\Gamma }}_{\text{OUT},p}=e^{j2\left(\angle S_{12}^{\left(P\right)}-{\theta }_P\right)}\frac{{\mathit{\Gamma }}_G-S_{11}^{\left(P\right)}}{1-S_{11}^{\left(P\right)}{\mathit{\Gamma }}_G}$

where S^(P) represents the S-parameter of the cascaded circuit of the reactive elements and matching network of the peaking amplifier, the latter designed to ensure the output matching. Γ_G is the peaking reflection coefficient similar to Γ_C. At a low-power drive, the peaking amplifier is turned off, and the intrinsic device behaves as an open circuit; thus,

${\mathit{\Gamma }}_{{\left.\text{OUT},p\right|}_{{\mathit{\Gamma }}_G=1}}=e^{j2\left(\angle S_{12}^{\left(P\right)}-{\theta }_P\right)}$

From Eq. (1.27), it is clear that, without the offset line, the open circuit at the intrinsic device output plane is not correctly reproduced at the common load plane, while we obtain Γ_{OUT, p} = 1 with an offset line of length:

${\theta }_P=\angle S_{12}^{\left(P\right)}+\mathit{n\pi },n\in \mathrm{\mathbb{N}}$

Since the matching network and reactive elements are composed of the reactive components, S₁₂ and S₂₁ have the same value. Therefore, the offset line for the peaking amplifier also assists for the load modulation like the offset line at the output of the carrier amplifier. With the offset line, the peaking amplifier properly operates; the output load of the peaking amplifier modulates from infinity to the R₀ while from infinity to R_OPT at the current source of a device. Since the offset lines at the carrier and peaking amplifiers rotate the same angle to the real impedance region, under the condition that the device output capacitances and the output-matching circuits are the same, the lengths of the two offset lines should be identical. Also, it is worth to be noticed that, with help of the quarter-wave inverter at the carrier amplifier, the impedance trajectories for the carrier and peaking amplifiers are lined up but at the different impedance levels, i.e., R₀ − R₀/2 and R₀ − ∞, respectively.

As Doherty described in his original paper, the Doherty load modulation circuit can be realized in a series voltage-combining mode of the two voltage sources. Fig. 1.9 shows the circuit schematic of the original Doherty amplifier with the series-connected load. The series-connected load properly combines the output powers delivered by the carrier and peaking amplifiers in a push-pull way since the load is ungrounded. It should be noticed that the impedance inverter is located at the peaking amplifier side and the load R_L is 2R_OPT instead of R_OPT/2 in the current-mode case.

When the peaking amplifier is in off state with a high impedance, the load seen by the carrier amplifier is R_L = 2R_OPT because the high impedance of the peaking amplifier is converted to a short by the inverter with Z_T = R_OPT. Conversely, when the carrier and peaking amplifiers deliver their full power, the two amplifiers equally share the 2R_OPT load. In between the two power levels, the loads seen by the carrier amplifier Z_C and peaking amplifier Z_P are modulated exactly the same way with current combining case. Since the Doherty modulation circuit provides the perfect matching, the calculation is simple.

$Z_C=R_L-\frac{{Z_O}^2}{Z_P}=\left(R_L\left(I_1-I_2\prime \right)+V_2\prime \right)/I_1=2R_{\mathit{OPT}}/\left(1+\alpha \prime \right)\mathrm{w}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e}{V}_2\prime =I_2\prime Z_P\prime =I_2\prime (R_L-Z_C)$

${Z_P}^{\prime }=\frac{R_L\left(I_2\prime -I_1\right)+V_1}{I_2\prime }=\frac{2R_{\mathit{OPT}}\alpha \prime }{\left(1+\alpha \prime \right)}\mathrm{w}\mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e}{V}_1=I_1{Z}_C=I_1(R_L-Z_P\prime )$

$Z_P=\frac{{Z_O}^2}{R_L-Z_C}=\frac{{Z_O}^2}{Z_P\prime }=\frac{R_{\mathit{OPT}}\left(1+\alpha \prime \right)}{2\alpha \prime }\mathrm{w}\mathrm{i}\mathrm{t}\mathrm{h}d=(I_2\prime )/I_1$

where, I₁ and V₁ are the carrier current and voltage, I₂ and V₂ are the peaking current and voltage, I₂′ and V₂′ are the peaking current and voltage transferred by the inverter, respectively.

Thus, the load modulation behavior at the voltage sources is identical to the parallel configuration as shown in Fig. 1.10. Therefore, the operational behavior is also identical with the same voltage and current responses for the two sources. Since the powers generated from the two amplifiers are combined in series way, the R_L is 2R_OPT instead of R_OPT/2 in the parallel case. It is evident that such a kind of configuration requires an output balun since the load is not connected to the ground, which is a big disadvantage of the series configuration.

1.4.1.2 Transformer Based Power Amplifier

The voltage-combining architecture is popular for a differential CMOS power amplifier with a transformer because the transformer can function as a voltage-combining balun. The differential structure is well suited for CMOS power amplifier to solve the low breakdown voltage and low power density of a CMOS device since the output load impedance is increased. The grounding problem of the CMOS power amplifier without via process is also solved by the differential structure. Therefore, a voltage-combined Doherty power amplifier based on the transformer is a natural choice for the CMOS process. The detailed load modulation behavior will be derived using the transformer-based CMOS Doherty power amplifier.

Fig. 1.11A shows a conceptual diagram of a conventional power amplifier architecture based on the transformer. I_PA represents the current source of the amplifier. The transformer transforms the 50 Ω load impedance to a lower impedance at the primary for a power match of the amplifier using 1:m transformer. Based on the transformer theory,

$V_2=m\cdot V_1$

$I_2=\frac{1}{m}\cdot I_1$

In the differential power amplifier shown in Fig. 1.11B, the impedances are given by

$R_L=\frac{V_2}{I_2}=\frac{2m^2\cdot V_0}{I_1}\left(\text{where}{V}_2=2m\cdot V_0\right)$

$Z_p=Z_n=\frac{V_0}{I_1}=\frac{R_L}{2m^2}$

The optimum impedances Z_p and Z_n are inversely proportional to 2m². However, in the single-ended power amplifier case shown in Fig. 1.11A, the impedances are

$R_L=\frac{V_2}{I_2}=\frac{m^2\cdot V_0}{I_1}\left(\text{where}{V}_2=m\cdot V_0\right)$

$Z_p^{\prime }=\frac{V_0}{I_1}=\frac{R_L}{m^2}$

The optimum impedance Z_p′ is two times larger, and the power cell size should be a half of the differential case. Therefore, the power level at the same matching impedance is 6 dB lower than that of the differential power amplifier. Therefore, the differential amplifier has a big advantage for power match of a high-power amplifier with a low impedance level.

1.4.1.3 Transformer Based Voltage Combined Doherty Amplifier

The transformer can modulate the load seen by the differential amplifiers, and this load modulation characteristic can be applied to the dynamic load modulation for a Doherty power amplifier. Fig. 1.12 shows the operational diagram of the voltage-combined Doherty power amplifier with a transformer. I_C and I_P are the current sources representing the carrier and peaking amplifiers, respectively, and their operations are identical to the current-combining case as described before. For the proper modulation with the voltage combining, the quarter-wave inverter is attached at the peaking amplifier. When the peaking amplifier is turned off, the open impedance of the peaking is converted to the short at the transformer. Therefore, the carrier amplifier is connected to the 2R_OPT load instead of R_OPT/2 for the current-combining case (1:1 ratio case). When the two amplifiers generate their full powers, the two amplifiers share the load, R_OPT each, and their powers are combined in the voltage-combining way. In between the two power levels, the transformer combines the two output powers properly as described below.

The modulation behavior can be calculated the same way as the current-combining case. It is assumed that each current source is linearly proportional to the input voltage after it is turned on, operating as a class B amplifier with harmonic short circuits. The peaking amplifier turns on at a half of the maximum input voltage. The phase difference between the carrier and peaking amplifiers is adjusted at the input. The two antiphased voltage signals are applied to the primary ports of the transformer, and the two signals are properly combined at the secondary output port. But, in this design, the carrier and peaking amplifiers do not operate in differential mode.

Fig. 1.13 shows the fundamental current and voltage amplitudes according to the input drive voltage. In the low-power region (0 < V_in < V_{in, max}/2), the peaking amplifier remains in the cutoff state, and the load impedance of the carrier amplifier is two times larger than that of the conventional amplifier. The operational behavior is the same as the single-ended operation explained earlier. The peaking amplifier's output impedance is infinity due to the open state. The quarter-wave inverter inserted at the output of the peaking amplifier transfers it to a short condition at the V′_P node.

In the high-power region (V_{in, max}/2 < V_in < V_{in, max}), where the peaking amplifier is conducting, the load impedances of the carrier amplifier and peaking amplifier are modulated. Assuming that transconductance of the peaking amplifier is two times larger than that of the carrier amplifier, the current swings of the two amplifiers increase in proportion to the input voltage level, and they are shown in Fig. 1.13A. The voltage swing of the peaking amplifier reaches to the V_max only at the maximum input voltage while that of the carrier amplifier remains at V_max. This behavior can be explained using the modulated load impedances.

The load impedances seen by the carrier and peaking amplifiers can be calculated by using Eqs. (1.34), (1.35) with $V_0=V_C-V_P^{\prime }$ and given in Eqs. (1.38), (1.40), respectively (where $0<V_P^{\prime }<V_C$):

$Z_{\mathrm{OPT},c}=\frac{V_C}{I_C}=\frac{R_L\cdot V_C}{m^2\left(V_C-V_P^{\prime }\right)}\left(\text{where}{I}_C=I_1\right)$

$Z_{\mathrm{OPT},p}^{\prime }=\frac{V_P^{\prime }}{I_P^{\prime }}=\frac{R_L\cdot V_P^{\prime }}{m^2\left(V_P^{\prime }-V_C\right)}\left(\text{where}{I}_P^{\prime }=I_1\right)$

$Z_{\mathrm{OPT},p}=\frac{m^2\cdot R_{\mathrm{OPT}}^2\cdot \left(V_P^{\prime }-V_C\right)}{R_L\cdot V_P^{\prime }}$

Z_OPT,p is Z′_OPT,p inverted by R_OPT inverter. Therefore, the load impedances of the carrier and peaking amplifiers are dynamically modulated according to the input power level. Using Eqs. (1.38), (1.40) and the currents in Fig. 1.13A, the calculated voltage profiles are shown in Fig. 1.13B, where R_L = 2R_OPT and m = 1 are assumed for a simple analysis (also a popular approach for a proper transformer design).

The magnitudes of the output currents I_c and $I_P^{\prime }$ at the primary of the transformer are the same with the I_L at the secondary (where I_c = − I _P  = I₁ = I_L) as shown in Fig. 1.14A. Since the currents are the same, the output voltages generated by the two amplifiers are voltage combined at the secondary of the transformer as shown in Fig. 1.14A. In the low-power region, the load impedance of Z′_OPT,p at the combining node is maintained at zero, thanks to the quarter-wave inverter, as shown in Fig. 1.14C, and the carrier amplifier with the load impedance of 2R_OPT achieves a peak efficiency at 6 dB power back-off (PBO) point under the single-ended operation. In the high-power region, through Eqs. (1.38), (1.40), the transformer with the quarter-wave inverter properly modulates the load impedance seen by each carrier (from 2R_OPT to R_OPT) and peaking (from ∞ to R_OPT) amplifiers as shown in Fig. 1.14D. The load impedance of Z′_OPT,p is inverted following Eq. (1.39).

As mentioned earlier, a differential operation is preferred for CMOS power amplifier. But the structure is not a differential mode and should be modified. A simple method is to operate the carrier and peaking amplifiers in differential mode, separately, and the four cells of the amplifiers are combined using a single transformer. Fig. 1.15 shows the circuit structure of the differential CMOS Doherty amplifier. The output power is four-way combined in this structure, which increases the output power by eight times for the same load impedance. Also, the imaginary part of the device impedance should be controlled properly using an offset line or parallel resonation of the output capacitor at the drain terminal as we have described earlier.

1.4.3.1 Using R_OPT/2 Inverter

In a conventional Doherty amplifier, the output-matching circuit of the carrier amplifier is designed to match the optimum output impedance of R_OPT at the peak output power region to R₀, and the characteristic impedances of the offset line and quarter-wave inverter are set to the same impedance, R₀, as depicted in Fig. 1.17A. The offset line and inverter modulate the load for matching to 2R_OPT at the back-off power region, while the match at the peak-power operation is not affected by the modulation circuit. In this design, the accurate output matching at the first peak efficiency region is very difficult due to the nonlinear load modulation behavior of the amplifier with a low matching tolerance. The load modulation does not behave ideally either due to the nonlinear device parameters variation. However, to get a high efficiency for amplification of a modulated signal, the accurate match at the back-off power region is more important than that at the peak-power region.

To solve the problem, the output-matching circuit of the carrier amplifier is matched at the output power level with the first peak efficiency, from 2R_OPT optimum load to R₀/2 load. The impedance inverter and offset line of the carrier power amplifier are also designed with the characteristic impedance of R₀/2, and the match is not affected by the load modulation circuit (Fig. 1.17B). The load is modulated for match at the high-power region. The new offset line compensates the reactive element effect for matching from R_OPT to R₀/4 load as shown in Fig. 1.18, and the R₀/4 load is inverted to R₀. And the load modulation behavior of the carrier amplifier is the same as the conventional design.

We can design the peaking amplifier matched at the first peak region, similarly to the carrier amplifier. But the peak-power region is more important for the peaking amplifier since no power is generated at the first peak region and the peaking amplifier is designed the same way as the conventional case.

Fig. 1.19 shows the output impedance trajectory of the carrier amplifier through the load modulation, which is simulated with a Cree gallium nitride (GaN) HEMT CGH40045 model. In the Doherty amplifier design, the efficiency at the first peak region is very important because overall efficiency is determined by the efficiency, while the power is important at the peak-power region because the power limits the dynamic range of the load modulation while the efficiency does not affect the overall efficiency significantly. Therefore, the carrier power amplifier is efficiently matched to R₀/2 at the back-off power with 2R_OPT, and the offset line is adjusted to deliver the maximum output power at the peak power. As shown in Fig. 1.19, this design concept of the first peak match has advantage in realization because the power contour at the peak-power region has a large tolerance of the matching impedance and the carrier power amplifier can be matched accurate to the high efficiency region at the low power region with low tolerance.

1.4.3.2 Using 2R_OPT Inverter

The other method is the use of the inverter with

$Z_T=R_L=2R_0$

Here, the carrier and peaking amplifiers are matched to 2R₀ load from 2R_OPT device impedance at the first peaking efficiency region. In this Doherty amplifier design shown in Fig. 1.20, the output impedance of the carrier amplifier Z_m is given by

$Z_m=\frac{V_c}{I_c}={Z_T}^2\cdot \frac{I_T}{V_L}={Z_T}^2\cdot \frac{I_L-I_a}{V_L}=\left(\frac{Z_T}{R_L}-\frac{I_a}{I_C}\right)\cdot Z_T$

$I_T=\frac{I_m\cdot Z_m}{Z_T}=\frac{I_m\cdot Z_T}{Z_L}\mathrm{with}{Z}_L=\frac{V_L}{I_T}$

$Z_a=V_L/I_a=I_m\bullet Z_T/I_a$

At the peak-power operation, the impedance of the carrier amplifier is R_OPT, and this impedance is transferred to 4R₀ by the inverter with Z_T = 2R₀. Therefore, I_T given by Eq. (1.43) should be identical to I_a and is given by

$I_T=I_m/2=I_a$

With Eqs. (1.44, (1.45), the I_m and I_a profiles versus the input voltage V_in are shown in Fig. 1.21, which are mathematically given as

$I_m=\frac{V_{\mathrm{in}}}{V_{\mathrm{in},\text{max}}}\left(I_{\text{max}}/2\right)={\upsilon }_{\mathit{in}}\left(I_{\mathit{max}}/2\right)$

$I_a=\left\{\begin{array}{cc}0,& 0\le {\upsilon }_{\mathit{in}}<0.5\\ \left({\upsilon }_{\mathit{in}}-\frac{1}{2}\right)\left(\frac{I_{\text{max}}}{2}\right),& 0.5\le {\upsilon }_{\mathit{in}}\le 1\end{array}\right.$

The I_a versus V_in function in Eq. (1.47) can be easily realized in practice using a peaking device with the same size as the main device, except biased in class C. But only a half of the current capability of the peaking amplifier is utilized.

Z_m, the impedance seen by the carrier device, is identical to that of the conventional Doherty with perfect tracking of 2R_OPT for up to 6 dB of back-off power. At the peak power, the peaking device now sees 4R_OPT instead of R_OPT because V_L is doubled while I_a is halved. Fig. 1.22 shows the load modulation in the Doherty amplifier calculated using Eqs. (1.42) and (1.44).

The voltages across the carrier and peaking devices, V_m and V_a, can be calculated using (1.42) and (1.46), (1.44) and (1.47), respectively. The voltage profile is shown in Fig. 1.23. As shown, the V_m is identical to that of the conventional Doherty amplifier in Fig. 1.3 in Section 1.3. On the other hand, the voltage V_L across the peaking device and the load now swings twice as much as the V_L of the conventional Doherty amplifier in the figure. As such, the DC drain bias of the peaking amplifier needs to be twice that of the carrier amplifier. From a practical perspective, the need for asymmetrical bias voltages implies that only a half of power capability of the carrier device is utilized for the power generation.

The efficiency curve and the peak output power are identical to that of the conventional Doherty power amplifier as shown in Fig. 1.24. This design method can achieve the goal of the accurate first peak match. But the carrier amplifier utilizes a half of the available voltage swing and the peaking amplifier a half of the current maximum current-handling capability. Those problems are serious limitation for this design technique. As we mentioned earlier, the peaking amplifier in the conventional Doherty amplifier utilizes a half of the current available, also. This problem can be solved by uneven drive that will be discussed in the next chapter.