3.2.1 Optimized Design of Carrier and Peaking Amplifiers

In a conventional Doherty architecture, the input of the carrier amplifier is conjugate-matched at the peak power with the output load of R_OPT. This match produces mismatch at a back-off power level and degrades the gain and the PAE. To solve the problem, the input should be matched at the first peak efficiency point.

Fig. 3.7A shows the nonlinear equivalent circuit model of the GaN HEMT. Here, we assume that the current source sees the load R_L for a power match. The extracted input capacitance, C_in, of the model is given by

$C_{\text{in}}=C_{\mathit{gs}}+C_{\mathit{gd}}\left(1+g_m{R}_L\right)$

The C_gs increases as the input power increases. The output load, R_L, of the carrier amplifier decreases from 2R_OPT to R_OPT through the load modulation. As a result, the input capacitance, C_in, of the carrier amplifier is varied as the input power increases as depicted in Fig. 3.7B. This C_in variation affects the power matching and gain.

Fig. 3.8 shows the source-pull simulation results for the fundamental impedance matching points of the carrier amplifier for the output load impedances of R_OPT and 2R_OPT. The input power level for R_OPT is 6 dB higher than that for 2R_OPT. As the load impedance is modulated from 2R_OPT to R_OPT with the increased input power, the effective input capacitance decreases. By matching the input impedance at the first peak power level with the 2R_OPT load, the gain of the carrier amplifier at the back-off region can be matched accurately with high efficiency although the matching tolerance is small. The slight mismatch at the lower power region (below the first peak power) provides a flat gain of the Doherty amplifier because the gain at the lower power region is higher than that at the first peak power due to the smaller C_in. The power match at the higher power operation is maintained because the optimum impedance contour at the high power region is insensitive due to the saturated operation with large tolerance as shown in the figure.

In Fig. 3.9, the CW characteristics of the first peak input matched carrier amplifier is compared with the peak power matched conventional amplifier. The new design allows a proper Doherty modulation since the gain difference between the 2R_OPT and R_OPT matches is about 3 dB. However, the conventional design can achieve the load modulation through the saturated operation of the peaking amplifier only because the two gains are almost identical. This load modulation through the saturated operation is described in Section 5.2.

The input of the peaking amplifier is conjugate-matched at the high power level to maximize the gain at the peak power level. The harmonics of the output impedance for the carrier and peaking amplifiers are matched to the optimum impedances for a high saturated drain efficiency, using LC parallel network circuits. The design method of the saturated amplifier can be found at the further reading. Fig. 3.10 represents the schematic of the proposed Doherty amplifier, which is implemented in MMIC.

3.2.2 Operation of the Optimally Matched Doherty Amplifier

For the simple circuit topology in MMIC, the fundamental output impedance at the output node of the carrier amplifier increases from 50 to 100 Ω, instead of the conventional design of 25 to 50 Ω, and that of the peaking amplifier decreases from infinity to 100 Ω as shown in Fig. 3.11A. For the optimum Doherty operation, the input power driving needs to be an uneven drive. The uneven input dividing is normally realized using the uneven power divider. It can be achieved using the nonlinear input capacitance of the peaking amplifier also as described in Section 5.3.1. Similarly to the nonlinear capacitance case, we could easily realize the uneven input dividing using the input matching. As shown in Fig. 3.11B, 1 dB more power is delivered to the carrier amplifier at the low-power operation and to the peaking amplifier at the high power. Fig. 3.12 shows a CW simulation result of the Doherty amplifier implemented at 1.8 GHz using TriQuint 3MI 0.25 m gallium nitride (GaN) high-electron-mobility transistors (HEMT) MMIC. The DE is more than 52% at the 6 dB back-off power and 59% at the peak power without degradation during the load modulation. Through the optimized input matching for the carrier amplifier, the gain at the back-off power is high for the single stage amplifier, over 19.5 dB. Because of the high gain of the carrier amplifier at the back-off power level, the gate bias voltage for the peaking amplifier can be increased, preventing the gain degradation of the Doherty amplifier at the modulation region as shown in Fig. 3.12.

The implemented integrated circuit size except for the RF choke inductor is 2.28 × 3.09 mm as shown in Fig. 3.13. Drain bias voltage is 28 V for both the carrier and peaking amplifiers, and gate bias voltages are − 2.8 V for the carrier amplifier and − 3.26 V for the peaking amplifier. The Doherty amplifier is tested using an LTE signal with 10 MHz bandwidth and 6.5 dB PAPR at 1.8 GHz. The Doherty amplifier achieves a drain efficiency of 57.2% (PAE of 56.3%) and a gain of 18.8 dB at an average output power of 35.6 dBm.

3.3.1 Optimized Design of Peaking Amplifier for Proper Doherty Operation

For the proper load modulation of the Doherty amplifier, the output currents of the carrier and peaking amplifiers should be increased with the input voltage as shown in Fig. 3.14. To get the current prolife, as we have discussed earlier, the transconductance of the peaking amplifier should be two times larger than that of the carrier amplifier. To minimize the production cost, however, the device sizes of the carrier and peaking amplifiers are the same since they generate the same maximum power. To overcome the lower power problem, the uneven input drive or the gate bias adaptation technique can be employed.

The problem can be solved by the input second harmonic voltage control, also. Usually, the input second harmonic load of a power amplifier is shorted for a small conduction angle of the output current, which is required for a high-efficiency operation. However, we can utilize the input second harmonic voltage generated from the nonlinear input capacitor to increase the conduction angle and thereby increase the output power. The input capacitance variation for the bias voltage has a reverse characteristic to the output capacitor, that is, it increases as the gate-source voltage increases as shown in Fig. 3.15A, and it generates the out-phased second harmonic voltage. In contrast to the in-phased second harmonic voltage, the out-phased second harmonic voltage flattens the peak of the voltage waveform as shown in Fig. 3.15B. With the flattened input voltage waveform, the effective conduction angle increases, compensating the reduced conduction angle of the peaking amplifier due to the class C bias. In addition, the peak value of the input voltage decreases, allowing the peaking amplifier to turn on late at the same gate bias condition. Therefore, the peaking amplifier with the peak flattened input voltage waveform is suitable for the ideal Doherty operation. To take full advantage of the nonlinear input capacitor, the input second harmonic load should be an inductive load. As shown in Fig. 3.15C, the peak input voltage decreases with the properly tuned inductive second harmonic load.

3.3.2 Simulation and Experimental Results

To validate the inductive harmonic tuning concept, a Doherty amplifier is designed at 2.14 GHz using TriQuint 0.25 μm GaN HEMT process. With the inductive input second harmonic load for the peaking amplifier, the input voltage has a peak flattened waveform. Due to the voltage waveform, the conduction angle of the peaking amplifier increases, and the peak input voltage is decreased as shown in Fig. 3.16.

Fig. 3.17 shows the CW performances of the designed carrier and peaking amplifiers. The input second harmonic load of the carrier amplifier is shorted, and the peaking amplifiers are designed with the short and inductive loads. V_GS is − 3 V for the carrier amplifier and − 4.5 V for the peaking amplifier. With the second harmonic short, the peaking amplifier delivers a lower output power and a higher efficiency than the carrier amplifier. However, with the inductive input second harmonic load, the peaking amplifier generates a larger output power, comparable with the carrier amplifier. In addition, with the same gate bias condition, the peaking amplifier with the inductive input second harmonic load turns on later than that of the peaking amplifier with the input second harmonic short circuit. These CW characteristics of the peaking amplifier are beneficial for the Doherty amplifier operation. Although the efficiency is degraded a little, the power is more important for the peaking amplifier.

Fig. 3.18 shows the schematic of the Doherty amplifier adopting the second harmonic tuned peaking amplifier. To realize the inductive input second harmonic load, an inductor is added after the second harmonic short circuit at the input of the peaking amplifier. The device size of the peaking amplifier is the same as that of the carrier amplifier. V_GS of the peaking amplifier is increased to − 4.3 V to get the same turn-on voltage. Fig. 3.19 shows the two-tone performance of the Doherty amplifier. At the output power of 37 dBm, the IMD3s at the two sides are lower than − 35 dBc, and the power-added efficiency is 47% (including the DC power consumption of the drive stage).

Fig. 3.20 shows the fabricated Doherty amplifier based on the schematic in Fig. 3.18. The integrated circuit size except for the RF choke inductor is 2.3 × 3.5 mm. The drain bias voltages are 28 V for the power stage of the carrier and peaking amplifiers and 20 V for the drive amplifier. The gate bias voltages of the drive amplifier and the carrier amplifier are − 2.8 V and that for the peaking amplifier is − 4.2 V. Fig. 3.21 shows the measured two-tone performance of the fabricated Doherty amplifier, which is similar to the simulation one. Fig. 3.22 shows the performance of the fabricated Doherty amplifier for the LTE signal at 2.14 GHz with a 10 MHz bandwidth and 6.5 dB PAPR. At the output power of 46.7 dBm, ACLR is − 35 dBc, PAE is 46.7% (including the DC power consumption of the drive stage), and gain is 29.3 dB.

In conclusion, the peaking amplifier cannot deliver the same maximum output power as that of the carrier amplifier because of the low gate bias voltage of the peaking amplifier and cannot properly modulate the load like an ideal Doherty amplifier. To solve the problem, the inductive input second harmonic load is employed. With the harmonic load, the input voltage becomes the peak flattened waveform, and it enlarges the conduction angle of the peaking amplifier. Therefore, the reduced conduction angle of the peaking amplifier, due to the low gate bias, is restored, and the proper Doherty operation could be realized.

3.4.1 Operational Principle of the Saturated Doherty Amplifier

The efficiency of the Doherty amplifier can be enhanced by employing the carrier and peaking amplifiers based on the class F^− 1 mode. Fig. 3.23 shows the schematic diagram of the fully matched saturated Doherty amplifier including the HCC and offset lines.

Fig. 3.23A shows an operational diagram of the saturated Doherty amplifier. For the Doherty operation, the carrier amplifier is biased at the pinch off and the peaking amplifier below the pinch off. The current and voltage waveforms at the devices of the carrier and peaking amplifiers are shaped by the harmonic impedances of the HCC. Theoretically, the high efficiency can be achieved in class F operation by generating half-sinusoidal current and square-wave voltage waveforms. These waveforms can be realized by creating the zero impedances at all even harmonics and infinite impedances at all odd harmonics. However, in a practical design, all harmonic contents cannot be controlled. Moreover, the amplifiers do not operate in the saturated mode for all power levels, either. Thus, a HCC, which can control the second and third harmonics, has been employed in front of the output matching circuit since the HCC does not need to be modulated. The Doherty circuit topology is depicted in Fig. 3.24. The HCC, which is shown in Fig. 3.25, shows the open and short circuits for the class F harmonic tuning. The harmonic matching impedances should not be changed with the matching and load modulation circuits. For the purpose, the second and third shorts are introduced after cutting off the impedance modulation effect. For proper Doherty operation, the offset line at the back of the output matching circuit has also been employed. Therefore, the harmonic control circuit is attached right at the drain terminal, and a tuning line is added for compensating the harmonic detuning effect by the devices' output capacitance. The amplifier circuit topology is depicted in Fig. 3.25.

The analysis of the circuit is based on the following assumptions:

1. (1) Each current source is linearly proportional to the input voltage above the pinch-off voltage.
2. (2) The voltage waveform depends only on the fundamental and third harmonic components.
3. (3) The maximally flat voltage waveform is generated by a 1/9 amplitude ratio and 180 phase difference between the fundamental and third harmonic component voltages, which is the voltage waveform of a class F amplifier.
4. (4) The fundamental load impedance is properly modulated using the uneven power drive.

Fig. 3.23B represents the magnitudes of the fundamental current and voltage according to the input drive voltage. Since the current and voltage waveforms represent the half-sinusoidal current and maximally flat voltage waveforms, I_1,max and V_1,max are a half of i_peak and 9/8 of V_DC, respectively. Here, I_1,max and V_1,max are the maximum fundamental components of the current and voltage, respectively; i_peak is the maximum current, and V_DC is the dc bias voltage. At the low-power region (0 < V_in < V_{turn on}), where only the carrier amplifier is active, the fundamental and dc currents of the amplifier are given by

$I_C=I_{1,\max }\left(\frac{v_{\text{in}}}{V_{\max }}\right)$

$I_{\mathit{DC},C}=I_{\mathit{dc},c}\left(\frac{v_{\text{in}}}{V_{\max }}\right)$

where I_dc,c is 1/π of i_peak and V_max is the maximum input voltage.

To analyze the load modulation behavior of the saturated Doherty amplifier, we use Z_T = R_OPT and Z_L = R_OPT/2, in Fig. 3.23A. The load impedance of the carrier amplifier Z_C is given by

$Z_C=\frac{Z_T^2}{Z_L}=2R_{\mathrm{OPT}}\text{where},R_{\mathrm{OPT}}=\frac{9}{8}\left(\frac{V_{\mathit{DC}}}{I_{1,\max }}\right)$

Due to the maximally flat voltage waveform, the fundamental voltage component is 9/8 times larger impedance than that of the class B amplifier. Thus, the load impedance of each amplifier is designed to have 9/8 times larger impedance than the conventional amplifier.

At the higher power region, both the carrier and peaking amplifiers are active. The amplifier is unevenly driven with the power ratio σ, which is defined in Eq. (2.4):

$\sigma =\frac{I_{1,\max }}{I_{1,p}\left(1-\psi \right)}$

where

$\psi =\frac{V_{\text{turn}\mathrm{on}}}{V_{\max }}$

$I_{1,p}=\frac{I_{\max }}{2\pi }\cdot \frac{{\theta }_p-sin{\theta }_p}{1-cos\left({\theta }_p/2\right)}$

Here, ψ is the turn-on portion, and I_{1, p} is the fundamental component of the peaking current with a conduction angle of θ_p.

The fundamental and dc currents of the peaking amplifier are expressed as

$I_P=\sigma I_{1,p}\left(\frac{v_{\text{in}}}{V_{\max }}-\psi \right)$

$I_{\mathit{DC},P}=\sigma I_{\mathit{dc},p}\left(\frac{v_{\text{in}}}{V_{\max }}-\psi \right)$

$I_{\mathit{dc},p}=\frac{I_{\max }}{2\pi }\cdot \frac{2sin\left({\theta }_p/2\right)-{\theta }_{p}cos\left({\theta }_p/2\right)}{1-cos\left({\theta }_p/2\right)}$

The load impedances of the carrier and peaking amplifiers are given by

$Z_C=\frac{Z_T^2}{\left[Z_L\cdot \left(1+I_P/I_C^{\prime }\right)\right]}$

$Z_P=Z_L\left(1+\frac{I_C^{\prime }}{I_P}\right)$

The fundamental load impedance of the carrier amplifier is modulated from 2R_OPT to R_OPT, and the load impedance of the peaking amplifier modulated from ∞ to R_OPT while the second harmonic short and third harmonic open impedances are maintained.

3.4.2 Efficiency and Linearity of the Saturated Doherty Amplifier

The power-level-dependent operation is explored by defining the saturation state and the unsaturation state according to the amplitude ratio/phase difference between the fundamental and third harmonic voltage components. The amplitude ratio α and the relative phase difference β are expressed as

$\begin{array}{c}V\left(t\right)=V_{\mathit{DC}}+V_{1}cos\left(\mathit{\omega t}+{\varphi }_1\right)+V_{3}cos\left(3\mathit{\omega t}+{\varphi }_3\right)\\ =V_{\mathit{DC}}+V_{1}cos\left({\varphi }_1\right)+V_{3}cos\left({\varphi }_3\right)\end{array}$

$\alpha =\left|\frac{V_3}{V_1}\right|$

$\beta ={\varphi }_1-{\varphi }_3$

where V₁ and V₃ are magnitudes of the fundamental and third harmonic voltages, respectively. ϕ₁ and ϕ₃ are phases of the fundamental and third harmonic voltages, respectively. At the saturation state, the amplifier should generate the half-sinusoidal current and maximally flat voltage waveforms with α = 1/9 and β = 180° at the given drive level. α and β values of the saturated Doherty amplifier have been investigated using the ADS simulator. Based on the data, we have analyzed the efficiency and the linearity.

3.4.2.1 Efficiency of the Saturated Doherty Amplifier

The efficiency analysis can be carried out using only the fundamental and dc components according to the current and voltage waveforms. At the low-power region (0 < V_in < V_{turn on}) where only the carrier amplifier is turned on, the RF and dc powers are given by

$\begin{array}{c}{P}_{\mathit{RF}}=\frac{1}{2}{I}_C^2\cdot Z_C\\ =\frac{I_{1,c}^2}{2}{\left(\frac{v_{\text{in}}}{V_{\max }}\right)}^2\cdot 2Z_0\\ =I_{1,c}{\left(\frac{v_{\text{in}}}{V_{\max }}\right)}^2\cdot \left(\frac{9}{8}\right)V_{\mathit{DC}}\end{array}$

  (3.26)

$\begin{array}{l}{P}_{\mathit{DC}}=I_{\mathit{DC},C}\cdot V_{\mathit{DC}}\\ =I_{\mathit{dc},c}\left(\frac{v_{\text{in}}}{V_{\max }}\right)\cdot V_{\mathit{DC}}\end{array}$

  (3.27)

From Eqs. (3.26), (3.27), the efficiency becomes

$\eta =\frac{P_{\mathit{RF}}}{P_{\mathit{DC}}}\times 100=\frac{I_{1,c}}{2I_{\mathit{dc},c}}\cdot \frac{9}{8}\left(\frac{v_{\text{in}}}{V_{\text{turn}\mathrm{on}}}\right)\times 100$

  (3.28)

The carrier amplifier operates at the unsaturated state until the (8/9) V_{turn on} input drive level. At this level, the amplifier has a class B peak efficiency due to the larger load impedance as shown in Fig. 3.26. The efficiency increases further to that of the third harmonic tuned class F amplifier as the amplifier is pushed into saturation. The peaking amplifier operates similarly. The efficiency of the peaking amplifier is slightly higher with deeper class C operation.

The load lines are slightly elliptical at a low drive level, and the load line of the carrier amplifier reaches to the minimum allowable voltage at the peaking turn-on point, as shown in Fig. 3.27A where the turn-on voltage of the peaking amplifier (V_{turn on}) is set to V_max/2. The amplifier reaches to the saturation state above this drive level, and as shown in Fig. 3.26, the efficiency increases from the class B peak efficiency (point A) to the class F peak efficiency (point B). The load line changes from the slightly elliptical to the quasi-“L” curve at the turn-on voltage, as shown in Fig. 3.27A, but the line cannot make the perfect “L” curve because the harmonic voltage control is limited to the third harmonic. This state illustrates that the amplifier has the half-sinusoidal current and maximally flat voltage waveforms, and the efficiency can reach to the peak efficiency of the class F amplifier with third harmonic tuning, i.e., 88%.

At the higher power region (V_{turn on} < V_in < V_max), both amplifiers are active. The RF and dc powers are sum of the two amplifiers' and are given by

$\begin{array}{c}{P}_{\mathit{RF}}=\frac{1}{2}\left(I_C^2{Z}_C+I_P^2{Z}_P\right)\\ =\frac{V_{\mathit{DC}}}{2}\left(\frac{9}{8}\right)\left[\frac{2I_{1,\max }^2{V}^3}{\left(I_{1,\max }+\sigma I_{1,p}\right)V-\sigma I_{1,p}\psi }+\frac{\sigma I_{1,p}\left(V-\psi \right)\left\{\left(I_{1,\max }+\sigma I_{1,p}\right)V-\sigma I_{1,p}\psi \right\}}{2I_{1,\max }}\right]\end{array}$

  (3.29)

$\begin{array}{c}{P}_{\mathit{DC}}=\left(I_{\mathit{DC},C}+I_{\mathit{DC},P}\right)\cdot V_{\mathit{DC}}\\ =\left[I_{\mathit{dc},c}V+\sigma I_{\mathit{dc},p}\left(V-\psi \right)\right]\cdot V_{\mathit{DC}}\end{array}$

  (3.30)

From Eqs. (3.29), (3.30), the efficiency becomes

$\begin{array}{c}\eta =\frac{P_{\mathit{RF}}}{P_{\mathit{DC}}}\times 100\\ =\frac{1}{2}\left(\frac{9}{8}\right)\frac{\left[\frac{2I_{1,\max }^2{V}^3}{\left(I_{1,\max }+\sigma I_{1,p}\right)V-\sigma I_{1,p}\psi }+\frac{\sigma I_{1,p}\left(V-\psi \right)\left\{\left(I_{1,\max }+\sigma I_{1,p}\right)V-\sigma I_{1,p}\psi \right\}}{2I_{1,\max }}\right]}{\left[I_{\mathit{dc},c}V+\sigma I_{\mathit{dc},p}\left(V-\psi \right)\right]}\times 100\end{array}$

  (3.31)

where,

$V=\frac{v_{\text{in}}}{V_{\text{in},\max }}$

Since the load impedances of the both amplifiers decrease, the load lines of the carrier amplifier move up while maintaining the quasi-“L” curves, as shown in Fig. 3.27A, and the carrier amplifier operates in the saturation state. On the other hand, the current and voltage swings of the peaking amplifier increase in proportion to the drive level due to the proper load modulation, but the amplifier maintains the unsaturation state until it reaches to the minimum allowable output voltage level (point C). In this situation, the load lines of the amplifier are slightly elliptical until it reaches to the minimum allowable output voltage level. For the input power higher than that of the point C operation, the load line becomes the quasi-“L” curve, as shown in Fig. 3.27B. The peaking amplifier reaches to the saturation state after it passes the minimum allowable output voltage level, and both amplifiers have the half-sinusoidal current and maximally flat voltage waveforms at the maximum drive level (point D). The efficiency of the saturated Doherty amplifier, which is the average efficiency of the two amplifiers, is higher than the peak efficiency of the carrier amplifier due to the higher efficiency of the class C bias peaking amplifier, as shown in Fig. 3.27. The operation states of the Doherty amplifier are summarized in Table 3.1.

Table 3.1

Operation State of the Carrier and Peaking Amplifiers According to Each Power Level

	Low-Power Region (A)	Medium-Power Level (B)	High-Power Region (C)	High Power Level (D)
Carrier amplifier	Unsaturated state	Saturation state	Saturation state	Saturation state
Peaking amplifier	Turn off	Turn on	Unsaturated state	Saturation state

3.4.2.2 Linearity of the Saturated Doherty Amplifier

The linearity of the saturated Doherty amplifier is worse than that of conventional Doherty amplifier because the carrier and peaking amplifiers are operated as saturated amplifiers to maximize the efficiency. In the low-power region, the linearity of the amplifier is entirely determined by the carrier amplifier like the conventional one. But the saturated amplifier has a poor linearity. Moreover, the carrier amplifier has a larger impedance load than that of the conventional one, and the amplifier reaches to saturation at a lower input drive level. Thus, the linearity is worse than the conventional Doherty amplifiers and is similar to the class F amplifier. However, in the high-power region, the linearity can be improved by the harmonic cancellation between the two amplifiers with appropriate gate biases like a conventional Doherty amplifier. Due to the linearity improvement mechanism, the Doherty amplifier can be more linear than the switching or saturated amplifiers.

Fig. 28A shows IM3 amplitudes of the carrier and peaking amplifiers and their phase difference. As already stated before, the carrier amplifier has relatively poor linearity with the high IM3 in the low-power region. In the high-power region where the carrier and peaking amplifiers are active, through proper gate bias arrangement of the two amplifiers, we can have IM3 amplitudes of both amplifiers are the same and the phase difference is maintained at ~ 180°. The IMD3 of the Doherty amplifier can be reduced by the harmonic cancellation, as shown in Fig. 3.28B. Therefore, the saturated Doherty amplifier can operate as a reasonably linear amplifier with very high efficiency in spite of the saturated operation, while the class F amplifier cannot.

3.4.3 Improved Harmonic Control Circuit for Saturated Amplifier

In the previous session, we have discussed the Doherty amplifier based on the class F amplifier. However, the saturated amplifier with the second harmonic control, which is not the short or open circuit but an inductive load, can provide very high efficiency, with very simple circuit and the Doherty amplifier based on the saturated amplifier is introduced in this section. The detailed operational behavior of the saturated amplifier can be found in Further Reading of this chapter. A conventional way to tune the second harmonic load in the saturated amplifier is to resonate at the second harmonic frequency using a capacitor. This capacitor is located at the end of the drain bias line and tunes the second harmonic impedance in the slightly inductive region from the resonation. Unfortunately, the second harmonic tuning is affected by the fundamental load modulation of the Doherty network, leading to a mismatch. Therefore, a new second harmonic tuning circuit, without being affected by the load modulation, is needed.

For the carrier amplifier, we generally employ R_O = 50 Ω to R_OPT matching circuit. To get the 2R_OPT load, two impedance transformers (50–25 and 25–100 Ω) and the offset line is used as shown in Fig. 3.29A. The impedance transformers have 90^° electric length at the fundamental frequency, and the second harmonic matching impedance is not affected by these transformers. Also, the offset line has 50 Ω characteristic impedance. Therefore, the second harmonic matching impedance for the carrier amplifier is not affected by the load modulation circuit. But an offset line is employed at the peaking amplifier also to make an open circuit at the combining node. However, this offset line cannot provide the open impedance at the second harmonic frequency as shown in Fig. 3.29B, inducing the second harmonic impedance mismatch at the carrier amplifier.

To correct the second harmonic impedance mismatch of the carrier amplifier, a correction circuit is needed. The correction circuit should be independent of the fundamental load modulation and easy to utilize with other techniques required to improve the Doherty amplifier performance. With these constraints, the best location to place the correction circuit is on the offset line since the offset line functions only at the fundamental frequency. The second harmonic impedance correction circuit consists of an adjustable line between the two quarter-wave stubs at the fundamental frequency. The two quarter-wave lines form an open circuit at a connection point on the offset line, and the fundamental impedance is not affected by the correction circuit. But the second harmonic impedance can be controlled as shown in Fig. 3.30. Using this second harmonic control circuit, the Doherty amplifier based on the saturated amplifier can be realized.

3.5.1 Derivation of Drain Bias Control Voltage and Output Power

The optimum load lines of an amplifier, which is biased at class B with different drain biases, are shown in Fig. 3.32. When the peak output power P₁ is decreased to P₂, the optimum drain bias voltage needs to be reduced from V_ds,1 to V_ds,2, and the knee voltage is moved from V_k1 to V_k2. Therefore, the ratio of P_1,linear and P_2,linear can be derived as

$\frac{p_{2,\text{linear}}}{p_{1,\text{linear}}}=\frac{V_{\mathit{ds},2}-V_{k2}}{V_{\mathit{ds},1}-V_{k1}}\cdot \frac{I_{\max ,2}}{I_{\max ,1}}$

Because the load impedance is fixed, the ratios of the current and voltage swings are the same for the two power levels and are given by

$\frac{V_{\mathit{ds},2}-V_{k2}}{V_{\mathit{ds},1}-V_{k1}}=\frac{I_{\max ,2}}{I_{\max ,1}}=\sqrt{\frac{p_{2,\text{linear}}}{p_{1,\text{linear}}}}$

The knee voltages V_k1 and V_k2 can be described as

$V_{k1}=R_{\mathit{on}}\cdot I_{\max ,1}\text{and}{V}_{k2}=R_{\mathrm{on}}\cdot I_{\max ,2}$

and the ratio of V_k1 and V_k2 can be expressed as

$\frac{V_{k2}}{V_{k1}}=\frac{I_{\max ,2}}{I_{\max ,1}}=\sqrt{\frac{p_{2,\text{linear}}}{p_{1,\text{linear}}}}$

By substituting Eq. (3.35) into Eq. (3.33), the optimum drain bias voltage V_ds,2 can be derived as

$V_{\mathit{ds},2}=V_{\mathit{ds},1}\cdot \sqrt{\frac{p_{2,\text{linear}}}{p_{1,\text{linear}}}}$

As a result, the drain bias voltages for the carrier and peaking amplifiers should be reduced in proportion to the square root of the peak output power ratio.

3.5.2 Derivation for Gate Bias Control Voltage

As the peak output power is decreased from P₁ to P₂, the input power should be reduced linearly. Therefore, the peaking amplifier should be turned on at a 6 dB back-off level from the lower input power. To be turned on in the optimum back-off level, the gate bias voltage of the peaking amplifier needs to be increased linearly also. The input power levels, when the peaking amplifier is turned on, can be derived as

$P_{1,\text{in}}=P_1-6-G_1\left(\mathrm{dBm}\right)\text{for}{P}_1\text{output}$

$P_{2,\text{in}}=P_2-6-G_2\left(\mathrm{dBm}\right)\text{for}{P}_2\text{output}$

where G₁ and G₂ are gains for P₁ and P₂ power operations, respectively. However, the lower drain bias operation leads to a lower gain, and the turn-on voltage of the peaking amplifier should be adjusted following Eq. (3.38).

In Fig. 3.33A, the extracted input capacitance, C_in, is shown as a function of the drain bias voltage. As the drain bias voltage is decreased, the input capacitance is increased, and the gain of the carrier amplifier is decreased as shown in Fig. 3.33B. Therefore, the gate voltage of the peaking amplifier should be reduced accordingly. The two mechanisms compensate the variation of the gate bias voltage. As a result, the optimum gate bias voltage of the peaking amplifier is almost the same for the reconfigured Doherty amplifier for the APT operation.

3.5.3 Simulation Result of Reconfigured Doherty Amplifier for APT Operation

To verify the analysis for the bias voltage adaptations of the reconfigured Doherty amplifier, a Doherty amplifier is designed at 1.94 GHz using a Cree GaN HEMT CGH40045 model. The output matching circuits are optimized for efficiency at the drain bias voltage of 30 V. The harmonics are matched to the optimum impedances for an efficient saturated operation as described in the previous section. The simulation is conducted for the peak output powers with 3 dB step. As the peak output power is decreased to 47 and 44 dBm from 50 dBm, the drain bias voltage is reduced to 21.2 and 15 V, respectively. The gate bias voltage of the peaking amplifier is almost the same, slightly increased from − 6 to − 5.5 V for 47 dBm and − 5.3 V for 44 dBm. The simulation results of the reconfigured Doherty amplifier are shown in Fig. 3.34. When the drain bias voltage is 30 V, the efficiencies are around 70% at the peak power (49.5 dBm) and 6 dB back-off level. As the drain bias voltage is reduced to 21.2 V and 15 V, the efficiencies are around 70% and 72%, respectively at the two power levels.

3.5.4 Implementation and Experimental Results

To validate the simulated results of the reconfigured Doherty amplifier for the APT operation, the amplifier is implemented. The Wilkinson power divider is designed for an even power split. The carrier amplifier is set to a deep class AB bias with an idle current of 180 mA. The experiment is conducted with the peak output powers of 50, 47, and 44 dBm, decreased in 3 dB step, and the bias conditions are the same with the simulated ones. The measured results for a CW signal are shown in Fig. 3.35. As the peak output powers are decreased with the 3 dB step, the drain bias voltages are reduced from 30 to 21.2 and 15 V, respectively. The gate bias voltage is remained almost the same, changing from − 6 to − 5.3 V as the drain bias voltage is decreased. As the result, the efficiency and gain characteristics of the reconfigured Doherty amplifier are moved by the 3 dB step as shown in the figure. The Doherty amplifier is tested using a 10 MHz LTE signal with a 6.5 dB PAPR at 1.94 GHz with a 6.5 dB PAPR. As shown in Fig. 3.36, the measured drain efficiencies and gains are 53.2%, 12.8 dB at 42.9 dBm; 54.3%, 11.2 dB at 39.9 dBm; and 53.4%, 9.1 dB at 37 dBm, respectively.