Endnotes

1. Blood, William R., Jr. Motorola MECL System Design Handbook, Motorola, 1988, p. 2.

2. Dasher, David J. "Measuring Parasitic Capacitance and Inductance Using TDR." Hewlett-Packard Journal, Apr–1996, p. 8.

3. Kielkowski, Ron. Inside SPICE. McGraw-Hill, Inc., 1994, p. 67.

4. Johnson, Howard, and Martin Graham. High-Speed Digital Design. Prentice Hall PTR, 1993, p. 2.

5. Diepebrock, Jay, Greg Edlund, Roland Frech, and Christian Schuster. "Novel Time Domain Scaling Technique for Crosstalk Characterization." DesignCon, 2005, p. 8.

6. Tehrani, Peivand F., Yuzhe Chen, and Jiayuan Fang. "Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS." Electronic Components and Technology Conference, 1996.

7. Unger, Bernhard. "Simultaneous Switching Noise (SSN) Modeling." IBIS Open Forum, Jan–2000, p. 6; http://www.vhdl.org/pub/ibis/summits/jan00/.

8. Mirmak, Michael. "IBIS Modeling Cookbook for IBIS Version 4.0." IBIS Open Forum, Sep–2005; http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf.

9. LaBonte, Mike. "IBIS Quality Task Group." IBIS Open Forum; http://www.vhdl.org/pub/ibis/quality_wip/.

10. Taflove, A., and S. Hagness. Computational Electrodynamics: The Finite Difference Time Domain Method. Artech House, 2000.

11. Ward, David W., and Keith A. Nelson. "Finite Difference Time Domain (FDTD) Simulations of Electromagnetic Wave Propagation Using a Spreadsheet." Massachusetts Institute of Technology, 2004; http://nelson.mit.edu/.

12. Yee, K, "Numerical Solution of Initial Boundary Value Problems Involving Maxwell's Equations in Isotropic Media." IEEE Transactions on Antennas and Propagation, 1966, p. 302.

13. Granberg, Tom. Digital Techniques for High-Speed Design. Prentice Hall PTR, 2004, p. 353.

14. DDR2 SDRAM Specification. JEDEC Solid State Technology Association, 2006.

15. Morgan, Chad. "An Accurate Technique for Measuring Broadband, Causal Electrical Properties of Dielectrics." IEEE MTT-S International Microwave Symposium, 2007, p. 9.

16. Edlund, Greg. "Packaging a Supercomputer in a PCI Express Form Factor." DesignCon, 2007.

17. Coleman, David, Scott Gardiner, Mohammad Kolbehdari, and Stephen Peters. PCI Express Electrical Interconnect Design. Intel Press, 2004, p. 10.

18. Li, Mike, and Andy Martwick. "PCI Express Jitter Modeling." PCI-SIG, 2004, p. 17.

19. Coleman, David, Scott Gardiner, Mohammad Kolbehdari, and Stephen Peters. PCI Express Electrical Interconnect Design. Intel Press, 2004, pp. 119,195.

20. Li, Mike, and Andy Martwick. "PCI Express Jitter Modeling." PCI-SIG, 2004, p. 15.

21. Katopis, George, et al. "MCM Technology and Design for the S/390 G5 System." IBM Journal of Research and Development, 1999, p. 621.

22. Hackenberg, John H. "Signal Integrity in the VAX 8600 System." Digital Technical Journal, 1985, p. 61.

23. Loyer, Jeff, Richard Kunze, and Xiaoning Ye. "Fiber Weave Effect: Practical impact Analysis and Mitigation Strategies" DesignCon, 2007.

24. Fraser, Arthur, and Straty Argyrakis. "Does Signal Integrity Engineering Have a Future?" DesignCon, 2003.

25. Nagel, Lawrence W. SPICE2: A Computer Program to Simulate Semiconductor Circuits. University of California, Berkeley, 1975.

26. Kielkowski, Ron. Inside SPICE. McGraw-Hill, Inc., 1994, p. 23.

27. http://www.mosis.org/Technical/Testdata/menu-testdata_mep.html.