Contents

Preface

Acknowledgments

About the Author

About the Cover

1 Engineering Reliable Digital Interfaces

A Sadly Familiar Tale

Power On

The Long Reach of Legacy Design

Reflections on a Near Disaster

Motivations to Develop a Simulation Strategy

The Boundaries of Simulation Space

2 Chip-to-Chip Timing

Root Cause

CMOS Latch

Timing Failures

Setup and Hold Constraints

Common-Clock On-Chip Timing

Setup and Hold SPICE Simulations

Timing Budget

Common-Clock IO Timing

Common-Clock IO Timing Using a Standard Load

Limits of the Common-Clock Architecture

3 Inside IO Circuits

CMOS Receiver

CMOS Differential Receiver

Pin Capacitance

Receiver Current-Voltage Characteristics

CMOS Push-Pull Driver

Output Impedance

Output Rise and Fall Times

CMOS Current Mode Driver

Behavioral Modeling of IO Circuits

Behavioral Model for CMOS Push-Pull Driver

Behavioral Modeling Assumptions

Tour of an IBIS Model

IBIS Header

IBIS Pin Table

IBIS Receiver Model

IBIS Driver Model

Behavioral Modeling Assumptions (Reprise)

Comparison of SPICE and IBIS Models

Accuracy and Quality of IO Circuit Models

4 Modeling 3D Discontinuities

Beyond Transmission Lines

Finite Difference Time Domain Method

Solo Flight in a 3D Field Solver

Coaxial Transmission Line

Boundary Conditions

Waveguide Ports

Stimulus Function

Mesh Density

Running the Solver

Port Signals

S-Parameters

Energy

Field Visualization

Coaxial Discontinuity

Formation of Reflection

S-Parameters and Their Explanation

5 Practical 3D Examples

Coupled Differential Vias

Mechanical Drawings

Ports

Mesh Density

Sanity Check

Documentation

Pre-Flight Checklist

Land Grid Array Connector

Mechanical Trade-Offs

Electrical Characterization

3D Modeling Decisions

Test Card Design

Model-to-Hardware Correlation

6 DDR2 Case Study

Evolution from a Common Ancestor

DDR2 Signaling

Write Timing

Read Timing

Get to Know Your IO

Off-Chip Driver

On-Die Termination

Rising and Falling Waveforms

Interconnect Sensitivity Analysis

Conductor and Dielectric Losses

Impedance Tolerance

Pin-to-Pin Capacitance Variation

Length Variation Within a Byte Lane

DIMM Connector Crosstalk

Vref AC Noise and Resistor Tolerance

Slope Derating Factor

Final Read and Write Timing Budgets

Sources of Conservatism

Assumptions

7 PCI Express Case Study

High-Speed Serial Interfaces

Sensitivity Analysis

Ideal Driver and Lossy Transmission Line

Differential Driver with De-Emphasis

Card Impedance Tolerance

3D Discontinuities

Channel Step Response

Crosstalk Pathology

Crosstalk-Induced Jitter

Channel Characteristics

Sensitivity Analysis Results

Model-to-Hardware Correlation

Reflections

A. A Short CMOS and SPICE Primer

MOSFETs

Two Basic CMOS Circuits

SPICE

Sample SPICE Input Deck

SPICE Transistor Models

SPICE Subcircuits

B. A Stroll Through 3D Fields

Four Poetic Equations

Charges at Rest

Steady-State Currents

The Non-Intuitive Force

Enter Time

Waves

Dropping a Few Dimensions

Endnotes

Index