8.1.1 Introduction to copper-based interconnect technology

There is perhaps some irony in the fact that ‘interconnects’, consisting of the metallization and surrounding dielectrics that route all electrical signals within advanced microchips, are most appreciated when they do essentially nothing (at least to the naked eye). An interconnects primary function is to connect an electrical output to another electrical input, all at chip level, and vice versa, and as long as such interconnects transmit electrical signals without loss of fidelity and with minimal latency or supply electrical bias without detrimental power loss, then microelectronics devices should only be functionally limited by the behavior of the transistors that make up the bulk of the active circuitry within a given microchip. More realistically, however, functionally passive metallization does not behave so passively at the atomic scale, and its consequences can be significant. Metal atoms within interconnects jostle about under the action of external forces and, if long enough times are sampled, the nanoscopic movements of these atoms can be microscopic enough to lead to macroscopic device failure. The movement of metal ions under the influence of some driving force has several manifestations that lead to interconnect failure. Such failure mechanisms include stress-migration (metal void-generated electrical contact failures under thermomechanical stress), metallic corrosion shorting (interaction of metals with corrosive ambient and residual electrical bias present during processing), and metallic bridging under electrical stress owing to metal ionic drift into the adjacent interconnect dielectric (leading to dielectric breakdown between adjacent metals during electrical stress).

Electromigration (EM), that is metal void-generated contact failures under applied electrical current, is probably the most well-known interconnect failure mechanism and has been both an important topic in reliability physics and a key reliability metric for robust process technology development since the mid-1960s (Blech and Sello, 1966; d’Heurle and Ho, 1978; Ho and Kwok, 1989; Kwok, 1993; Hu et al., 1995; Clement, 2001). During EM, the application of current through a metal creates the so-called ‘electron wind’ and causes metal ions to hop in aggregate from lattice site to lattice site along the direction of electron flow from the cathode end (the electron source side) to anode end. The continued flow of these metal ions from a given site can eventually trigger void nucleation and subsequent void growth. The void growth can then lead to interconnect failure by open circuit. This classical representation of EM is necessary to understand EM for advanced interconnect applications; however, a more nuanced picture of EM will be needed to understand the potential reliability trends for advanced Cu interconnects beyond 32 nm node.

During the earlier era of microelectronics, spanning from the mid-1960s to 1997, Al-based metallization was the primary metallization used to form the interconnections between transistor elements within a microelectronic device such as a microprocessor. Starting around 1997, Cu-based metallization was introduced to enable the necessary performance scaling (Edelstein et al., 1997). Because Cu metallization became the new manufacturing process for advanced interconnects, much refinement in the basic Cu integration process has been done to improve on interconnect defectivity and uniformity so that technology scaling can continue at least up to the year 2015 (ITRS, 2009) before new solutions must be developed to keep pace with scaling requirements. Furthermore, tweaks to the basic Cu process and integration approach have been developed to improve either interconnect performance and/or reliability. These improvements have a direct bearing on EM performance and, in this chapter, we attempt to assess how EM performance might be expected to trend for the remainder of this decade.

8.1.2 The canonical copper interconnect and technology scaling

The canonical or standard picture of a Cu interconnect used in advanced CMOS-based technology appears little changed from its first use around 1997 (Edelstein et al., 1997; Li et al., 2004) and is depicted in Fig. 8.1. Interconnects are fabricated using a so-called ‘damascene’ approach, where a blanket film dielectric on a Si wafer is patterned and etched to form open spaces (trench and via openings). Via openings, for connection to the metal level immediately below, are made either before or after a trench pattern is created. Cu metallization is deposited within the trench and via features using electrochemical deposition (ECD). Before such Cu deposition, however, a metal diffusion barrier, typically Ta-based, and Cu seed layer must be deposited, using physical vapor deposition, to enable conformal growth of Cu metallization during an ECD plating process. Good quality metal diffusion barrier is needed to keep any Cu from ‘out-diffusing’ into the low-k dielectric (Michael et al., 2003a, 2003b; Augur et al., 2003; Lu et al., 2005; Pyun et al., 2005) and potentially allowing the dielectric to be shorted out under electrical bias, since Cu is known to be a ready diffuser into such dielectrics under electrical bias (Tsu et al., 2000), if pin hole defects exist within the metal barrier. After out-diffusion, the Cu then subsequently oxidizes within the inter-metal dielectric (Michael et al., 2003a, 2003b). The Cu plating creates a blanket film overburden above the trench feature that needs to be removed by chemical mechanical polishing (CMP) to eventually form the metal interconnect. CMP flattens or ‘planarizes’ the trench top surface for subsequent capping by a dielectric diffusion barrier. The Cu microstructure is usually improved and stabilized somewhat (increased grain size and stabilized Cu grain texture) by use of a thermal anneal treatment (Hu et al., 2007b) with overburden present or maybe after overburden removal by CMP, depending on the integration approach used.

Overburden anneal is usually preferred, however, because it minimizes the potential for void generation within the interconnect or hillock formation on the trench surface during anneal. The overburden presence also allows microstructure evolution during anneal from the overburden to penetrate into the trench feature and improve the resulting trench microstructure (Harper et al., 1999; Lingk and Gross, 1998; van den Boom et al., 2007), at least for interconnects greater than 250 nm in width. Following CMP, a dielectric film, typically a form of SiC_xN_y in presently available 90, 65, and maybe 45 nm technology nodes, covers or ‘caps’ the remaining free Cu surface so that Cu is fully confined within its trench by diffusion barriers. The dielectric cap layer can also function as an etch stop during via etch when a metal layer above must be connected to a metal layer below.

A procedure whereby such via are formed in conjunction with trench formation above is known as a ‘dual-damascene’ integration scheme where metal barrier/Cu-seed/Cu-plating steps are subsequently carried out into both via and trench concurrently. Typically, the first Back-end-of-Line (BeoL) metal layer, generally called ‘M1’, is made using a ‘single damascene’ integration scheme for connection to a lower tungsten (W) contact plug and eventual connection to transistors or Si substrate. At M2, a dual damascene process is used to connect to the M1 interconnect. This dual-damascene process is then repeated level-by-level until the complete metallization stack is generated. Generally, the interconnect feature size (width and often length) at lower or intermediate metal level is at or near the minimum allowable critical dimensions at a given technology node. The interconnect dimensions at the upper metal level tend to be larger, especially at the highest metal levels, where power and signal routing are used and finally where bond pad connections for access to device package wiring or solder bumping are needed. Thus, the interconnect layout tends to be ‘hierarchical’ in the sense that lower level interconnect dimensions tend to be smaller than those found toward the top levels; however, such dimensional transitions and the extent of such hierarchy are entirely dependent upon product type, cost, performance, and potential reliability issues that are not specifically related to EM.

8.1.3 Issues and evolution of the canonical copper interconnect

The ‘canonical Cu interconnect’ model above has not, however, stayed constant with time because its evolution is needed to keep pace with pressing technology needs. Manufacturing feasibility at a given point in time is an important consideration because the ITRS roadmap has required several adjustments to the rate of implementation of low-k dielectrics because of difficulties encountered incorporating them into a high yielding manufacturing process (Shaviv, 2008; Gambino, 2008; Lu, 2009). Although the overall integration scheme is pretty much the same, a number of improvements have occurred since Cu was first introduced. The intra- and inter-metal effective dielectric constant has decreased owing to new materials substitutions such as SiC_xO_yH_z (carbon-doped oxide; k ~ 2.9) for fluorinated silica glass (FSG; k ~ 3.5), which replaced tetraethyl orthosilicate (TEOS; k ~ 4.0) and capping dielectric SiC_xN_y (k ≤ 6) for SiN_x (k > 6). Etch and CMP processes have evolved for better overall uniformity across a Si wafer and for addressing differences in metal density and feature size. The dielectric cap process has been gradually improved through utilization of surface pre-treatments and time-window management before capping dielectric deposition for better adhesion/mechanical strength, EM performance, and corrosion prevention. The barrier metal has been gradually thinned in each generation to reduce the overall interconnect resistivity. Additional changes for more advanced technologies are also pending. Somewhere before the 15 nm node, ultra low-k porous interconnect dielectrics (k ≤ 2.5), EM mitigation process enhancements (such as metal capping, alloying, and/or interface treatment), and possibly atomic layer deposition (ALD) barriers will be implemented, provided that they are proven to be suitable for large-scale manufacturing (van Roosmalen, 2006). Beyond 15 nm, the inherent difficulty in mitigating the progressively worsened resistivity of Cu metallization while simultaneously placing increased demands on the process margin and performance poses a formidable challenge. Table 8.1 shows how the maximum current density, resistivity, and metal barrier thickness might be expected to scale down to the 7 nm node. Whereas other trends found in the ITRS roadmap are also very important, these three items are of particular interest to EM reliability, although, for brevity, the matter of barrier thickness scaling is only touched upon in this chapter (Traving et al., 2004).

A significant increase in resistivity from both grain boundary and interface electron scattering has been well-characterized by multiple authors (Besling et al., 2004; Gignac et al., 2007; Im et al., 2005; Kim et al., 2003; Rossnagel and Kuan, 2004; Shimada et al., 2006; Steinhögl et al., 2002, 2004, 2005; Sun et al., 2009; Tay et al., 2005; Wada et al., 2009; Yarimbiyik et al., 2006; Zhang et al., 2004a, 2004b) to the point that their respective interconnect delay contributions are well-predicted in the ITRS roadmap for the rest of this decade. In Fig. 8.2, Cu interconnect resistivity as a function of the technology node is shown along with data from some representative authors. The resistivity contributions are modeled using the formalism developed by Steinhögl et al. (2002, 2004, 2005), and the primary drivers for interconnect resistivity increase are shown to come from grain boundary (Mayadas and Shatzkes, 1970) and surface (interface) scattering (Fuchs, 1938; Sondheimer, 1952). The form provided by Steinhögl et al. (2002, 2004, 2005) is as follows:

[8.1]

where , w is the width, AR the aspect ratio (height over width), ρ₀ the bulk material resistivity, λ the mean free path, d_gb the average distance between grain boundaries, p the specularity parameter at the metal surface, and R the grain boundary reflectivity coefficient. The parameter C is a constant and equals 1.2 for rectangular cross-sections. Equation [8.1] is an approximation to the exact solution of the transport problem in a conductor with surface scattering. The approximation accuracy compared with the exact integral relationship is estimated by Steinhögl et al. (2005) to be better than 3.5% for linewidths between 50 and 1000 nm. The first term in equation [8.1] corresponds with the grain boundary scattering contribution and the second with interface scattering. The values of the other parameters are taken directly from Im (2005) with the exception of the bulk resistivity, where ρ₀ = 1.85 μΩ cm at ~ 50 °C (348 K) is assumed: λ = 37.3 nm (300 K), p = 0.41, and R = 0.22. Similar plots are found in the studies previously noted, and data from those align well with those shown in Fig. 8.2. The parameters w and AR are necessary geometrical parameters that are determined by the ITRS roadmap, and the trending curve for effective resistivity in Fig. 8.2 is directly tied to ITRS predictions from 2007 and 2009. Using these parameters, the grain boundary contribution seems larger than that from interface scattering, but surface scattering is argued as being as least as important by others (Gignac, 2007; Graham et al., 2008) in Cu interconnect microstructures where the mean grain size exceeds the electron mean free path. It is likely that there will be improvements in process and integration to improve on the grain structure, size and interface smoothness, but such improvements will not be easily achieved. In fact, the evidence appears to indicate that microstructure development (Brandstetter et al., 2010) and interface quality because of line edge roughness (LER) (Noguchi, 2005) are less easily controlled or perhaps more complicated to address when the line width is decreased. An LER contribution that does not improve with scaling would significantly worsen the resistivity trend (Lopez et al., 2009). Thus, interconnect microstructure that becomes progressively more difficult to control as trench width narrows, adds further complexity to the expected Cu resistivity increase as interconnect critical dimensions scale downwards (ITRS, 2009) in width and thickness.

The result in Fig. 8.2 demonstrates the dramatic resistivity increase expected beyond the 32 nm node, although the accuracy of the prediction needs verification because the result is based on an integral approximation. The published data obtained so far for technologically relevant Cu interconnect does not yet extend down below 40 nm so that the worst of the projected resistivity increase has yet to be verified. Interestingly, resistivity trending for Al interconnect (from Lee et al., 2007) is also shown for reference, and it is clear that Al metallization remains an inferior option down to 50 nm and probably beyond. The reason is that present Al interconnect technology requires the use of TiN antireflective coating (ARC) and a high resistivity Ti/TiN redundant metal liner to mitigate Al susceptibility to stress-induced voids (Okabayashi, 1993; Walls, 1997) or EM (Gambino, 2008; Murphy et al., 2008), and it will be difficult to thin the liners with technology scaling (Rosenberg et al., 2000).

The contributions for grain boundary, interface scattering and the barrier metal are also shown in Fig. 8.2. The barrier contribution shows as a negative because it provides an additional current pathway, which reduces effective resistivity by a very minor amount. This barrier contribution analysis can be seen by treating the interconnect as stemming from two parallel pathways owing to the Cu metal and the metal barrier. The total resistance can be shown to have a form where the barrier metal contribution can be expanded out as (1 + x)^− 1 ≅ 1 − x + x², where x is a term consisting of metal barrier resistivity and cross-sectional area contributions. Note that the above analysis completely ignores vias, which necessarily have barrier metal at the bottom, so that it will have a serial, in addition to the already present parallel, contribution to the via resistance or effective via resistivity. This serial contribution is a seriously detrimental contributor to via resistance and can only be scaled downwards by thinning the barrier. This scaling impact of via resistance is presently not a well-addressed or well-documented problem. How via bottom barrier thickness is addressed will potentially have impact on the use of the Short Length Effect (Blech, 1976, 1997, 1998; Filippi et al., 1995; Wang and Filippi, 2001; Christiansen et al., 2008; Oates and Lin, 2008, 2009) for current density enhancement in short-length interconnects because the via bottom barrier serves both as the flux blocking barrier from one lower level interconnect to an upper level interconnect and as the thin membrane to support back-stress development in sufficiently short-length interconnects (Aubel et al., 2007).

According to Meindl et al. (2002), interconnect signal latency can be generically expressed as a product of three factors:

[8.2]

where τ is latency of a single isolated interconnect, ρε is the resistivity– permittivity factor, h is the metal height, t is the dielectric thickness, and l is the interconnect length. As technology scales, assuming the rather ideal situation that no additional chip functions are added with scaling, all the physical dimensions in the BeoL stack shrink proportionately so that the only simple way to decrease latency is to improve the properties of the materials used in interconnects; namely, by reducing either the metal resistivity ρ, or the effective dielectric permittivity ε. From the metallization perspective, Cu is as good a conductor as can be expected, for a presently available technology. Although improved metallization alternatives to Cu are being investigated (e.g., metal silicides, nano-Ag, carbon nanotubes, nano-graphene, phonon engineering, on-chip optical interconnects, and positive quantum confinement effects; ITRS, 2009), there is little clarity on which technology or technologies will be an appropriate future interconnect medium from a performance, reliability, and manufacturability standpoint; however, the increasing resistivity of Cu metallization as interconnect dimensions scale downwards means that such improvements are critical. Otherwise, the dimensional scaling benefit will be easily lost.

Unfortunately, no new and realistic materials solution presently exists to fully eliminate this upwards resistivity trend of Cu metallization. At this stage, the main effort is to improve on the effective dielectric constant by substituting materials with progressively lower dielectric constant k, where ε = kε₀ and ε₀ is the permittivity of free space. It is clear, however, that any materials improvement through the use of an ultra low-k dielectric (k ≤ 2.5) is limited by the presence of higher k etch stop layers (4.0 < k < 6) in the present BeoL stack. Significant process optimization effort is required to integrate new materials into a given integration scheme and, although the transition to much lower k materials is a priority for future scaling, such effort may come at the possible cost of decreasing the process margin. For BeoL technology at 22 nm and beyond, use of air-gap technology between the interconnect metal and the use of an ultra-thin metal barrier will be necessary to achieve the required performance improvements (Chen et al., 2008). For metal 1 and intermediate layers, the increased BeoL interconnect delay for a fixed length is likely to be very significant by the end of this decade, and, although capacitance is considered to be more important at these levels than resistance, this resistivity trending may not be easily countered by simple chip shrinkage (See Meindl’s equation [8.2]) as is presently done. Interconnect delay issues are also a major concern for global (across chip) interconnect wiring because their length does not scale as easily as lower level metal interconnects, but because their lateral dimensions remain large relative to the electron mean free path, they still benefit from the incorporation of ultra low-k solutions. Moreover, increased functionality for a given device with technology scaling (so-called system-on-chip or SOC integration) inevitably keeps the overall total wiring length from decreasing as fast from technology node to technology node. Generally, interconnect delay issues can be expected to progressively worsen with each generation and are not easily addressed by new materials substitution in the BeoL, although it might be expected that better process control over the Cu microstructure and interface quality will be forthcoming and that it will provide additional relief from resistivity scaling. By that time, three-dimensional (3D) integration (die stacking and chip-to-chip connection through the Si die) will probably be a stronger technology driving force. In a sense, these latest pre-15 nm Cu-based interconnect technology advances could spell the ‘last hey-day’ for advanced Cu-based interconnect technology development.

8.4.1 Microstructure development in damascene copper interconnects

The microstructure that develops in Cu damascene interconnects is greatly affected by a number of process-related factors, including etch profile and uniformity (Choi et al., 2010), barrier/seed deposition, ECD conditions such as the impact of impurity concentration (Neuner et al., 2010), anneal conditions (Barmak et al., 2003; Brandstetter et al., 2010; Carreau et al., 2007), defect generation (Detavernier et al., 2003), overburden thickness (Dubreuil et al., 2008; Field et al., 2003), and metallization stress or strain (Harper et al., 1999). The main factors affecting grain size within a damascene trench, however, are the interconnect dimensions (Besser et al., 2001; Brandstetter et al., 2010; Cho et al., 2005; Lingk et al., 1999; Vanasupa et al., 1999b; Wu et al., 2004). The as-plated grain size is small, somewhere on the order of 50 to 100 nm, and depends on the plating conditions used. Generally, the most characteristic film texture for as-deposited and annealed Cu films is (111)-oriented with contributions from other secondary grain orientations such as (200) and (311) (Cho et al., 2005; Lee et al., 2003; Neuner et al., 2003; Rosenberg et al., 2000; Vanasupa et al., 1999a). The microtexture found in Cu interconnects has a much less preferred orientation (Ji et al., 2004) than that in Al metallization found in microelectronics (Rosenberg et al., 2000). In Cu lines, (111) oriented grains from the trench bottom and sidewalls are found (Besser et al., 2001; Cho et al., 2005; Ganesh et al., 2010). A (111) oriented fiber texture is considered advantageous for grain boundary EM for Al(Cu) metallization (Knorr and Rodbell, 1996; Knorr et al., 1991) and has been confirmed for Cu metallization (Abe et al., 2004; Ryu et al., 1999); however, developing the preferred (111) orientation trenches within ultranarrow trenches is difficult to achieve because side-wall grain growth is prevalent (Leaming-Sphabmixay et al., 2007). For wider interconnects (>~0.5 μm), the grains tend to be polygranular so that smaller grains bunched together can span a given line width. The presence of the overburden has a stronger effect on the microstructure development within wider trenches so that grains can extend from the trench bottom to the overburden surface. The grain boundaries in such instances tend to be more or less vertical, but if several grains are needed to span the interconnect width, a clear longitudinal grain boundary EM pathway would exist for extended lengths over large sections along the interconnect.

When the interconnect line width is reduced, the overburden is found to have limited relation to microtexture development within the trench (Besser et al., 2001; Brandstetter et al., 2010) below 250 nm and virtually no effect at 80 nm or less, although its effect may be more pronounced when the overburden is purposely reduced (Dubreuil et al., 2008). For a narrow interconnect, sidewall growth is thought to increasingly lead to greater complexity in the microstructure (Besser et al., 2001); however, it has recently been argued that a superconformal filling process (Andricacos et al., 1998; Josell et al., 2001) may limit such sidewall orientation contribution for interconnects with widths at least down to 140 nm, especially after thermal anneal treatment. Furthermore, it is argued that stress profiles along the length and depth of the trench during anneal have a greater impact on the final texture than sidewall growth (Cho et al., 2005). As for grain size, it scales roughly with the interconnect width so that, for the narrowest interconnects (80 nm and below), the grains can be longer than wide (Graham et al., 2008); however, it is also found that the interconnect grains show regions of bamboo and polygranular character with smaller grains found deeper in the trench than higher in the trench (Hu et al., 2007b). Interestingly, electrochemical deposition (ECD) actually yields a larger grain size than other deposition methods such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) (Ryu et al., 1999). Twinning is evident in Cu grains regardless of the line width, although the grain size increases and twinning density decreases after thermal anneal treatments (Cho et al., 2005; Hübner et al., 2010). Grain boundaries defined by twins generally have low energy so that they are very unlikely to be effective pathways for EM mass transport (Chen et al., 2008b).

Brandstetter et al. (2010) has shown that high temperature annealing (400 °C for 6 h) has a pronounced effect (16-fold increase with overburden) on grain size only for the larger width interconnects, and a lower temperature anneal (150 °C for 6 h) has somewhat less effect (10-fold). Below 250 nm, the annealing impact on grain size is less significant even for 400 °C annealing (70 nm increased to 100 nm at 80 nm line width). The resulting changes to the microstructure appear to reduce the overall strain present within the Cu grains (Lingk and Gross, 1998; Harper et al., 1999; Moriyama et al., 2003; Lee et al., 2003; Ito et al., 2007); however, the overburden-driven strain energy minimization process of grain growth is stunted by the presence of the interconnect side walls (Wu et al., 2004). When considering such general trends, however, one should be aware that the microstructure found in actual production environments depends upon the explicit process flow used and is not necessarily optimized for grain size or microtexture uniformity.

8.4.2 Microstructure impact on copper EM

When EM is rate-limited by interface mass transport, as is the case for canonical damascene Cu, little evidence of microstructure impact on EM will be apparent (Arnaud et al., 1999; Hu et al., 1999a; Hau-Riege and Thompson, 2001). Hau-Riege and Thompson ran an interesting experiment where direct alteration of the microstructure using a scanned laser annealing method yielded little difference in EM performance in 500 nm wide interconnects. It should be noted that these results pertain to intermediate width interconnects, where the overburden grain growth can extend deeper into the trench. In such intermediate width interconnects, the grain microstructure is found to exhibit bamboo or near-bamboo character (Hu et al., 2007a; Brandstetter et al., 2010). Thus, changing the microstructure for such an interconnect could possibly mean a change from a smaller density of shorter length bamboo grains to a larger density of longer ones. Ryu et al. (1999) did find differences in EM performance in Cu CVD-deposited long test lines with larger dimensions (1.5 μm width and 0.5 μm thickness). It was found that the (111)-preferred orientation had a four-fold better EM performance than the (200) oriented test lines so that some microstructure effects are likely present. In this instance, the test lines would be expected to show polygranular character, especially since the deposition method is CVD and not ECD, so that a microstructure dependence seems reasonable. These CVD metal lines, however, were not passivated, and the effects observed may have been manifested by differences in surface diffusion along differently oriented grain surfaces (which is maybe a more subtle microstructure effect). In summary, the natural conclusions are the following: (a) for wider polygranular interconnects (more than 1 μm), one would expect to have significant contributions from both interfacial and grain boundary EM; (b) for intermediate width interconnects (say, 200 to 3000 nm width), Cu grain boundaries in ECD-deposited interconnects do not matter so much after annealing. Such microstructure is not as important because (i) they are not able to form fast percolative pathways throughout the interconnect length [perhaps because they are blocked by individual bamboo grains or maybe width spanning twinned grains (Hübner et al., 2010)] or (ii) the interface pathway is much faster than any grain boundary pathway even when a percolative path exists. Regardless, any means of increasing the interface pathway resistance to EM increases the influence of the grain boundaries on EM performance as Hau-Riege and Thompson astutely noted in 2001 before the described methods of capping interface improvement were introduced. Similar conclusions have been formed by Ogurtani and Oren (2001) using a more theoretical analysis.

For much narrower interconnects, the grain size may have a clearer role because they probably define the vertical component of the critical void volume, equation [8.5] for EM failure (Arnaud et al., 2010; Li et al., 2004; Oates and Lee, 2006). Thus, the presence of small grains within and under vias may set the conditions for EM early failures. Furthermore, polygranularity in narrow interconnects probably enhances the role of grain boundary diffusion during EM (Hu et al., 2007a, 2010). Then, when interface engineering to arrest interface EM is implemented, the role of grain boundary formation in void nucleation and growth is enhanced (as is evident from Fig. 8.11). Recent observations confirm that EM in CoWP-capped interfaces does not provide as large an EM margin as expected if extended grain boundary paths exist (Hu et al., 2010; Zhang et al., 2010a, 2010b). Hence, microstructure control, and not just interface engineering, is absolutely vital to retain an EM margin in well-capped interconnects below the 32 nm node (Lin et al., 2010).

If grain boundary EM does become a more critical factor, then presumably much of the learning from grain boundary EM in Al should find relevance. Suo et al. (1994) have shown that circular voids will preferentially follow an instability located on a hemispherical void during EM stress so that the instability is extended in opposition to the healing forces owing to surface energy (void surface tension). In contrast to maybe an interface dominant situation but under the same types of EM and surface tension effects, the voids would be expected to extend along the current flow direction (Choy and Kavanagh, 2004). In this context, a grain boundary that connects to an interface is a natural generator of local instability, should a hemispherical void pass through it (Zaporozhets et al., 2005), and such void growth and void translation physics appears to be similar to what is observed by in situ SEM studies (Meyer and Zschech, 2007). Stress modeling of the microstructure effect on void nucleation indicates that small grains at an interface may be susceptible to fracture and are candidates for void nucleation events (Kteyan et al., 2007). Hau-Riege et al. (2004) showed that the critical stress for void nucleation decreases as the Young’s modulus of the surrounding dielectric decreases and has implications for scaling with the need to incorporate ultra-low-k dielectrics or air gap technology and reduced metal barrier thickness. Because grain boundary triple points remain at the capping interface, voids probably nucleate there (Vairagar et al., 2004b), especially at non- Σ3ⁿ boundaries that intersect an interface wall (Arnaud et al., 2006; Cayron, 2007). Grain boundary triple points within the metal may also become important sites for void nucleation too. When a grain boundary EM pathway begins to dominate (at least locally around the grain boundary), voids can grow along the grain boundary and generate width spanning slit voids (Sukharev et al., 2009). Ogurtani and Oren (2004) developed a detailed model of void dynamics occurring in bamboo-type interconnects and identified a time-to-failure equation based on the average number of bamboo grains that need to be passed before a given fatal void reaches the cathode end.

Not all grain boundaries provide sufficiently fast EM pathways and, at present, detailed analysis has not been done to identify those grain boundaries that are most susceptible to forming trans-width slit voids. From Al-based EM (Hu et al., 1995), it is expected that (111) tilt grain boundaries with low misorientation angles (< 11° to 15°) are poor pathways for EM voiding. High-angle misorientation boundaries probably provide faster diffusivity paths with the exception of certain special boundaries known as ‘coincident site lattices’ (CSL). Because Cu is also an FCC metal, similar arguments would be expected to apply; however, for Cu damascene interconnects, the Cu lines do not show as strong (111) fiber texture so that a higher density of grain boundary pathways should be active. Thus, more detailed analysis will be needed.

More pragmatically, if horizontal or vertical slit voids only form well beyond the expected life for microelectronics devices under regular use conditions, then the detailed microstructure EM physics is only a minor concern to those more interested in simply meeting the performance demands of the ITRS roadmap. The question remains whether such a reliability margin can be met by the billions of interconnects undergoing some degree of EM amount in a customer environment. To address those concerns, more detailed statistical analysis to identify the extent of EM early failures is necessary. Such discussion, however, is beyond the scope of this chapter, but suitable references are provided because it is an important topic (Gall et al., 1997; Hauschildt et al., 2007, 2008; Lee and Ho, 2004; Li et al., 2006; Oates and Lee, 2006; Ogawa et al., 2001; Tsuchiya and Yokogawa, 2006). Layout effects on EM are also an important consideration and are also listed for reference (Girault et al., 2008; Hau-Riege and Klein, 2008; Hau-Riege and Thompson, 2000; Kakuhara et al., 2009; Park et al., 2010; Roy et al., 2009).

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