Index
A
Abstraction, system design,
123–125
Adder floating point adder example,
169
Verilog examples
VHDL examples
Address space
Linux kernel addition in partitioning,
236–238
platform field-programmable gate array,
144
Advanced configuration environment (ACE) file, Xilinx,
39–40
Advanced encryption standard (AES), profiling,
230–231
Advanced technology attachment (ATA) bus,
165
Affected state, partitioning,
218–219
Asynchronous design, Kahn Process Network,
298
B
Bandwidth
balancing
Kahn Process Network
data-flow firing rule,
296
memory techniques
direct memory access
off-chip memory access
on-chip memory access
block random access memory,
326
FIFO configuration options,
325
Native Port Interface
microprocessor peripheral description file,
342
Xilinx project modifications,
342–343
scalability
constraints
solutions
Base system builder (BSB) wizard
Xilinx Platform Studio launching,
29–35
Xilinx Platform Studio project files,
167
Behavioral circuit,
59,
69
Bitstream
configuration bitstream
transition from hardware description language,
74
Black box description (BBD) file,
175
Block random access memory (BRAM)
on-chip memory access,
326
platform field-programmable gate array
architecture design tools,
164
Board support package (BLP),
159
Bridge, platform field-programmable gate array,
140
Bus
platform field-programmable gate array,
138–139
platform field-programmable gate array architecture design tools,
163–164
Bus master
C
Capability, field-programmable gate array,
Capacity, field-programmable gate array,
Char device driver, Linux kernel addition in partitioning,
239–241
ChipScope
hardware core modification,
283–286
Clock regions, Xilinx Virtex 5,
86–87
Coarse-grain parallelism,
247
Cohesion, system design,
125
Commodity off-the-shelf (COTS) components,
251
Complementary metal oxide semiconductor (CMOS) transistor, functional overview,
44,
46–47
Complex programmable logic device (CPLD),
48–49
Computing system
general purpose computing system,
5–6
Configurable logic block (CLB)
Coprocessor model
Correctness
Costs
finance and consumer demand,
19–20
nonrecurring engineering costs,
18–19
spectrometer platform field-programmable gate array example,
26–27
Create/Import Peripheral (CIP) wizard
hardware core configuration,
170
name and version page,
102
slave interface page,
104
slave registers page,
105
Crosstool-NG, downloading and installing,
185–187
Custom compute core, assembly
design composition and approaches,
148–162
D
Data-flow firing rule, Kahn Process Network,
296
Data-flow graph, Kahn Process Network,
296
Debugging
spatial design
ChipScope
hardware core modification,
283–286
software addressable registers,
281–282
Degree of parallelism (DOP),
250
Design entry, definition,
21
costs
finance and consumer demand,
19–20
nonrecurring engineering costs,
18–19
life cycle of project,
10–12
success measures
Device control register (DCR) bus,
164
Diffused intellectual property,
222
Digital clock manager (DCM),
56,
87
Digital signal processing block (DSP)
Xilinx Virtex 5 slices,
84–85
Direct memory access (DMA)
Dual in-line memory module (DIMM),
144
Dynamic Host Configuration Protocol (DHCP),
361
E
Efficiency, custom compute cores,
147–148
Electronic Design Interchange Format (EDIF)
cell hierarchy description,
74
Embedded Development Kit (EDK)
platform field-programmable gate array architecture design
base system building,
166
Energy, performance metric,
15
Evolvability, design quality,
120
Execution models, embedded systems,
7–10
External criteria, design quality,
117
F
Fast simplex link (FSL) bus,
164
application overview,
1–2
function generators,
49–51
programmable logic device comparison,
21
special-purpose function blocks,
53–57
Fine-grain parallelism,
247
Finite difference time domain (FDTD), application simulation,
231–233
Finite state machine (FSM)
bus master logic
control finite state machine,
332
read request finite state machine,
332–333
write request finite state machine,
333–334
Native Port Interface
control finite state machine,
338–339
read request finite state machine,
339
write request finite state machine,
339–342
Formal description, module,
122–123
Function generator, field-programmable gate array,
49–51
G
Gate-level modeling circuit,
68
General purpose computing system,
5–6
GNU
Graphical processor unit (GPU),
252
H
configuration bitstream transition,
74
debugging of spatial design,
278–281
hardware core project directory,
105–110
Hardware, definition,
High-level language (HLL),
158
High-speed serial transceiver,
57,
85–86
Hypertext Markup Language (HTML),
358
Hypertext Transfer Protocol (HTTP),
358
I
IBM CoreConnect, platform field-programmable gate array architecture design
Implementation, module,
123
Implicit description, module,
121–122
Informal description, module,
121–122
Input/output block (IOB), field-programmable gate array,
53
Input/output buffer (IOB), Xilinx Virtex 5,
85
Instruction-level parallelism,
249
Integrated circuit (IC), field-programmable gate array comparison,
Integrated controller (ICON), ChipScope,
283–284
Integrated logic analyzer (ILA), ChipScope,
283–286
Integrated Software Environment (ISE)
commands
configuration bitstream generation,
93–94
Integration stage, design,
11–12
Intellectual property core,
22
Intellectual property interconnect (IPIC),
103–104,
106
Intellectual property interface (IPIF),
100,
103–104
Interface, system design,
121
Internal criteria, design quality,
117
Interoperability, design quality,
120
Iteration-level parallelism,
249
K
Kahn Process Network (KPN)
data-flow firing rule,
296
L
Law of Diminishing Returns,
207
Legal ordering, subtasks,
257
Link layer, networking,
351
Linux
advantages in development,
28
cross-compiling
hardware base system building,
189–190
kernel addition in partitioning
Local memory bus (LMB),
163
Logical link control (LLC),
352
Logic block, field-programmable gate array,
52–53
Logic cell
field-programmable gate array,
51–52
representation in partitioning,
208
Xilinx Virtex 5 slice,
82
Look-up table (LUT)
four-input function mapped to two, 3-LUTs,
76
function generator,
49–51
Loop-carried dependence,
264
Loop-independent dependence,
263
Low-voltage differential signaling (LVDS),
165
M
Maintainability, design quality,
119
Maintenance stage, design,
12
Media access controller (MAC),
351,
361
Memory
architecture design tools,
164
bandwidth techniques
direct memory access
off-chip memory access
off-chip memory controllers,
302–304
on-chip memory access
block random access memory,
326
FIFO configuration options,
325
scalability
Memory controller, platform field-programmable gate array,
137
Memory management unit (MMU),
136,
239
Memory transaction, platform field-programmable gate array,
137–138
Metal oxide semiconductor effect transistor (MOSFET)
complimentary metal oxide semiconductor effect transistor,
46–47
n-channel transistor,
44–45
Microprocessor hardware specification (MHS) file,
168
Microprocessor peripheral description file (MPD),
105–107,
175,
342
Microprocessor software specification (MSS) file,
168
Modular design approach,
140
Module
Multiple instruction stream, multiple data stream (MIMD),
251–252
Multiple instruction stream, single data stream (MISD),
251–252
Multithreaded model, partitioning,
216–217
N
Native Port Interface (NPI)
finite state machines
control finite state machine,
338–339
read request finite state machine,
339
write request finite state machine,
339–342
microprocessor peripheral description file,
342
Xilinx project modifications,
342–343
Netlist
Integrated Software Environment building,
91–92
Network File Systems Protocol (NFS),
359
Networking
high-speed communication
internetworking communication
Network File Systems Protocol,
359
Simple Network Management Protocol,
359
low-speed communication
hardware base system generation,
366–367
microprocessor hardware specification file,
367–368
microprocessor software specification file,
368–370
miscellaneous protocols,
348
user constraints file,
367
operating system configuration,
360–361
Network-on-chip model, partitioning,
217–218
Network Time Protocol (NTP),
359–360
Nonrecurring engineering costs,
18–19
O
Off-line,
On-chip peripheral bus (OPB),
163–164
Open Source Interface (OSI),
352
Operating system, configuration,
360–361
P
Parallelism
degree of parallelism,
250
identification
uniform dependence vectors,
262–254
spatial parallelism with platform field-programmable gate arrays
parallelism within designs,
271–272
Partial ordering, subtasks,
258
Partitioning
analytical approach
fraction of execution time,
210
communication
coprocessor model
error-correcting subroutine,
212
transfer of state
feature
Linux kernel addition
performance
profiling
practical issues
Performance metrics
Peripheral analysis order file (PAO),
108–109,
110
architecture design of platform field-programmable gate arrays,
165–166
examples of platform field-programmable gate arrays,
140–141
Physical layer, networking,
350–352
Place-and-route tool (PAR),
77,
93
Platform field-programmable gate array
hardware design
hardware versus software features,
7–8
historical perspective,
22
overview,
spectrometer example,
25–27
Portability, design quality,
120
Power
performance metric,
16–17
PowerPC 440 processor, Xilinx Virtex 5,
87–88,
163
Predictability, custom compute cores,
148
Primitives
Printed circuit board (PCB), design,
12
Processor
definition,
field-programmable gate array features,
56
platform field-programmable gate array
architecture design tools,
163
scalability
Program, definition,
Programmable logic array (PLA),
47
Programmable logic device (PLD)
historical perspective,
21,
47
Prototype, software reference design,
130
R
Refactoring, system design,
129
Regression testing, system design,
129
Regular network topology,
351
Relative cost of reuse (RCR),
128
Relative cost of writing for reuse (RCWR),
128
Reliability
Reparability, design quality,
119
Request for comment (RFC),
357
Requirements stage, design,
10
Resilience
Routing
Run-time,
S
Scalability, platform field-programmable gate arrays,
27
Secure Socket Layer (SSL),
360
Sensitivity list, VHDL,
67
Serial advanced technology attachment (SATA),
165
Serial Peripheral Interface (SPI),
348
Simple Network Management Protocol (SNMP),
359
Simulation, hardware description language,
58
Single instruction stream, multiple data stream (SIMD),
251
Single instruction stream, single data stream (SISD),
251
Single program multiple data (SPMD),
252
Size, performance metric,
17
Slice
Small computer system interconnect (SCSI),
176
Software
Software reference design,
130
Sparc Improved Boot Loader (SILO),
161
Spatial design
debugging
ChipScope
hardware core modification,
283–286
software addressable registers,
281–282
parallelism
degree of parallelism,
250
identification
uniform dependence vectors,
262–254
spatial parallelism with platform field-programmable gate arrays
parallelism within designs,
271–272
sequential versus parallel,
246–247
Very High-Speed Integrated Circuit Hardware Description Language for spatial design
Specifications, design,
11
Spectrometer, platform field-programmable gate array example,
25–27
Speed
performance metric,
13–15
Standalone C program,
154
State, system design,
125
Static random access memory (SRAM),
50–51,
77,
304
Static single assignment (SSA),
259
Storage element, field-programmable gate array,
51
Structural/data flow circuit,
59,
68
Subroutine, definition,
202
Switch box, logic blocks,
52
Synchronous design, Kahn Process Network,
298
Synchronous dynamic random access memory (SDRAM),
304–305
Synthesis, netlist file output,
74
System design
custom compute core assembly
design composition and approaches,
148–162
hardware design
additions to platform field-programmable gate array,
142–144
platform field-programmable gate array architecture design
base system
core generator
Create/Import Peripheral wizard for hardware core configuration,
170
cross-development tools and libraries,
184–187
embedding of GNU/Linux system
Unix filesystem organization,
178–180
floating point adder example,
169
hardware core
connection to base system,
176
testing
Xilinx Embedded Development Kit and IBM CoreConnect
Xilinx Platform Studio project files
microprocessor hardware specification,
168
microprocessor software specification,
168
software design
T
Thread-level parallelism (TLP),
249
Time-to-market, finance and consumer demand,
19–20
Total energy, performance metric,
15–16
Totally ordered subtasks,
257
Transceiver
high-speed serial transceiver,
57
Transmission Control Protocol/Internet Protocol (TCP/IP),
349–350,
352–353
Transportation layer, networking,
352
Trapped state, partitioning,
220–221
U
Universal Serial Bus (USB), advantages over RS-232,
346
Unix, filesystem organization,
178–180
User constraints file (UCF),
168–169
User Datagram Protocol (UDP),
352
V
Verifiability, design quality,
119
Verilog
adder circuit examples
finite state machine example,
71–73
synthesizable Verilog,
68–69
Very High-Speed Integrated Circuit Hardware Description Language (VHDL)
adder circuit examples
finite state machine example,
63–68
synthesizable VHDL,
58–59
Very High-Speed Integrated Circuit Hardware Description Language, spatial design
von-Neumann stored-program compute model,
W
World Wide Web (WWW),
358
X
Xilinx core generator ,
See CoreGen
Xilinx Microprocessor Debugger (XMD),
39
Xilinx ML-510
Xilinx Platform Studio (XPS)
Create/Import Peripheral wizard,
99–105
downloading hardware and software,
39–40
graphical user interface
project files
microprocessor hardware specification,
168
microprocessor software specification,
168
Software Design Kit,
36,
39
software platform windows,
36–38
Xilinx Synthesis Tool (XST),
88–91
Xilinx Virtex 5
block random access memory,
83–84
configurable logic block,
83
digital signal processing block slices,
84–85
PowerPC 440 processor,
87–88