Index

A

Abstraction, system design, 123–125
Adder floating point adder example, 169
Verilog examples
1-bit full adder, 69
2-bit full adder, 70–71
VHDL examples
1-bit full adder, 60–61
2-bit full adder, 61–63
Address space
Linux kernel addition in partitioning, 236–238
platform field-programmable gate array, 144
Advanced configuration environment (ACE) file, Xilinx, 39–40
Advanced encryption standard (AES), profiling, 230–231
Advanced technology attachment (ATA) bus, 165
Affected state, partitioning, 218–219
Amdahl’s law, 200
AND gate, 45, 47, 74
Asynchronous design, Kahn Process Network, 298
Aurora, 363–364

B

Bandwidth
balancing
Kahn Process Network
asynchronous design, 298
data-flow firing rule, 296
data-flow graph, 296
overview, 296–298
synchronous design, 298
pipeline balancing, 295
stall, 294
memory techniques
access, 305–309
block random access memory, 300, 302, 314
direct memory access
bus-based interface, 307–308
controller, 306–307, 328–330
direct connect interface, 308–309
memory bandwidth, 309–310
off-chip memory access
bus master, 330–332
controllers, 302–304
on-chip memory access
block random access memory, 326
FIFO configuration options, 325
FIFO memory types, 324–325
LocalLink interface, 326–328
overview, 299–302
practical issues, 314
programmable input/output, 305–306
streaming instrument data, 311–314
types of memory, 304–305
Native Port Interface
data transfer, 337
little endian, 336–337
logic, 337–342
microprocessor peripheral description file, 342
overview, 323, 334–335
signals, 335–336
Xilinx project modifications, 342–343
scalability
constraints
core, 315, 317–318
memory, 318–319
processor, 316
solutions
bus bandwidth limitations, 320–321
memory, 321–322
processor, 319–320
Base system builder (BSB) wizard
Linux cross-compiling, 189–190
Xilinx Platform Studio launching, 29–35
Xilinx Platform Studio project files, 167
Basic input/output (BIOS), 159–161
Behavioral circuit, 59, 69
Bit-level parallelism, 248–249
Bitgen, 77, 94
Bitstream
configuration bitstream
generation, 93–94
transition from hardware description language, 74
overview, 77
Black box description (BBD) file, 175
Block random access memory (BRAM)
bandwidth techniques, 300, 302, 314
on-chip memory access, 326
platform field-programmable gate array
architecture design tools, 164
overview, 54–55, 137
Xilinx Virtex 5, 83–84
Block , See Core
Board support package (BLP), 159
Bootloader (PROM), 160–161
Bottom-up approach, 120, 141, 150–152
Bourne shell, 29
Bridge, platform field-programmable gate array, 140
Burst transfer, 310, 321
Bus
bandwidth limitations, 320–321
peripheral bus, 139
platform field-programmable gate array, 138–139
platform field-programmable gate array architecture design tools, 163–164
system bus, 139
Bus master
adding to core, 330–334
logic, 332–334
signals, 330–332

C

Call graph (CG), 202, 233
Capability, field-programmable gate array, 1
Capacity, field-programmable gate array, 1
CG , See Call graph
Char device driver, Linux kernel addition in partitioning, 239–241
ChipScope
Analyzer Pro, 286–289
hardware core modification, 283–286
integrated controller, 283–284
integrated logic analyzer, 283–286
Client/sever model , See Coprocessor model
Clock regions, Xilinx Virtex 5, 86–87
Coarse-grain parallelism, 247
Cohesion, system design, 125
Commodity off-the-shelf (COTS) components, 251
Communication , See Networking
Complementary metal oxide semiconductor (CMOS) transistor, functional overview, 44, 46–47
Complex programmable logic device (CPLD), 48–49
Computing system
abstract view, 3–4
embedded systems, 4–5
general purpose computing system, 5–6
Configurable logic block (CLB)
coupling, 128
overview, 52
Xilinx Virtex 5, 83
Control flow graph (CFG), 129–132, 202
Control parallelism, 253–256
Coprocessor model
blocking, 215–216
fixed timing, 215s
pin-lock, 215
principles, 214–215
special solution, 216
CoreGen, 94–99, 170–171
Correctness
definition, 118
example, 118
Costs
direct costs, 17–18
finance and consumer demand, 19–20
indirect costs, 17–18
nonrecurring engineering costs, 18–19
overview, 17
personnel, 17–18
reuse, 128
spectrometer platform field-programmable gate array example, 26–27
Coupling, system design, 125–128
Create/Import Peripheral (CIP) wizard
bus interface page, 102
hardware core configuration, 170
IPIC page, 106
IPIF page, 103
launching, 99
name and version page, 102
peripheral flow page, 100–101
project page, 100–101
simulation page, 107
slave interface page, 104
slave registers page, 105
summary page, 109
support page, 108
welcome page, 99–100
Cross-compiler, 158
Crosstool-NG, downloading and installing, 185–187
Current, 16
Custom compute core, assembly
design composition and approaches, 148–162
disadvantages, 148
rationale and advantages, 144–148
spatial composition, 152–153

D

Data-flow firing rule, Kahn Process Network, 296
Data-flow graph, Kahn Process Network, 296
Data-flow model, 8–10
Data parallelism, 256
Debugging
monitor, 159–160
spatial design
ChipScope
Analyzer Pro, 286–289
hardware core modification, 283–286
integrated controller, 283–284
integrated logic analyzer, 283–286
inferring components, 280–281
latches versus flip-flops, 279–280
sensitivity list, 279
simulation, 278–281
software addressable registers, 281–282
Decomposition , See Partitioning
Degree of parallelism (DOP), 250
Design entry, definition, 21
Design, see also Spatial design; see also System design
costs
direct costs, 17–18
finance and consumer demand, 19–20
indirect costs, 17–18
nonrecurring engineering costs, 18–19
overview, 17
personnel, 17–18
life cycle of project, 10–12
success measures
energy, 15
overview, 13
power, 16–17
size and packaging, 17
speed, 13–15
total energy, 15–16
Device control register (DCR) bus, 164
Diffused core, 22
Diffused intellectual property, 222
Digital clock manager (DCM), 56, 87
Digital signal processing block (DSP)
overview, 55–56
Xilinx Virtex 5 slices, 84–85
Direct costs, 17–18
Direct memory access (DMA)
bus-based interface, 307–308
controller, 306–307, 328–330
direct connect interface, 308–309
overview, 138
Double buffering, 309
D-type flip-flop, 51
Dual in-line memory module (DIMM), 144
Dynamic Host Configuration Protocol (DHCP), 361

E

Efficiency, custom compute cores, 147–148
Electronic Design Interchange Format (EDIF)
Boolean function, 75
cell hierarchy description, 74
file extensions, 74–75
Embedded Development Kit (EDK)
installation, 28–29
platform field-programmable gate array architecture design
base system building, 166
buses, 163–164
memory, 164
peripherals, 165–166
processors, 163
soft IP cores, 162–163
Energy, performance metric, 15
Evolvability, design quality, 120
Execution models, embedded systems, 7–10
External criteria, design quality, 117

F

Fast simplex link (FSL) bus, 164
Feature, definition, 198
Field-programmable gate array (FPGA), see also Platform field-programmable gate array
application overview, 1–2
blank slate, 1–2
components, 49
function generators, 49–51
input/output blocks, 53
logic blocks, 52–53
logic cells, 51–52
programmable logic device comparison, 21
special-purpose function blocks, 53–57
storage elements, 51
FIFO generation , See CoreGen
Filesystem image, 157–158
Fine-grain parallelism, 247
Finite difference time domain (FDTD), application simulation, 231–233
Finite state machine (FSM)
bus master logic
control finite state machine, 332
read request finite state machine, 332–333
write request finite state machine, 333–334
Native Port Interface
control finite state machine, 338–339
read request finite state machine, 339
write request finite state machine, 339–342
Verilog example, 71–73
VHDL example, 63–68
Formal description, module, 122–123
FSL bus , See Fast simplex link bus
Function generator, field-programmable gate array, 49–51

G

Gate-level modeling circuit, 68
General purpose computing system, 5–6
GNU
embedding, 178–184
release process, 179, 181–183
Go/Dune model , See Coprocessor model
Gprof, profiling, 199, 229–233
Graphical processor unit (GPU), 252

H

HandelC, 73
Hard block, 22
Hard core, 22
Hardware description language (HDL), see also Verilog; see also Very High-Speed Integrated Circuit Hardware Description Language
configuration bitstream transition, 74
debugging of spatial design, 278–281
HandelC, 73
hardware core project directory, 105–110
Impulse, 73
overview, 21, 57–58
simulation, 58
SystemC, 73
Hardware, definition, 7
High-level language (HLL), 158
High-speed serial transceiver, 57, 85–86
Host, networking, 349
Hypertext Markup Language (HTML), 358
Hypertext Transfer Protocol (HTTP), 358

I

IBM CoreConnect, platform field-programmable gate array architecture design
buses, 163–164
memory, 164
peripherals, 165–166
processors, 163
soft IP cores, 162–163
Ifupdown, 361
Implementation, module, 123
Implicit description, module, 121–122
Impulse, 73
Indirect costs, 17–18
Informal description, module, 121–122
Input/output block (IOB), field-programmable gate array, 53
Input/output buffer (IOB), Xilinx Virtex 5, 85
Instance, 123
Instantiate, 123
Instruction-level parallelism, 249
Integrated circuit (IC), field-programmable gate array comparison, 1
Integrated controller (ICON), ChipScope, 283–284
Integrated logic analyzer (ILA), ChipScope, 283–286
Integrated Software Environment (ISE)
commands
configuration bitstream generation, 93–94
map, 92–93
netlist builder, 91–92
place and route, 93
synthesis tool, 88–91
installation, 28–29
Integration stage, design, 11–12
Intellectual property core, 22
Intellectual property interconnect (IPIC), 103–104, 106
Intellectual property interface (IPIF), 100, 103–104
Interface, system design, 121
Interintegrated Circuit (IIC), 348, 368–370
Internal criteria, design quality, 117
Interoperability, design quality, 120
Iteration-level parallelism, 249

K

Kahn Process Network (KPN)
asynchronous design, 298
data-flow firing rule, 296
data-flow graph, 296
overview, 296–298
synchronous design, 298

L

Law of Diminishing Returns, 207
Legal ordering, subtasks, 257
LILO , See Linux Loader
Link layer, networking, 351
Linux
advantages in development, 28
booting on ML-510, 192–193
cross-compiling
hardware base system building, 189–190
kernel compiling, 190
preparation, 187–188
embedding, 178–184
kernel addition in partitioning
address spaces, 236–238
application view, 238–239
char device driver, 239–241
modules, 233–236
Linux Loader (LILO), 161
Local memory bus (LMB), 163
LocalLink, 326–328, 364
Logical link control (LLC), 352
Logic block, field-programmable gate array, 52–53
Logic cell
field-programmable gate array, 51–52
representation in partitioning, 208
Xilinx Virtex 5 slice, 82
Look-up table (LUT)
four-input function mapped to two, 3-LUTs, 76
function generator, 49–51
Xilinx Virtex 5, 82
Loop-carried dependence, 264
Loop-independent dependence, 263
Low-voltage differential signaling (LVDS), 165
LUT , See Look-up table

M

Machine triple, 182–183
Maintainability, design quality, 119
Maintenance stage, design, 12
MAP program, 92–93
Mapping, definition, 76
Media access controller (MAC), 351, 361
Memory
architecture design tools, 164
bandwidth techniques
access, 305–309
block random access memory, 300, 302, 314
direct memory access
bus-based interface, 307–308
controller, 306–307
direct connect interface, 308–309
memory bandwidth, 309–310
off-chip memory access
bus master, 330–332
controllers, 302–304
off-chip memory controllers, 302–304
on-chip memory access
block random access memory, 326
FIFO configuration options, 325
FIFO memory types, 324–325
LocalLink interface, 326–328
overview, 299–302
practical issues, 314
programmable input/output, 305–306
streaming instrument data, 311–314
types, 304–305
overview, 137–138
scalability
constraints, 318–319
solutions, 321–322
Memory controller, platform field-programmable gate array, 137
Memory management unit (MMU), 136, 239
Memory transaction, platform field-programmable gate array, 137–138
Metal oxide semiconductor effect transistor (MOSFET)
complimentary metal oxide semiconductor effect transistor, 46–47
gates, 45
n-channel transistor, 44–45
p-channel transistor, 46
Microprocessor hardware specification (MHS) file, 168
Microprocessor peripheral description file (MPD), 105–107, 175, 342
Microprocessor software specification (MSS) file, 168
ML-510 , See Xilinx ML-510
Modular design approach, 140
Module
definition, 120
functional descriptions, 121–122
system design, 120–123
Module , See Core
Monitor, debugging, 159–160
Mounted filesystem, 157
Multi-Ported Memory Controller (MPMC), 164, 334–336, 338, 342–343
Multiple instruction stream, multiple data stream (MIMD), 251–252
Multiple instruction stream, single data stream (MISD), 251–252
Multithreaded model, partitioning, 216–217

N

NAND gate, 45, 47
Native Port Interface (NPI)
data transfer, 337
finite state machines
control finite state machine, 338–339
read request finite state machine, 339
write request finite state machine, 339–342
little endian, 336–337
logic, 337–342
microprocessor peripheral description file, 342
overview, 323, 334–335
signals, 335–336
Xilinx project modifications, 342–343
Netlist
Integrated Software Environment building, 91–92
synthesis, 74
VHDL, 58
Network File Systems Protocol (NFS), 359
Networking
design testing, 371
high-speed communication
Aurora, 363–364
clock correction, 364–365
error testing, 365
LocalLink, 364
loopback, 365
RocketIO, 363
internetworking communication
application interface, 353–356
Network File Systems Protocol, 359
Network Time Protocol, 359–360
network layer, 352
network topology, 351
overview, 348–353
Secure Socket Layer, 360
Simple Network Management Protocol, 359
Telnet, 357–358
Transmission Control Protocol/Internet Protocol, 349–350, 352–353
World Wide Web, 358
low-speed communication
hardware base system generation, 366–367
microprocessor hardware specification file, 367–368
microprocessor software specification file, 368–370
miscellaneous protocols, 348
RS-232, 346–348
user constraints file, 367
operating system configuration, 360–361
overview, 345–346
Network-on-chip model, partitioning, 217–218
Network Time Protocol (NTP), 359–360
NGCBuild, 91–92
NGDBuild, 92, 175
Nonrecurring engineering costs, 18–19
NOR gate, 45
NOT gate, 45

O

Off-chip memory access , See Bandwidth
Off-line, 4
Ohm’s law, 16
On-chip memory access , See Bandwidth
On-chip peripheral bus (OPB), 163–164
Open Source Interface (OSI), 352
Operating system, configuration, 360–361
OR gate, 47–48, 74

P

Parallel, definition, 246–247
Parallelism
degree of parallelism, 250
granularity, 247–250
identification
dependence, 258–262
ordering, 256–258
uniform dependence vectors, 262–254
spatial organizations, 250–256
spatial parallelism with platform field-programmable gate arrays
hardware cores, 266–271
overview, 264–266
parallelism within designs, 271–272
Partial ordering, subtasks, 258
Partitioning
analytical approach
fraction of execution time, 210
heuristic, 209–210
performance gain, 210–211
problem statement, 209
communication
coprocessor model
blocking, 215–216
fixed timing, 215
principles, 214–215
special solution, 216
spin-lock, 215
error-correcting subroutine, 212
multithreaded model, 216–217
network-on-chip model, 217–218
overview, 211–213
transfer of state
affected state, 218–219
transfer-of-state problem, 221–223
trapped state, 220–221
data structure, 226–227
decomposition, 198
feature
definition, 198
size manipulation, 228
JPEG2000 encoder example, 199–200, 234
Linux kernel addition
address spaces, 236–238
application view, 238–239
char device driver, 239–241
modules, 233–236
overview, 197–199
partitions, 203–204
performance
analysis, 200–201
expected gain, 205–207
profiling
gprof example, 229–233
overview, 199–200
practical issues
correlated behavior, 224
data-dependent execution, 223–224
input/output effects, 225–226
number of calls, 226
phased behavior, 225
resource considerations, 207–209
terminology, 202–205
Pass transistor, 76
Performance metrics
energy, 15
overview, 13
power, 16–17
size and packaging, 17
speed, 13–15
total energy, 15–16
Peripheral analysis order file (PAO), 108–109, 110
Peripheral bus, 139
Peripherals, see also Networking
architecture design of platform field-programmable gate arrays, 165–166
examples of platform field-programmable gate arrays, 140–141
Personnel, costs, 17–18
Physical layer, networking, 350–352
Pipeline balancing, 295
Pipeline parallelism, 252–253
Place-and-route tool (PAR), 77, 93
Placement, definition, 76, 78–79
Platform field-programmable gate array
block diagram, 54–55
definition, 22
hardware design
additions, 142–144
components, 135–142
origins, 133–135
hardware versus software features, 7–8
historical perspective, 22
overview, 2
spatial parallelism , See Parallelism
spectrometer example, 25–27
tool chain , See Xilinx Platform Studio
Portability, design quality, 120
Power
performance metric, 16–17
transistors, 45–46
Power-on-self-test (POST), 159–160
PowerPC 440 processor, Xilinx Virtex 5, 87–88, 163
Predictability, custom compute cores, 148
Primitives
mapping, 76
placement, 76
Printed circuit board (PCB), design, 12
Processor
definition, 9
field-programmable gate array features, 56
platform field-programmable gate array
architecture design tools, 163
overview, 135–137
scalability
constraints, 316
solutions, 319–320
Processor Local Bus (PLB), 139, 143, 163, 330
Profiling, partitioning, 199–200
Program, definition, 7
Programmable input/output, 305–306
Programmable logic array (PLA), 47
Programmable logic device (PLD)
historical perspective, 21, 47
storage addition, 48
PROM , See Bootloader
Prototype, software reference design, 130

R

Refactoring, system design, 129
Regression testing, system design, 129
Regular network topology, 351
Relative cost of reuse (RCR), 128
Relative cost of writing for reuse (RCWR), 128
Reliability
definition, 118
example, 119
Reparability, design quality, 119
Request for comment (RFC), 357
Requirements stage, design, 10
Resilience
definition, 118
example, 119
Resistance, 16
RocketIO, 363
Root filesystem, 156–158
Router, 350
Routing
Route tool, 93
transistors, 77–79
RS-232, 346–348
Run-time, 4

S

Scalability, platform field-programmable gate arrays, 27
Secure Socket Layer (SSL), 360
Sensitivity list, VHDL, 67
Sequential, definition, 246–247
Serial advanced technology attachment (SATA), 165
Serial Peripheral Interface (SPI), 348
Simple Network Management Protocol (SNMP), 359
Simulation, hardware description language, 58
Single instruction stream, multiple data stream (SIMD), 251
Single instruction stream, single data stream (SISD), 251
Single program multiple data (SPMD), 252
Size, performance metric, 17
Slice
logic cells, 52
Xilinx Virtex 5, 82–83
Small computer system interconnect (SCSI), 176
Soft block, 22
Soft core, 22
Software
definition, 7, 154
design , See System design
Software Design Kit (SDK), Xilinx, 36, 39, 177–178
Software reference design, 130
Sparc Improved Boot Loader (SILO), 161
Spatial design
debugging
ChipScope
Analyzer Pro, 286–289
hardware core modification, 283–286
integrated controller, 283–284
integrated logic analyzer, 283–286
inferring components, 280–281
latches versus flip-flops, 279–280
sensitivity list, 279
simulation, 278–281
software addressable registers, 281–282
overview, 245–246
parallelism
degree of parallelism, 250
granularity, 247–250
identification
dependence, 258–262
ordering, 256–258
uniform dependence vectors, 262–254
spatial organizations, 250–256
spatial parallelism with platform field-programmable gate arrays
hardware cores, 266–271
overview, 264–266
parallelism within designs, 271–272
sequential versus parallel, 246–247
Very High-Speed Integrated Circuit Hardware Description Language for spatial design
constants and generics, 273–274
design constraints, 277–278
generate statements, 276–277
user-defined types, 274–276
Spatial implementation, 152–153
Specifications, design, 11
Spectrometer, platform field-programmable gate array example, 25–27
Speed
custom compute cores, 146–147
performance metric, 13–15
Speedup, partitioning, 206–207
Stall, 294
Standalone C program, 154
State, system design, 125
Static random access memory (SRAM), 50–51, 77, 304
Static single assignment (SSA), 259
Storage element, field-programmable gate array, 51
Structural/data flow circuit, 59, 68
Subroutine, definition, 202
Switch box, logic blocks, 52
Synchronous design, Kahn Process Network, 298
Synchronous dynamic random access memory (SDRAM), 304–305
Synthesis, netlist file output, 74
System bus, 139
System design
abstraction, 123–125
cohesion, 125
control flow graph, 129–132
coupling, 125–128
custom compute core assembly
design composition and approaches, 148–162
disadvantages, 148
rationale and advantages, 144–148
spatial composition, 152–153
design quality, 117–120
hardware design
additions to platform field-programmable gate array, 142–144
components, 135–142
origins, 133–135
modules and interfaces, 120–123
overview, 115–116
platform field-programmable gate array architecture design
base system
augmentation, 167
building, 166, 169
core generator
adder generation, 171
FIFO generation, 170–171
user logic template, 171–175
Create/Import Peripheral wizard for hardware core configuration, 170
cross-compiling Linux, 187–190
cross-development tools and libraries, 184–187
embedding of GNU/Linux system
GNU release process, 179, 181–183
menuconfig, 183–184
Unix filesystem organization, 178–180
floating point adder example, 169
hardware core
connection to base system, 176
project file modification, 175–176
Linux booting on ML-510, 192–193
root filesystem building, 190–191
testing
overview, 176–177
Software Design Kit, 177–178
Xilinx Embedded Development Kit and IBM CoreConnect
buses, 163–164
memory, 164
peripherals, 165–166
processors, 163
soft IP cores, 162–163
Xilinx Platform Studio project files
microprocessor hardware specification, 168
microprocessor software specification, 168
overview, 167–168
user constraints file, 168–169
software design
cross-development tools, 158–159
monitors and bootloader, 159–161
options, 154–156
overview, 153
root filesystem, 156–158
state, 125
SystemC, 73

T

Telnet, 357–358
Temporal implementation, 151–152
Test bench, VHDL, 58
Test vector, VHDL, 58
Thread-level parallelism (TLP), 249
Time-to-market, finance and consumer demand, 19–20
Top-down approach, 120, 150–152
Top-level cell, 74
Total energy, performance metric, 15–16
Totally ordered subtasks, 257
Transceiver
high-speed serial transceiver, 57
overview, 57
Xilinx Virtex 5, 85–86
Transmission Control Protocol/Internet Protocol (TCP/IP), 349–350, 352–353
Transportation layer, networking, 352
Trapped state, partitioning, 220–221

U

Universal asynchronous receiver/transmitter (UART), 141–142, 165, 167, 347
Universal Serial Bus (USB), advantages over RS-232, 346
Unix, filesystem organization, 178–180
User constraints file (UCF), 168–169
User Datagram Protocol (UDP), 352

V

Vector parallelism, 252–253
Verifiability, design quality, 119
Verilog
adder circuit examples
1-bit full adder, 69
2-bit full adder, 70–71
finite state machine example, 71–73
overview, 68
syntax, 69–73
synthesizable Verilog, 68–69
Very High-Speed Integrated Circuit Hardware Description Language (VHDL)
adder circuit examples
1-bit full adder, 60–61
2-bit full adder, 61–63
finite state machine example, 63–68
overview, 58
syntax, 59–68
synthesizable VHDL, 58–59
Very High-Speed Integrated Circuit Hardware Description Language, spatial design
constants and generics, 273–274
design constraints, 277–278
generate statements, 276–277
user-defined types, 274–276
Virtex 5 , See Xilinx Virtex 5
Virtex-II Pro, 22
Voltage, 16
von-Neumann stored-program compute model, 8

W

World Wide Web (WWW), 358
WWW , See World Wide Web

X

Xilinx ChipScope , See ChipScope
Xilinx core generator , See CoreGen
Xilinx Embedded Development Kit , See Embedded Development Kit
Xilinx FX130T, 315
Xilinx Integrated Software Environment , See Integrated Software Environment
Xilinx Microprocessor Debugger (XMD), 39
Xilinx ML-510
Linux booting, 192–193
model system, 24
Xilinx Platform Studio (XPS)
Create/Import Peripheral wizard, 99–105
downloading hardware and software, 39–40
graphical user interface
launching, 29–35
overview, 34–36
installation, 28–29
project files
microprocessor hardware specification, 168
microprocessor software specification, 168
overview, 167–168
user constraints file, 168–169
Software Design Kit, 36, 39
software platform windows, 36–38
Xilinx Synthesis Tool (XST), 88–91
Xilinx Virtex 5
block random access memory, 83–84
clock regions, 86–87
configurable logic block, 83
digital signal processing block slices, 84–85
groups of devices, 81
input/output buffer, 85
look-up table, 82
PowerPC 440 processor, 87–88
resource allocation, 208
slice, 82–83
transceiver, 85–86
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