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Appendix A: The ARM Instruction Set

This appendix lists the ARM 64-bit instruction in two sections: first, the core instruction set, then the NEON and FPU instructions. There is a brief description of each instruction:

{S} after an instruction indicates you can optionally set the condition flags.

† means the instruction is an alias.

ARM 64-Bit Core Instructions

Instruction	Description
ADC{S}	Add with carry
ADD{S}	Add
ADDG	Add with tag
ADR	Form PC relative address
ADRP	Form PC relative address to 4KB page
AND{S}	Bitwise AND
ASR†	Arithmetic shift right
ASRV	Arithmetic shift right variable
AT†	Address translate
AUTDA, AUTDZA	Authenticate data address, using key A
AUTDB, AUTDZB	Authenticate data address, using key B
AUTIA, AUTIA1716	Authenticate instruction address, using key A
AUTIASP, AUTIAZ	Authenticate instruction address, using key A
AUTIZA	Authenticate instruction address, using key A
AUTIB, AUTIB1716	Authenticate instruction address, using key B
AUTIBSP, AUTIBZ	Authenticate instruction address, using key B
AUTIZB	Authenticate instruction address, using key B
AXFlag	Convert floating-point condition flags
B	Branch
B.cond	Branch conditionally
BFC†	Bitfield clear
BFI†	Bitfield insert
BFM	Bitfield move
BFXIL†	Bitfield extract and insert at low end
BIC{S}	Bitwise bit clear
BL	Branch with link
BLR	Branch with link to register
BLRAA, BLRAAZ	Branch with link to register, with pointer authentication
BLRAB, BLRABZ	Branch with link to register, with pointer authentication
BR	Branch to register
BRAA, BRAAZ	Branch to register, with pointer authentication
BRAB, BRABZ	Branch to register, with pointer authentication
BRK	Breakpoint instruction
BTI	Branch target identification
CAS, CASA	Compare and swap word or doubleword in memory
CASAL, CASL	Compare and swap word or doubleword in memory
CASB, CASAB	Compare and swap byte in memory
CASALB, CASLB	Compare and swap byte in memory
CASH, CASAH	Compare and swap halfword in memory
CASALH, CASLH	Compare and swap halfword in memory
CASP, CASPA	Compare and swap pair of words or doublewords in memory
CASPAL, CASPL	Compare and swap pair of words or doublewords in memory
CBNZ	Compare and branch on nonzero
CBZ	Compare and branch on zero
CCMN	Conditional compare negative
CCMP	Conditional compare
CFINV	Invert carry flag
CFP†	Control flow prediction restriction by context
CINC†	Conditional increment
CINV†	Conditional invert
CLREX	Clear exclusive
CLS	Count leading sign bits
CLZ	Count leading zeros
CMN†	Compare negative
CMP†	Compare
CMPP†	Compare with tag
CNEG†	Conditional negate
CPP†	Cache prefetch prediction restriction by context
CRC32B, CRC32H	CRC32 checksum
CRC32W, CRC32X	CRC32 checksum
CRC32CB	CRC32C checksum
CRC32CH	CRC32C checksum
CRC32CW	CRC32C checksum
CRC32CX	CRC32C checksum
CSDB	Consumption of speculative data barrier
CSEL	Conditional select
CSET†	Conditional set
CSETM†	Conditional set mask
CSINC	Conditional select increment
CSINV	Conditional select invert
CSNEG	Conditional select negation
DC†	Data cache operation
DCPS1	Debug change PE state to EL1
DCPS2	Debug change PE state to EL2
DCPS3	Debug change PE state to EL3
DMB	Data memory barrier
DRPS	Debug restore process state
DSB	Data synchronization barrier
DVP†	Data value prediction restriction by context
EON	Bitwise exclusive OR NOT
EOR	Bitwise exclusive OR
ERET	Exception return
ERETAA, ERETAB	Exception return, with pointer authentication
ESB	Error synchronization barrier
EXTR	Extract register
GMI	Tag mask insert
HINT	Hint instruction
HLT	Halt instruction
HVC	Hypervisor call
IC†	Instruction cache operation
IRG	Insert random tag
ISB	Instruction synchronization barrier
LDADD, LDADDA	Atomic add on word or doubleword in memory
LDADDAL, LDADDL	Atomic add on word or doubleword in memory
LDADDB, LDADDAB	Atomic add on byte in memory
LDADDALB	Atomic add on byte in memory
LDADDLB	Atomic add on byte in memory
LDADDH	Atomic add on halfword in memory
LDADDAH	Atomic add on halfword in memory
LDADDALH	Atomic add on halfword in memory
LDADDLH	Atomic add on halfword in memory
LDAPR	Load-acquire RCpc register
LDAPRB	Load-acquire RCpc register byte
LDAPRH	Load-acquire RCpc register halfword
LDAPUR	Load-acquire RCpc register (unscaled)
LDAPURB	Load-acquire RCpc register byte (unscaled)
LDAPURH	Load-acquire RCpc register halfword (unscaled)
LDAPURSB	Load-acquire RCpc register signed byte (unscaled)
LDAPURSH	Load-acquire RCpc register signed halfword (unscaled)
LDAPURSW	Load-acquire RCpc register signed word (unscaled)
LDAR	Load-acquire register
LDARB	Load-acquire register byte
LDARH	Load-acquire register halfword
LDAXP	Load-acquire exclusive pair of registers
LDAXR	Load-acquire exclusive register
LDAXRB	Load-acquire exclusive register byte
LDAXRH	Load-acquire exclusive register halfword
LDCLR, LDCLRA	Atomic bit clear on word or doubleword in memory
LDCLRAL, LDCLRL	Atomic bit clear on word or doubleword in memory
LDCLRB, LDCLRAB	Atomic bit clear on byte in memory
LDCLRALB	Atomic bit clear on byte in memory
LDCLRLB	Atomic bit clear on byte in memory
LDCLRH, LDCLRAH	Atomic bit clear on halfword in memory
LDCLRALH	Atomic bit clear on halfword in memory
LDCLRLH	Atomic bit clear on halfword in memory
LDEOR, LDEORA	Atomic exclusive OR on word or doubleword in memory
LDEORAL, LDEORL	Atomic exclusive OR on word or doubleword in memory
LDEORB, LDEORAB	Atomic exclusive OR on byte in memory
LDEORALB	Atomic exclusive OR on byte in memory
LDEORLB	Atomic exclusive OR on byte in memory
LDEORH, LDEORAH	Atomic exclusive OR on halfword in memory
LDEORALH	Atomic exclusive OR on halfword in memory
LDEORLH	Atomic exclusive OR on halfword in memory
LDG	Load allocation tag
LDGV	Load allocation tag
LDLAR	Load LOAcquire register
LDLARB	Load LOAcquire register byte
LDLARH	Load LOAcquire register halfword
LDNP	Load pair of registers, with non-temporal hint
LDP	Load pair of registers
LDPSW	Load pair of registers signed word
LDR	Load register
LDRAA, LDRAB	Load register, with pointer authentication
LDRB	Load register byte
LDRH	Load register halfword
LDRSB	Load register signed byte
LDRSH	Load register signed halfword
LDRSW	Load register signed word
LDSET, LDSETA	Atomic bit set on word or doubleword in memory
LDSETAL, LDSETL	Atomic bit set on word or doubleword in memory
LDSETB, LDSETAB	Atomic bit set on byte in memory
LDSETALB	Atomic bit set on byte in memory
LDSETLB	Atomic bit set on byte in memory
LDSETH, LDSETAH	Atomic bit set on halfword in memory
LDSETALH	Atomic bit set on halfword in memory
LDSETLH	Atomic bit set on halfword in memory
LDSMAX	Atomic signed maximum on word or doubleword in memory
LDSMAXA	Atomic signed maximum on word or doubleword in memory
LDSMAXAL	Atomic signed maximum on word or doubleword in memory
LDSMAXL	Atomic signed maximum on word or doubleword in memory
LDSMAXB	Atomic signed maximum on byte in memory
LDSMAXAB	Atomic signed maximum on byte in memory
LDSMAXALB	Atomic signed maximum on byte in memory
LDSMAXLB	Atomic signed maximum on byte in memory
LDSMAXH	Atomic signed maximum on halfword in memory
LDSMAXAH	Atomic signed maximum on halfword in memory
LDSMAXALH	Atomic signed maximum on halfword in memory
LDSMAXLH	Atomic signed maximum on halfword in memory
LDSMIN, LDSMINA	Atomic signed minimum on word or doubleword in memory
LDSMINAL	Atomic signed minimum on word or doubleword in memory
LDSMINL	Atomic signed minimum on word or doubleword in memory
LDSMINB	Atomic signed minimum on byte in memory
LDSMINAB	Atomic signed minimum on byte in memory
LDSMINALB	Atomic signed minimum on byte in memory
LDSMINLB	Atomic signed minimum on byte in memory
LDSMINH	Atomic signed minimum on halfword in memory
LDSMINAH	Atomic signed minimum on halfword in memory
LDSMINALH	Atomic signed minimum on halfword in memory
LDSMINLH	Atomic signed minimum on halfword in memory
LDTR	Load register (unprivileged)
LDTRB	Load register byte (unprivileged)
LDTRH	Load register halfword (unprivileged)
LDTRSB	Load register signed byte (unprivileged)
LDTRSH	Load register signed halfword (unprivileged)
LDTRSW	Load register signed word (unprivileged)
LDUMAX	Atomic unsigned maximum on word or doubleword in memory
LDUMAXA	Atomic unsigned maximum on word or doubleword in memory
LDUMAXAL	Atomic unsigned maximum on word or doubleword in memory
LDUMAXL	Atomic unsigned maximum on word or doubleword in memory
LDUMAXB	Atomic unsigned maximum on byte in memory
LDUMAXAB	Atomic unsigned maximum on byte in memory
LDUMAXALB	Atomic unsigned maximum on byte in memory
LDUMAXLB	Atomic unsigned maximum on byte in memory
LDUMAXH	Atomic unsigned maximum on halfword in memory
LDUMAXAH	Atomic unsigned maximum on halfword in memory
LDUMAXALH	Atomic unsigned maximum on halfword in memory
LDUMAXLH	Atomic unsigned maximum on halfword in memory
LDUMIN	Atomic unsigned minimum on word or doubleword in memory
LDUMINA	Atomic unsigned minimum on word or doubleword in memory
LDUMINAL	Atomic unsigned minimum on word or doubleword in memory
LDUMINL	Atomic unsigned minimum on word or doubleword in memory
LDUMINB	Atomic unsigned minimum on byte in memory
LDUMINAB	Atomic unsigned minimum on byte in memory
LDUMINALB	Atomic unsigned minimum on byte in memory
LDUMINLB	Atomic unsigned minimum on byte in memory
LDUMINH	Atomic unsigned minimum on halfword in memory
LDUMINAH	Atomic unsigned minimum on halfword in memory
LDUMINALH	Atomic unsigned minimum on halfword in memory
LDUMINLH	Atomic unsigned minimum on halfword in memory
LDUR	Load register (unscaled)
LDURB	Load register byte (unscaled)
LDURH	Load register halfword (unscaled)
LDURSB	Load register signed byte (unscaled)
LDURSH	Load register signed halfword (unscaled)
LDURSW	Load register signed word (unscaled)
LDXP	Load exclusive pair of registers
LDXR	Load exclusive register
LDXRB	Load exclusive register byte
LDXRH	Load exclusive register halfword
LSL†	Logical shift left
LSLV	Logical shift left variable
LSR†	Logical shift right
LSRV	Logical shift right variable
MADD	Multiply-add
MNEG†	Multiply-negate
MOV†	Move
MOVK	Move wide with keep
MOVN	Move wide with NOT
MOVZ	Move wide with zero
MRS	Move system register
MSR	Move value to special register
MSUB	Multiply-subtract
MUL†	Multiply
MVN†	Bitwise NOT
NEG{S}†	Negate
NGC{S}†	Negate with carry
NOP	No operation
ORN	Bitwise OR NOT
ORR	Bitwise OR
PACDA, PACDZA	Pointer authentication code for data address, using key A
PACDB, PACDZB	Pointer authentication code for data address, using key B
PACGA	Pointer authentication code, using generic key
PACIA, PACIA1716	Pointer authentication code for instruction address, using key A
PACIASP, PACIAZ	Pointer authentication code for instruction address, using key A
PACIZA	Pointer authentication code for instruction address, using key A
PACIB, PACIB1716	Pointer authentication code for instruction address, using key B
PACIBSP, PACIBZ	Pointer authentication code for instruction address, using key B
PACIZ	Pointer authentication code for instruction address, using key B
PRFM	Prefetch memory
PSB CSYNC	Profiling synchronization barrier
PSSBB	Physical speculative store bypass barrier
RBIT	Reverse bits
RET	Return from subroutine
RETAA, RETAB	Return from subroutine, with pointer authentication
REV	Reverse bytes
REV16	Reverse bytes in 16-bit halfwords
REV32	Reverse bytes in 32-bit words
REV64†	Reverse bytes
RMIF	Rotate, mask insert flags
ROR†	Rotate right
RORV	Rotate right variable
SB	Speculation barrier
SBC{S}	Subtract with carry
SBFIZ†	Signed bitfield insert in zero
SBFM	Signed bitfield move
SBFX†	Signed bitfield extract
SDIV	Signed divide
SETF8, SETF16	Evaluation of 8- or 16-bit flag values
SEV	Send event
SEVL	Send event local
SMADDL	Signed multiply-add long
SMC	Secure monitor call
SMNEGL†	Signed multiply-negate long
SMSUBL	Signed multiply-subtract long
SMULH	Signed multiply high
SMULL	Signed multiply long: an alias of SMADDL
SSBB	Speculative store bypass barrier
ST2G	Store allocation tags
STADD, STADDL†	Atomic add on word or doubleword in memory, without return
STADDB†	Atomic add on byte in memory, without return
STADDLB†	Atomic add on byte in memory, without return
STADDH†	Atomic add on halfword in memory, without return
STADDLH†	Atomic add on halfword in memory, without return
STCLR, STCLRL†	Atomic bit clear on word or doubleword in memory, without return
STCLRB, STCLRLB†	Atomic bit clear on byte in memory, without return
STCLRH, STCLRLH†	Atomic bit clear on halfword in memory, without return
STEOR, STEORL†	Atomic exclusive OR on word or doubleword in memory, without return
STEORB, STEORLB†	Atomic exclusive OR on byte in memory, without return
STEORH, STEORLH†	Atomic exclusive OR on halfword in memory, without return
STG	Store allocation tag
STGP	Store allocation tag and pair of registers
STGV	Store tag vector
STLLR	Store LORelease register
STLLRB	Store LORelease register byte
STLLRH	Store LORelease register halfword
STLR	Store-release register
STLRB	Store-release register byte
STLRH	Store-release register halfword
STLUR	Store-release register (unscaled)
STLURB	Store-release register byte (unscaled)
STLURH	Store-release register halfword (unscaled)
STLXP	Store-release exclusive pair of registers
STLXR	Store-release exclusive register
STLXRB	Store-release exclusive register byte
STLXRH	Store-release exclusive register halfword
STNP	Store pair of registers, with non-temporal hint
STP	Store pair of registers
STR	Store register
STRB	Store register byte
STRH	Store register halfword
STSET, STSETL†	Atomic bit set on word or doubleword in memory, without return
STSETB, STSETLB†	Atomic bit set on byte in memory, without return
STSETH, STSETLH†	Atomic bit set on halfword in memory, without return
STSMAX†	Atomic signed maximum on word or doubleword in memory
STSMAXL†	Atomic signed maximum on word or doubleword in memory
STSMAXB†	Atomic signed maximum on byte in memory, without return
STSMAXLB†	Atomic signed maximum on byte in memory, without return
STSMAXH†	Atomic signed maximum on halfword in memory, without return
STSMAXLH†	Atomic signed maximum on halfword in memory, without return
STSMIN, STSMINL†	Atomic signed minimum on word or doubleword in memory, without return
STSMINB†	Atomic signed minimum on byte in memory, without return
STSMINLB†	Atomic signed minimum on byte in memory, without return
STSMINH†	Atomic signed minimum on halfword in memory, without return
STSMINLH†	Atomic signed minimum on halfword in memory, without return
STTR	Store register (unprivileged)
STTRB	Store register byte (unprivileged)
STTRH	Store register halfword (unprivileged)
STUMAX†	Atomic unsigned maximum on word or doubleword in memory
STUMAXL†	Atomic unsigned maximum on word or doubleword in memory
STUMAXB†	Atomic unsigned maximum on byte in memory
STUMAXLB†	Atomic unsigned maximum on byte in memory
STUMAXH†	Atomic unsigned maximum on halfword in memory
STUMAXLH†	Atomic unsigned maximum on halfword in memory
STUMIN†	Atomic unsigned minimum on word or doubleword in memory
STUMINL†	Atomic unsigned minimum on word or doubleword in memory
STUMINB†	Atomic unsigned minimum on byte in memory
STUMINLB†	Atomic unsigned minimum on byte in memory
STUMINH†	Atomic unsigned minimum on halfword in memory
STUMINLH†	Atomic unsigned minimum on halfword in memory
STUR	Store register (unscaled)
STURB	Store register byte (unscaled)
STURH	Store register halfword (unscaled)
STXP	Store exclusive pair of registers
STXR	Store exclusive register
STXRB	Store exclusive register byte
STXRH	Store exclusive register halfword
STZ2G	Store allocation tags, zeroing
STZG	Store allocation tag, zeroing
SUB{S}	Subtract
SUBG	Subtract with tag
SUBP{S}	Subtract pointer
SVC	Supervisor call
SWP, SWPA	Swap word or doubleword in memory
SWPAL, SWPL	Swap word or doubleword in memory
SWPB, SWPAB	Swap byte in memory
SWPALB, SWPLB	Swap byte in memory
SWPH, SWPAH	Swap halfword in memory
SWPALH, SWPLH	Swap halfword in memory
SXTB†	Signed extend byte
SXTH†	Sign extend halfword
SXTW†	Sign extend word
SYS	System instruction
SYSL	System instruction with result
TBNZ	Test bit and branch if nonzero
TBZ	Test bit and branch if zero
TLBI†	TLB invalidate operation
TSB CSYNC	Trace synchronization barrier
TST†	Test bits
UBFIZ†	Unsigned bitfield insert in zero
UBFM	Unsigned bitfield move
UBFX†	Unsigned bitfield extract
UDF	Permanently undefined
UDIV	Unsigned divide
UMADDL	Unsigned multiply-add long
UMNEGL†	Unsigned multiply-negate long
UMSUBL	Unsigned multiply-subtract long
UMULH	Unsigned multiply high
UMULL†	Unsigned multiply long
UXTB†	Unsigned extend byte
UXTH†	Unsigned extend halfword
WFE	Wait for event
WFI	Wait for interrupt
XAFlag	Convert floating-point condition flags from external format to ARM format
XPACD, XPACI	Strip pointer authentication code
XPACLRI	Strip pointer authentication code
YIELD	Yield

ARM 64-Bit NEON and FPU Instructions

Instruction	Description
ABS	Absolute value
ADD	Add
ADDHN, ADDHN2	Add returning high narrow
ADDP	Add pair of elements
ADDV	Add across vector
AESD	AES single round decryption
AESE	AES single round encryption
AESIMC	AES inverse mix columns
AESMC	AES mix columns
AND	Bitwise AND
BCAX	Bit clear and XOR
BIC	Bitwise bit clear
BIF	Bitwise insert if false
BIT	Bitwise insert if true
BSL	Bitwise select
CLS	Count leading sign bits
CLZ	Count leading zero bits
CMEQ	Compare bitwise equal
CMGE	Compare signed greater than or equal
CMGT	Compare signed greater than
CMHI	Compare unsigned higher
CMHS	Compare unsigned higher or same
CMLE	Compare signed less than or equal to zero
CMLT	Compare signed less than zero
CMTST	Compare bitwise test bits nonzero
CNT	Population count per byte
DUP	Duplicate vector element to vector or scalar
EOR	Bitwise exclusive OR
EOR3	Three-way exclusive OR
EXT	Extract vector from pair of vectors
FABD	Floating-point absolute difference
FABS	Floating-point absolute value
FACGE	Floating-point absolute compare greater than or equal
FACGT	Floating-point absolute compare greater than
FADD	Floating-point add
FADDP	Floating-point add pair of elements
FCADD	Floating-point complex add
FCCMP	Floating-point conditional quiet compare
FCCMPE	Floating-point conditional signaling compare
FCMEQ	Floating-point compare equal
FCMGE	Floating-point compare greater than or equal
FCMGT	Floating-point compare greater than
FCMLA	Floating-point complex multiply accumulate
FCMLE	Floating-point compare less than or equal to zero
FCMLT	Floating-point compare less than zero
FCMP	Floating-point quiet compare
FCMPE	Floating-point signaling compare
FCSEL	Floating-point conditional select
FCVT	Floating-point convert precision
FCVTAS	Floating-point convert to signed integer, rounding to nearest
FCVTAU	Floating-point convert to unsigned integer, rounding to nearest
FCVTL, FCVTL2	Floating-point convert to higher precision long
FCVTMS	Floating-point convert to signed integer, rounding toward minus infinity
FCVTMU	Floating-point convert to unsigned integer, rounding toward minus infinity
FCVTN, FCVTN2	Floating-point convert to lower precision narrow
FCVTNS	Floating-point convert to signed integer, rounding to nearest
FCVTNU	Floating-point convert to unsigned integer, rounding to nearest
FCVTPS	Floating-point convert to signed integer, rounding toward plus infinity
FCVTPU	Floating-point convert to unsigned integer, rounding toward plus infinity
FCVTXN, FCVTXN2	Floating-point convert to lower precision narrow, rounding to odd
FCVTZS	Floating-point convert to signed fixed point, rounding toward zero
FCVTZU	Floating-point convert to unsigned fixed point, rounding toward zero
FDIV	Floating-point divide
FJCVTZS	Floating-point JavaScript convert to signed fixed point
FMADD	Floating-point fused multiply-add
FMAX	Floating-point maximum
FMAXNM	Floating-point maximum number
FMAXNMP	Floating-point maximum number of pair of elements
FMAXNMV	Floating-point maximum number across vector
FMAXP	Floating-point maximum of pair of elements
FMAXV	Floating-point maximum across vector
FMIN	Floating-point minimum
FMINNM	Floating-point minimum number
FMINNMP	Floating-point minimum number of pair of elements
FMINNMV	Floating-point minimum number across vector
FMINP	Floating-point minimum of pair of elements
FMINV	Floating-point minimum across vector
FMLA	Floating-point fused multiply-add to accumulator
FMLAL, FMLAL2	Floating-point fused multiply-add long to accumulator
FMLS	Floating-point fused multiply-subtract from accumulator
FMLSL, FMLSL2	Floating-point fused multiply-subtract long from accumulator
FMOV	Floating-point move to or from general-purpose register
FMSUB	Floating-point fused multiply-subtract
FMUL	Floating-point multiply
FMULX	Floating-point multiply extended
FNEG	Floating-point negate
FNMADD	Floating-point negated fused multiply-add
FNMSUB	Floating-point negated fused multiply-subtract
FNMUL	Floating-point multiply-negate
FRECPE	Floating-point reciprocal estimate
FRECPS	Floating-point reciprocal step
FRECPX	Floating-point reciprocal exponent
FRINT32X	Floating-point round to 32-bit integer, using current rounding mode
FRINT32Z	Floating-point round to 32-bit integer toward zero
FRINT64X	Floating-point round to 64-bit integer, using current rounding mode
FRINT64Z	Floating-point round to 64-bit integer toward zero
FRINTA	Floating-point round to integral, to nearest with ties to away
FRINTI	Floating-point round to integral, using current rounding mode
FRINTM	Floating-point round to integral, toward minus infinity
FRINTN	Floating-point round to integral, to nearest with ties to even
FRINTP	Floating-point round to integral, toward plus infinity
FRINTX	Floating-point round to integral exact, using current rounding mode
FRINTZ	Floating-point round to integral, toward zero
FRSQRTE	Floating-point reciprocal square root estimate
FRSQRTS	Floating-point reciprocal square root step
FSQRT	Floating-point square root
FSUB	Floating-point subtract
INS	Insert vector element from another vector element
LD1	Load multiple single-element structures to one, two, three, or four registers
LD1R	Load one single-element structure and replicate to all lanes
LD2	Load multiple 2-element structures to two registers
LD2R	Load single 2-element structure and replicate to all lanes of two registers
LD3	Load multiple 3-element structures to three registers
LD3R	Load single 3-element structure and replicate to all lanes of three registers
LD4	Load multiple 4-element structures to four registers
LD4R	Load single 4-element structure and replicate to all lanes of four registers
LDNP	Load pair of SIMD&FP registers, with non-temporal hint
LDP	Load pair of SIMD&FP registers
LDR	Load SIMD&FP register
LDUR	Load SIMD&FP register
MLA	Multiply-add to accumulator
MLS	Multiply-subtract from accumulator
MOV†	Move vector element to another vector element
MOVI	Move immediate
MUL	Multiply
MVN†	Bitwise NOT
MVNI	Move inverted immediate
NEG	Negate
NOT	Bitwise NOT
ORN	Bitwise inclusive OR NOT
ORR	Bitwise inclusive OR
PMUL	Polynomial multiply
PMULL, PMULL2	Polynomial multiply long
RADDHN	Rounding add returning high narrow
RADDHN2	Rounding add returning high narrow
RAX1	Rotate and exclusive OR
RBIT	Reverse bit order
REV16	Reverse elements in 16-bit halfwords
REV32	Reverse elements in 32-bit words
REV64	Reverse elements in 64-bit doublewords
RSHRN, RSHRN2	Rounding shift right narrow
RSUBHN, RSUBHN2	Rounding subtract returning high narrow
SABA	Signed absolute difference and accumulate
SABAL, SABAL2	Signed absolute difference and accumulate long
SABD	Signed absolute difference
SABDL, SABDL2	Signed absolute difference long
SADALP	Signed add and accumulate long pairwise
SADDL, SADDL2	Signed add long
SADDLP	Signed add long pairwise
SADDLV	Signed add long across vector
SADDW, SADDW2	Signed add wide
SCVTF	Signed fixed point convert to floating point
SDOT	Dot product signed arithmetic
SHA1C	SHA1 hash update (choose)
SHA1H	SHA1 fixed rotate
SHA1M	SHA1 hash update (majority)
SHA1P	SHA1 hash update (parity)
SHA1SU0	SHA1 schedule update 0
SHA1SU1	SHA1 schedule update 1
SHA256H	SHA256 hash update (part 1)
SHA256H2	SHA256 hash update (part 2)
SHA256SU0	SHA256 schedule update 0
SHA256SU1	SHA256 schedule update 1
SHA512H	SHA512 hash update part 1
SHA512H2	SHA512 hash update part 2
SHA512SU0	SHA512 schedule update 0
SHA512SU1	SHA512 schedule update 1
SHADD	Signed halving add
SHL	Shift left
SHLL, SHLL2	Shift left long
SHRN, SHRN2	Shift right narrow
SHSUB	Signed halving subtract
SLI	Shift left and insert
SM4E	SM4 encode
SM4EKEY	SM4 key
SMAX	Signed maximum
SMAXP	Signed maximum pairwise
SMAXV	Signed maximum across vector
SMIN	Signed minimum
SMINP	Signed minimum pairwise
SMINV	Signed minimum across vector
SMLAL, SMLAL2	Signed multiply-add long
SMLSL, SMLSL2	Signed multiply-subtract long
SMOV	Signed move vector element to general-purpose register
SMULL, SMULL2	Signed multiply long
SQABS	Signed saturating absolute value
SQADD	Signed saturating add
SQDMLAL	Signed saturating doubling multiply-add long
SQDMLAL2	Signed saturating doubling multiply-add long
SQDMLSL	Signed saturating doubling multiply-subtract long
SQDMLSL2	Signed saturating doubling multiply-subtract long
SQDMULH	Signed saturating doubling multiply returning high half
SQDMULL	Signed saturating doubling multiply long
SQDMULL2	Signed saturating doubling multiply long
SQNEG	Signed saturating negate
SQRDMLAH	Signed saturating rounding doubling multiply accumulate
SQRDMLSH	Signed saturating rounding doubling multiply subtract returning high half
SQRDMULH	Signed saturating rounding doubling multiply returning high half
SQRSHL	Signed saturating rounding shift left
SQRSHRN	Signed saturating rounded shift right narrow
SQRSHRN2	Signed saturating rounded shift right narrow
SQRSHRUN	Signed saturating rounded shift right unsigned narrow
SQRSHRUN2	Signed saturating rounded shift right unsigned narrow
SQSHL	Signed saturating shift left
SQSHLU	Signed saturating shift left unsigned
SQSHRN, SQSHRN2	Signed saturating shift right narrow
SQSHRUN	Signed saturating shift right unsigned narrow
SQSHRUN2	Signed saturating shift right unsigned narrow
SQSUB	Signed saturating subtract
SQXTN, SQXTN2	Signed saturating extract narrow
SQXTUN, SQXTUN2	Signed saturating extract unsigned narrow
SRHADD	Signed rounding halving add
SRI	Shift right and insert
SRSHL	Signed rounding shift left
SRSHR	Signed rounding shift right
SRSRA	Signed rounding shift right and accumulate
SSHL	Signed shift left
SSHLL, SSHLL2	Signed shift left long
SSHR	Signed shift right
SSRA	Signed shift right and accumulate
SSUBL, SSUBL2	Signed subtract long
SSUBW, SSUBW2	Signed subtract wide
ST1	Store multiple single-element structures from one to four registers
ST2	Store multiple 2-element structures from two registers
ST3	Store multiple 3-element structures from three registers
ST4	Store multiple 4-element structures from four registers
STNP	Store pair of SIMD&FP registers, with non-temporal hint
STP	Store pair of SIMD&FP registers
STR	Store SIMD&FP register
STUR	Store SIMD&FP register (unscaled offset)
SUB	Subtract
SUBHN, SUBHN2	Subtract returning high narrow
SUQADD	Signed saturating accumulate of unsigned value
SXTL, SXTL2†	Signed extend long
TBL	Table vector lookup
TBX	Table vector lookup extension
TRN1	Transpose vectors (primary)
TRN2	Transpose vectors (secondary)
UABA	Unsigned absolute difference and accumulate
UABAL, UABAL2	Unsigned absolute difference and accumulate long
UABD	Unsigned absolute difference
UABDL, UABDL2	Unsigned absolute difference long
UADALP	Unsigned add and accumulate long pairwise
UADDL, UADDL2	Unsigned add long
UADDLP	Unsigned add long pairwise
UADDLV	Unsigned sum long across vector
UADDW, UADDW2	Unsigned add wide
UCVTF	Unsigned fixed point convert to floating point
UDOT	Dot product unsigned arithmetic
UHADD	Unsigned halving add
UHSUB	Unsigned halving subtract
UMAX	Unsigned maximum
UMAXP	Unsigned maximum pairwise
UMAXV	Unsigned maximum across vector
UMIN	Unsigned minimum
UMINP	Unsigned minimum pairwise
UMINV	Unsigned minimum across vector
UMLAL, UMLAL2	Unsigned multiply-add long
UMLSL, UMLSL2	Unsigned multiply-subtract long
UMOV	Unsigned move vector element to general-purpose register
UMULL, UMULL2	Unsigned multiply long
UQADD	Unsigned saturating add
UQRSHL	Unsigned saturating rounding shift left
UQRSHRN	Unsigned saturating rounded shift right narrow
UQRSHRN2	Unsigned saturating rounded shift right narrow
UQSHL	Unsigned saturating shift left
UQSHRN	Unsigned saturating shift right narrow
UQSHRN2	Unsigned saturating shift right narrow
UQSUB	Unsigned saturating subtract
UQXTN, UQXTN2	Unsigned saturating extract narrow
URECPE	Unsigned reciprocal estimate
URHADD	Unsigned rounding halving add
URSHL	Unsigned rounding shift left
URSHR	Unsigned rounding shift right
URSQRTE	Unsigned reciprocal square root estimate
URSRA	Unsigned rounding shift right and accumulate
USHL	Unsigned shift left
USHLL, USHLL2	Unsigned shift left long
USHR	Unsigned shift right
USQADD	Unsigned saturating accumulate of signed value
USRA	Unsigned shift right and accumulate
USUBL, USUBL2	Unsigned subtract long
USUBW, USUBW2	Unsigned subtract wide
UXTL, UXTL2†	Unsigned extend long
UZP2	Unzip vectors
XAR	Exclusive OR and rotate
XTN, XTN2	Extract narrow
ZIP1, ZIP2	Zip vectors

Appendix B: Binary Formats

This appendix describes the basic characteristics of the data types we have been working with.

Table B-1

Size, alignment, range, and C type for the basic integer types

Size	Type	Alignment in Bytes	Range	C Type
8	Signed	1	–128 to 127	signed char
8	Unsigned	1	0 to 255	char
16	Signed	2	–32,768 to 32,767	short
16	Unsigned	2	0 to 65,535	unsigned short
32	Signed	4	–2,147,483,648 to 2,147,483,647	int
32	Unsigned	4	0 to 4,294,967,295	unsigned int
64	Signed	8	–9,223,372,036,854,775,808 to 9,223,372,036,854,775,807	long long
64	Unsigned	8	0 to 18,446,744,073,709,551,615	unsigned long long

Table B-2

Size, alignment, positive range, and C type for floating-point numbers

Size	Alignment in Bytes	Range	C Type
16	2	0.000061035 to 65504	half
32	4	1.175494351e-38 to 3.40282347e+38	float
64	8	2.22507385850720138e-308 to 1.79769313486231571e+308	double

Table B-3

Size, range, and C type of a pointer

Size	Range	C Type
64	0 to 18,446,744,073,709,551,615	void ∗

Integers

The following table provides the basic integer data types we have used. Signed integers are represented in two’s complement form.

Floating Point

The ARM floating point and NEON coprocessors use the IEEE-754 standard for representing floating-point numbers. All floating-point numbers are signed.

Note

The ARM implementation of 16-bit half-precision floating point differs from the standard by not supporting infinity or NaNs.

Note

Not all C compilers support 16-bit floating-point numbers.

These ranges are for normalized values; the ARM processor will allow floats to become unnormalized to avoid underflow.

Addresses

All addresses or pointers are 64 bits. They point to memory in the processes virtual address space. They do not point directly to physical memory.

Appendix C: Assembler Directives

This appendix lists a useful selection of GNU Assembler directives . It includes all the directives used in this book and a few more that are commonly used.

Directive	Description
.align	Pad the location counter to a particular storage boundary
.ascii	Defines memory for an ASCII string with no NULL terminator
.asciz	Defines memory for an ASCII string and adds a NULL terminator
.byte	Defines memory for bytes
.data	Assembles following code to the end of the data subsection
.double	Defines memory for double floating-point data
.dword	Defines storage for 64-bit integers
.else	Part of conditional assembly
.elseif	Part of conditional assembly
.endif	Part of conditional assembly
.endm	End of a macro definition
.endr	End of a repeat block
.equ	Defines values for symbols
.fill	Defines and fills some memory
.float	Defines memory for single-precision floating-point data
.global	Makes a symbol global, needed if reference from other files
.hword	Defines memory for 16-bit integers
.if	Marks the beginning of code to be conditionally assembled
.include	Merges a file into the current file
.int	Defines storage for 32-bit integers
.long	Defines storage for 32-bit integers (same as .int)
.macro	Defines a macro
.octa	Defines storage for 64-bit integers
.quad	Same as .octa
.rept	Repeats a block of code multiple times
.set	Sets the value of a symbol to an expression
.short	Same as .hword
.single	Same as .float
.text	Generates following instructions into the code section
.word	Same as .int

Appendix D: ASCII Character Set

Here is the ASCII Character Set . The characters from 0 to 127 are standard. The characters from 128 to 255 are taken from code page 437, which is the character set of the original IBM PC.

Dec	Hex	Char	Description
0	00	NUL	Null
1	01	SOH	Start of header
2	02	STX	Start of text
3	03	ETX	End of text
4	04	EOT	End of transmission
5	05	ENQ	Enquiry
6	06	ACK	Acknowledge
7	07	BEL	Bell
8	08	BS	Backspace
9	09	HT	Horizontal tab
10	0A	LF	Line feed
11	0B	VT	Vertical tab
12	0C	FF	Form feed
13	0D	CR	Carriage return
14	0E	SO	Shift out
15	0F	SI	Shift in
16	10	DLE	Data link escape
17	11	DC1	Device control 1
18	12	DC2	Device control 2
19	13	DC3	Device control 3
20	14	DC4	Device control 4
21	15	NAK	Negative acknowledge
22	16	SYN	Synchronize
23	17	ETB	End of transmission block
24	18	CAN	Cancel
25	19	EM	End of medium
26	1A	SUB	Substitute
27	1B	ESC	Escape
28	1C	FS	File separator
29	1D	GS	Group separator
30	1E	RS	Record separator
31	1F	US	Unit separator
32	20	space	Space
33	21	!	Exclamation mark
34	22	"	Double quote
35	23	#	Number
36	24	$	Dollar sign
37	25	%	Percent
38	26	&	Ampersand
39	27	'	Single quote
40	28	(	Left parenthesis
41	29	)	Right parenthesis
42	2A	∗	Asterisk
43	2B	+	Plus
44	2C	,	Comma
45	2D	-	Minus
46	2E	.	Period
47	2F	/	Slash
48	30	0	Zero
49	31	1	One
50	32	2	Two
51	33	3	Three
52	34	4	Four
53	35	5	Five
54	36	6	Six
55	37	7	Seven
56	38	8	Eight
57	39	9	Nine
58	3A	:	Colon
59	3B	;	Semicolon
60	3C	<	Less than
61	3D	=	Equality sign
62	3E	>	Greater than
63	3F	?	Question mark
64	40	@	At sign
65	41	A	Capital A
66	42	B	Capital B
67	43	C	Capital C
68	44	D	Capital D
69	45	E	Capital E
70	46	F	Capital F
71	47	G	Capital G
72	48	H	Capital H
73	49	I	Capital I
74	4A	J	Capital J
75	4B	K	Capital K
76	4C	L	Capital L
77	4D	M	Capital M
78	4E	N	Capital N
79	4F	O	Capital O
80	50	P	Capital P
81	51	Q	Capital Q
82	52	R	Capital R
83	53	S	Capital S
84	54	T	Capital T
85	55	U	Capital U
86	56	V	Capital V
87	57	W	Capital W
88	58	X	Capital X
89	59	Y	Capital Y
90	5A	Z	Capital Z
91	5B	[	Left square bracket
92	5C		Backslash
93	5D	]	Right square bracket
94	5E	^	Caret/circumflex
95	5F	_	Underscore
96	60	`	Grave/accent
97	61	a	Small a
98	62	b	Small b
99	63	c	Small c
100	64	d	Small d
101	65	e	Small e
102	66	f	Small f
103	67	g	Small g
104	68	h	Small h
105	69	i	Small i
106	6A	j	Small j
107	6B	k	Small k
108	6C	l	Small l
109	6D	m	Small m
110	6E	n	Small n
111	6F	o	Small o
112	70	p	Small p
113	71	q	Small q
114	72	r	Small r
115	73	s	Small s
116	74	t	Small t
117	75	u	Small u
118	76	v	Small v
119	77	w	Small w
120	78	x	Small x
121	79	y	Small y
122	7A	z	Small z
123	7B	{	Left curly bracket
124	7C	\|	Vertical bar
125	7D	}	Right curly bracket
126	7E	~	Tilde
127	7F	DEL	Delete
128	80	Ç
129	81	ü
130	82	é
131	83	â
132	84	ä
133	85	à
134	86	å
135	87	ç
136	88	ê
137	89	ë
138	8A	è
139	8B	ï
140	8C	î
141	8D	ì
142	8E	Ä
143	8F	Å
144	90	É
145	91	æ
146	92	Æ
147	93	ô
148	94	ö
149	95	ò
150	96	û
151	97	ù
152	98	ÿ
153	99	Ö
154	9A	Ü
155	9B	¢
156	9C	£
157	9D	¥
158	9E	₧
159	9F	ƒ
160	A0	á
161	A1	í
162	A2	ó
163	A3	ú
164	A4	ñ
165	A5	Ñ
166	A6	ª
167	A7	°
168	A8	¿
169	A9	⌐
170	AA	¬
171	AB	½
172	AC	¼
173	AD	¡
174	AE	«
175	AF	»
176	B0
177	B1
178	B2
179	B3	│
180	B4	┤
181	B5	╡
182	B6	╢
183	B7	╖
184	B8	╕
185	B9	╣
186	BA	║
187	BB	╗
188	BC	╝
189	BD	╜
190	BE	╛
191	BF	┐
192	C0	└
193	C1	┴
194	C2	┬
195	C3	├
196	C4	─
197	C5	┼
198	C6	╞
199	C7	╟
200	C8	╚
201	C9	╔
202	CA	╩
203	CB	╦
204	CC	╠
205	CD	═
206	CE	╬
207	CF	╧
208	D0	╨
209	D1	╤
210	D2	╥
211	D3	╙
212	D4	╘
213	D5	╒
214	D6	╓
215	D7	╫
216	D8	╪
217	D9	┘
218	DA	┌
219	DB	█
220	DC	▄
221	DD	▌
222	DE	▐
223	DF	▀
224	E0	α
225	E1	ß
226	E2	Γ
227	E3	π
228	E4	Σ
229	E5	σ
230	E6	μ
231	E7	τ
232	E8	Φ
233	E9	Θ
234	EA	Ω
235	EB	δ
236	EC	∞
237	ED	φ
238	EE	ε
239	EF	∩
240	F0	≡
241	F1	±
242	F2	≥
243	F3	≤
244	F4	⌠
245	F5	⌡
246	F6	÷
247	F7	≈
248	F8	°
249	F9	∙
250	FA	·
251	FB	√
252	FC	n
253	FD	²
254	FE	■
255	FF

Answers to Exercises

This appendix has answers to selected exercises. For program code, check the online source code at the Apress GitHub site.

Chapter 1

1-1. 0100 1101 0010, 0x4d2

1-6. 8192 instructions, 1,336,934 instructions

Chapter 2

2-1. 177 (0xb1), 233 (0xe9)

2-2. -14, -125

2-3. 0x78563412

2-4. 0x118

2-5. 0x218

2-6. ADDS X1, X3, X5 // Lower order 64-bits

ADCS X6, X7, X8 // Middle order 64-bits

ADC X0, X2, X4 // Higher order 64-bits

2-7. SUBS X1, X3, X5 // Lower order 64-bits

SBC X0, X2, X4 // Higher order 64-bits

Chapter 5

5-2. TheLDR instruction either provides an offset to thePC directly from the address or creates the address in the code section using indirection from thePC to load this value.

Chapter 6

6-1. STP X0, X1, [SP, #16]!

STR X2, [SP, #16]!

LDR X2, [SP], #-16

LDP X0, X1, [SP], #-16

6-2. STP X20, X23, [SP, #-16]!

STP X27, LR, [SP, #-16]!

...

LDP X27, LR, [SP], #16

LDP X20, X23, [SP], #16

6-5. This allows clever register usage to avoid frequent pushing and popping to and from the stack.

Chapter 8

8-1. Get/set the IP address, and configure various TCP/IP network options like whether you want to receive broadcast packets.

8-2. The main constraint is usually making the electronics inexpensive, and this is done at the expense of ease of programming.

8-3. Any access to physical memory and hardware registers is dangerous and discouraged. Safe access is always through a device driver that enforces Linux security.

Chapter 14

14-1.W5 is still shifted for all non-lower-case letters; these need to be shifted back in an else clause adding complexity again.

14-3. If you use instructions added in a newer version of the ARM architecture, then you will get an illegal instruction exception if you run your program on any ARM processor using an earlier version of the architecture. Make sure you don’t limit your target audience by eliminating too many customers. On the pro side, you could get better performance and more compact code.

Index

Acorn computer

Address space layout randomization (ASLR)

ADRP instruction

Android application

building project

C/Assembly Language code

C++ wrapper

Gradle build system

Java/Kotlin programming languages

Kotlin program

programming framework

project creation

wrapper layer

xml screen definition

ARM processor

assembly instructions

SeeAssembly instructions

assembly language

building/executing

common convention

data

Gnome calculator

Hello World program

hexadecimal digits

Linux shell

MOV

numbers

RISC-V architecture

64 bits

specialty programs

starting point

text editor

ARM 64-bit instruction

ARM 64-bit NEON/FPU instructions

ASCII character set

asm statement

Assembly instructions

CPU register

data processing format

execution pipeline

format

Binary formats

addresses

floating point

integer

Bit clear (BIC) operation

Branch instruction

Buffer overflow hack

causes

C runtime’s strcpy

data leakages

DOS

PIE

protection technique

stack canaries

user interface module

CBNZ instruction

C functions

Assembly Language from python, calling

Assembly Language routines, calling

embedded Assembly code

print debug information

ADDS/ADC instructions

calling printf

C printf function

passing string

preserving state

runtime

C library’s strlen() function

CMP instruction

Complex instruction set computer (CISC)

Condition flags

C printf function

D, E

Data breaches

Denial of service (DoS)

Division

instructions

MUL/SMULH

FADDP instruction

Floating-point numbers

comparison routine

conversions

distance points

FCMP instructions

FCVT instructions

LDP instructions

NaNs

normalization

rounding error

single-/double-precision

Floating-point unit (FPU)

FMUL instruction

For loops

fpcomp routine

FPU registers

arithmetic operations

FMOV instructions

LDR/STR instructions

FSUB instruction

Function call protocol

GNC Compiler Collection (GCC)

ADD instruction

ADRP instruction

assembler

assembly code

CBNZ instruction

C compiler

mytoupper routine

General-purpose I/O (GPIO) pins

Assembly language

flashing LEDs

mapped memory

pin direction, setting

Raspberry Pi

root access

setting/clearing pins

table driven

Linux

memory locations

Raspberry Pi 1

registers, in bits

Broadcom

function select registers

set/clear pin

resisters

virtual memory addresses

Ghidra

GCC optimizer

high-level information

tstStr/outStr

upper C program

ghidraRun script

Gnome calculator

GNU Assembler directives

GNU Debugger (GDB)

goto statement

GPIO pins

Hacking

buffer overflow

SeeBuffer overflow hack

NULL (0) terminator

objdump output

RET instruction

stack, calltoupper function

stealing credit card numbers

If/then/else statement

imm26 operand

Integers to ASCII, conversion

compiling/execution, program

GNU assembler

printing, register

pseudo-code, register

STRB

iOS application

Assembly Language code, adding

bridge, creating

building/running, project

creating project

Swift code, adding

UI elements to main storyboard

Xcode

Java Native Interface (JNI)

Kotlin

SeeAndroid application

ld command

Linux/GCC code

GitHub repositories

64-bit Assembly Language source code

Linux kernel

copy page function

C runtime functions

loop unrolling

parallel processing

pldl1strm string

TST instruction

virtual memory manager

Linux openat service

Linux operating system services

calling convention

call numbers

definition

return code

structures

converting file to upper-case

build S files

case conversion program

error checking

file I/O routines

loop

openat service

function call wrappers

Little-endian

Logical operators

AND

EOR

ORR

MUL/SMULH

MUL instruction

Multiplication

examples instruction

functions

instruction

SMULL/UMULL

Multiply/accumulate operation

instruction, accumulate

matrix elements

matrix multiplication program

registers

SMADDL instruction

vector

National Security Agency (NSA)

NEON coprocessor

arithmetic operations

4D vector distance calculation

lanes

registers

3x3 matrix multiplication

Not a Number (NaN)

NULL (0) character

NVidia Jetson Nano

NZCV system register

objdump command line program

objdump/gdb

Optimizing code

avoiding expensive instruction

branch instruction

loop unrolling

macros

overheating

reducing data quantity

upper-case routine

SeeUpper-case routine

Out-of-order execution

OVerflow

P, Q

pldl1strm string

Position-independent executables (PIE)

Program counter (PC)

Pulse-position modulation (PPM)

Pulse width modulation (PWM)

Raspberry Pi 4

Reduced instruction set computer (RISC)

Shared library

SIMD instructions

Single board computer (SBC)

single instruction multiple data (SIMD)

SMADDL instruction

SMULL/UMULL

Spaghetti code

Static library

Store byte (STRB) instruction

SUB instruction

Swift

SeeiOS application

System on a chip (SoC)

tstStr/outStr

Unconditional branch

Upper-case routine

BIC instruction

CMHI

conditional instruction

CSEL instruction

Neon Coprocessor

NULL terminator

problem domain

pseudo-code

range comparisons

string processing

Vector floating-point (VFP)

W, X, Y, Z

While loops

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