Most synthesizers employ “phase-locking” to achieve high frequency accuracy. We therefore dedicate this chapter to a study of PLLs. While a detailed treatment of PLLs would consume an entire book, our objective here is to develop enough foundation to allow the analysis and design of RF synthesizers. The outline of the chapter is shown below. The reader is encouraged to review the mathematical model of VCOs described in Chapter 8.

In its simplest form, a PLL is a negative feedback loop consisting of a VCO and a “phase detector” (PD). We therefore first define what a PD is and subsequently construct the loop.

A PD is a circuit that senses two periodic inputs and produces an output whose average value is proportional to the difference between the *phases* of the inputs. Shown in Fig. 9.1, the input/output characteristic of the PD is ideally a straight line, with a slope called the “gain” and denoted by *K _{PD}*. For an output voltage quantity,

How is the phase detector implemented? We seek a circuit whose average output is proportional to the input phase difference. For example, an exclusive-OR (XOR) gate can serve this purpose. As shown in Fig. 9.3, the XOR gate generates pulses whose width is equal to Δ*φ*. In this case, the circuit produces pulses at both the rising edge and the falling edge of the inputs.

Recall from the mathematical model of VCOs in Chapter 8 that the output phase of a VCO cannot change instantaneously as it requires an ideal impulse on the control voltage. Now, suppose a VCO oscillates at the same frequency as an ideal reference but with a finite phase error (Fig. 9.6). We wish to null this error by adjusting the phase of the VCO. Noting that the control voltage is the only input and that the phase does not change instantaneously, we recognize that we must (1) change the *frequency* of the VCO, (2) allow the VCO to accumulate phase faster (or more slowly) than the reference so that the phase error vanishes, and (3) change the frequency back to its initial value. As shown in Fig. 9.6, *V _{cont}* is stepped at

How do we determine the time at which the phase error in Fig. 9.6 reaches zero? A phase detector comparing the VCO phase and the reference phase can serve this purpose, yielding the negative feedback loop shown in Fig. 9.7(a). If the “loop gain” is sufficiently high, the circuit minimizes the input error. Note that the loop only “understands” phase quantities (rather than voltage or current quantities) because the input “subtractor” (the PD) operates with phases.

The circuit of Fig. 9.7(a) suffers from a critical issue. The phase detector produces repetitive pulses at its output, modulating the VCO frequency and generating large sidebands. We therefore interpose a low-pass filter (called the “loop filter”) between the PD and the VCO so as to suppress these pulses [Fig. 9.7(b)].

We call the circuit of Fig. 9.7(b) a phase-locked loop and will study its behavior in great detail. But it is helpful to decipher the expressions “phase-locked” or “phase locking.” First, consider the more familiar voltage-domain circuit shown in Fig. 9.8(a). If the open-loop gain of the unity-gain buffer is relatively large, then the output voltage “tracks” the input voltage. Similarly, the PLL of Fig. 9.8(b) ensures that *φ _{out}*(

An important and unique consequence of phase locking is that the input and output frequencies of the PLL are *exactly* equal. This can be seen by writing

and hence

This attribute proves critical to the operation of phase-locked systems, including RF synthesizers.

Can two periodic waveforms have a constant phase difference but different frequencies? If we define the phase difference as the time elapsed between consecutive zero crossings, we observe that this is not possible. That is, if the phases are “locked,” then the frequencies are naturally equal.

Figure 9.10(a) shows a PLL implementation using an XOR gate and a top-biased LC VCO (Chapter 8). The low-pass filter is realized by means of *R*_{1} and *C*_{1}. If the loop is locked, the input and output frequencies are equal, the PD generates repetitive pulses, the loop filter extracts the average level, and the VCO senses this level so as to operate at the required frequency. Note that the signal of interest changes dimension as we “walk” around the loop: the PD input is a phase quantity, the PD output and the LPF output are voltage quantities, and the VCO output is a phase quantity. By contrast, the unit-gain buffer of Fig. 9.8(a) contains signals in only the voltage and current domains.

Following our above study, we may have many questions in regards to PLLs: (1) how does a PLL reach the locked condition? (2) does a PLL always lock? (3) how do we compute the voltages and phases around the loop in the locked condition? (4) how does a PLL respond to a change at its input? In this section, we address some of these questions.

We begin our analysis by examining the signals at various nodes in the circuit of Fig. 9.10(a). Figure 9.10(b) shows the waveforms, assuming the loop is locked. The input and output have equal frequencies but a finite phase difference, Δ*φ*_{1}, and the PD generates pulses whose width is equal to Δ*φ*_{1}. These pulses are low-pass filtered to produce the dc voltage that enables the VCO to operate at a frequency equal to the input frequency, *ω*_{1}. The residual disturbance on the control line is called the “ripple.” A lower LPF corner frequency further attenuates the ripple, but at the cost of other performance parameters. We return to this point later.

With the VCO and PD characteristics known, it is possible to compute the control voltage of the VCO and the phase error. As illustrated in Fig. 9.10(c), the VCO operates at *ω*_{1} if *V _{cont}* =

Let us now study, qualitatively, the response of a PLL that is locked for *t < t*_{0} and experiences a small, positive frequency step, Δ*ω*, at the input at *t* = *t*_{0} (Fig. 9.12). We expect that the loop reaches the final values stipulated in Example 9.6, but we wish to examine the transient behavior. Since the input frequency, *ω _{in}*, is momentarily greater than the output frequency,

The foregoing study leads to two important points. First, among various nodes in a PLL, the control voltage provides the most straightforward representation of the transient response. By contrast, the VCO or PD outputs do not readily reveal the loop’s settling behavior. Second, the loop locks only after *two* conditions are satisfied: (1) *ω _{out}* becomes equal to

If the input/output phase error of a PLL varies with time, we say the loop is “unlocked,” an undesirable state because the output does not track the input. For example, if at the startup, the VCO frequency is far from the input frequency, the loop may never lock. While the behavior of a PLL in the unlocked state is not important per se, whether and how it acquires lock are both critical issues. In our development of PLLs in this section, we devise a method to guarantee lock.

The transient response of PLLs is generally a nonlinear phenomenon that cannot be formulated easily. Nevertheless, a linear approximation can be used to gain intuition and understand trade-offs in PLL design. We begin our analysis by obtaining the transfer function. Next, we examine the transfer function to predict the time-domain behavior.

It is instructive to ponder the meaning of the term “transfer function” in a phase-locked system. In the more familiar voltage-domain circuits, such as the unity-gain buffer of Fig. 9.15(a), the transfer function signifies how a sinusoidal input *voltage* propagates to the output.^{1} For example, a slow input sinusoid experiences little attenuation, whereas a fast sinusoid emerges with a small *voltage* amplitude. How do we extend these concepts to the *phase* domain? The transfer function of a PLL must reveal how a slow or a fast change in the input (excess) *phase* propagates to the output. Figure 9.15(b) illustrates examples of slow and fast phase change. From Example 9.7, we predict that the PLL’s low-pass behavior “attenuates” the phase excursions if the input phase varies fast. That is, the output phase tracks the input phase closely only for slow phase variations.

Let us now construct a “phase-domain model” for the PLL. The phase detector simply *subtracts* the output phase from the input phase and scales the result by a factor of *K _{PD}* so as to generate an average

Since the open-loop transfer function contains one pole at the origin (due to the VCO) (i.e., one ideal integrator), this system is called a “type-I PLL.” As expected, for slow input phase variations (*s* ≈ 0), *H*(*s*) ≈ 1, i.e., the output phase tracks the input phase.

The second-order transfer function given by Eq. (9.6) can have an overdamped, critically-damped, or underdamped behavior. To derive the corresponding conditions, we express the denominator in the familiar control theory form, , where *ζ* is the “damping factor” and *ω _{n}* the “natural frequency.” Thus,

where

and *ω _{LPF}* = 1/(

Since phase and frequency are related by a linear, time-invariant operation, Eq. (9.6) also applies to frequency quantities. For example, if the input frequency varies slowly, the output frequency tracks it closely.

An extremely useful property of PLLs is frequency multiplication, i.e., the generation of an output frequency that is a multiple of the input frequency. How can a PLL “amplify” a frequency? We revisit the more familiar voltage buffer of Fig. 9.8(a) and note that it can provide amplification if its output is *divided* (attenuated) before returning to the input [Fig. 9.18(a)]. Similarly, the output frequency of a PLL can be divided and then fed back [Fig. 9.18(b)]. The ÷*M* circuit is a counter that generates one output pulse for every *M* input pulses (Chapter 10). From another perspective, in the locked condition, *ω _{F}* =

The PLL of Fig. 9.18(b) can also *synthesize* frequencies: if the divider modulus changes by 1, the output frequency changes by *ω _{in}*. This point forms the basis for the frequency synthesizers studied in Chapter 10.

How does the presence of a feedback divider affect the loop dynamics? In analogy with the op amp circuit of Fig. 9.18(a), we surmise that the weaker feedback leads to a slower response and a larger phase error. We study the response in Problem 9.7 and the phase error in the following example.

Modern RF synthesizers rarely employ the simple PLL studied here. This is for two reasons. First, Eq. (9.8) imposes a tight relation between the loop stability (*ζ*) and the corner frequency of the low-pass filter. Recall from Example 9.12 that the ripple on the control line modulates the VCO frequency and must be suppressed by choosing a *low* value for *ω _{LPF}*. But, a small

Second, the simple PLL suffers from a limited “acquisition range,” e.g., if the VCO frequency and the input frequency are very different at the startup, the loop may never “acquire” lock.^{2} Without delving into the process of lock acquisition, we wish to avoid this issue completely so that the PLL always locks.

While not directly relevant to RF synthesizers, the finite static phase error and its variation with the input frequency [Eq. (9.5)] also prove undesirable in some applications. This error can be driven to zero by means of an infinite loop gain—as explained in the next section.

We continue our development by first addressing the second issue mentioned above, namely, the problem of limited acquisition range. While beyond the scope of this book, this limitation arises because *phase* detectors produce little information if they sense *unequal frequencies* at their inputs. We therefore postulate that the acquisition range can be widened if a *frequency* detector is added to the loop. Of course, we note from Example 9.5 that an FD by itself does not suffice and the loop must eventually lock the phases. Thus, it is desirable to seek a circuit that operates as an FD if its input frequencies are not equal and as a PD if they are. Such a circuit is called a “phase/frequency detector” (PFD).

Figure 9.20 conceptually shows the operation of a PFD. The circuit produces *two* outputs, *Q _{A}* and

To arrive at a circuit implementation of the above idea, we surmise that at least three logical states are necessary: *Q _{A}* =

Figure 9.22 illustrates a logical implementation of the above state machine. The circuit consists of two edge-triggered, resettable D flipflops with their D inputs tied to logical ONE. Signals A and B act as clock inputs of DFF* _{A}* and DFF

What is the effect of reset pulses on *Q _{B}* in Fig. 9.22? Since only the average value of

Each resettable D-flipflop in Fig. 9.22 can be implemented as shown in Fig. 9.23. (Note that no D input is available.) This circuit suffers from a limited speed—a minor issue because in frequency-multiplying PLLs, *ω _{in}* is typically much lower than

The use of a PFD in a phase-locked loop resolves the issue of the limited acquisition range. Shown in Fig. 9.24 is a conceptual realization employing a PFD. The dc content of *Q _{A}* −

We must next address the trade-off between the damping factor and the corner frequency of the loop filter [Eq. (9.8)]. This is accomplished by introducing a “charge pump” (CP) in the loop.

A charge pump sinks or sources current for a limited period of time. Depicted in Fig. 9.25 is an example, where switches *S*_{1} and *S*_{2} are controlled by the inputs “Up” and “Down,” respectively. A pulse of width Δ*T* on Up turns *S*_{1} on for Δ*T* seconds, allowing *I*_{1} to charge *C*_{1}. Consequently, *V _{out}* goes

Let us precede the circuit of Fig. 9.25 with a PFD (Fig. 9.26). We note that if, for example, *A* leads *B*, then *Q _{A}* produces pulses and

We now construct a PLL using the circuit of Fig. 9.26. Illustrated in Fig. 9.27, such a loop ideally forces the input phase error to zero because, as mentioned in the previous section, a finite error would lead to an *unbounded* value for *V _{cont}*. To quantify the behavior of this arrangement, we wish to derive the transfer function from

How do we compute this transfer function? We can apply a (phase) step at the input, derive the time-domain output, differentiate it, and compute its Laplace transform [2]. A phase step simply means a displacement of the zero crossings. As shown in Fig. 9.28, a phase step of Δ*φ*_{0} at one of the inputs repetitively turns *S*_{1} or *S*_{2} on, monotonically changing the output voltage.

This behavior is similar to that of an integrator. Unfortunately, however, this system is nonlinear: if Δ*φ*_{0} is doubled, not every point on the “charge-and-hold” output waveform, *V _{out}*, is doubled (why?). Fortunately, we can approximate this waveform by a ramp—as if the charge pump

where [Δ*φ*_{0}/(2*π*)]*T _{in}* denotes the phase difference in seconds and

Differentiating Eq. (9.13) with respect to time, normalizing to Δ*φ*_{0}, and taking the Laplace transform, we have

As predicted earlier, the PFD/CP/*C*_{1} cascade operates as an integrator.

From Eq. (9.14), the closed-loop transfer function of the PLL shown in Fig. 9.27 can be expressed as

This arrangement is called a type-II PLL because its open-loop transfer function contains two poles at the origin (i.e., two ideal integrators).

Equation (9.16) reveals two poles on the *jω* axis, indicating an oscillatory system. From Example 8.5 for two ideal (lossless) integrators in a loop, we note that the instability is to be expected. We thus postulate that if one of the integrators becomes *lossy*, the system can be stabilized. This can be accomplished by inserting a resistor in series with *C*_{1} (Fig. 9.30). The resulting circuit is called a “charge-pump PLL” (CPPLL).

We repeat the analysis illustrated in Fig. 9.28(a) to obtain the new transfer function. As shown in Fig. 9.31, when *S*_{1} or *S*_{2} turns on, *V _{cont}* jumps by an amount equal to

The transfer function of the PFD/CP/filter cascade is therefore given by

Equation (9.18) allows us to express the closed-loop transfer function of the PLL shown in Fig. 9.30 as

As with the type-I PLL in Section 9.2, we write the denominator as and obtain

Interestingly, as *C*_{1} increases (so as to reduce the ripple on the control voltage), so does *ζ*—a trend opposite of that observed in type-I PLLs. We have thus removed the trade-off between stability and ripple amplitude. The closed-loop poles are given by

Equation (9.19) also reveals a closed-loop zero at −*ω _{n}*/(2

The transfer function expressed by Eq. (9.18) offers another perspective on stabilization (frequency compensation) of a two-integrator loop. Writing (9.18) as

we can say that a real left-half-plane zero, *ω _{z}* = −1/(

The behavior illustrated in Fig. 9.32 also explains the dependence of *ζ* upon *K _{VCO}* [Eq. (9.20)]. As

Suppose during the lock transient, the phase difference is not zero at some point in time. Then, a current of *I _{p}* flows through

The closed-loop transfer function of the PLL, as expressed by Eq. (9.19), can be used to predict the transient response.

The inverse Laplace transform of Eq. (9.19) yields the output frequency, Δ*ω _{out}*, as a function of time for a frequency step at the input, Δ

Since the response decays exponentially, we may call 1/(*ζ ω _{n}*) the “time constant” of the loop, but, as explained below, that is not an accurate statement. Note that (9.24) can be simplified if we assume (i.e.,

From (9.20) and (9.21), the time constant of the loop is expressed as

This quantity (or its inverse) serves as a measure of the settling speed of the loop if *ζ* is in the vicinity of unity.

What happens as *ζ* well exceeds unity? If *ζ*^{2} 1, then , and Eq. (9.22) reduces to

Note that *ω _{p}*

Charge-pump PLLs are inherently discrete-time (DT) systems because the charge pump turns off for part of the period and breaks the loop. In the derivation of the CPPLL transfer function, we have made two continuous-time approximations: the charge-and-hold waveform in Fig. 9.28 is represented by a ramp, and the series of pulses in Fig. 9.31(b) is modeled by a step. These approximations hold only if the time “granularities” inherent in the original waveforms are very small with respect to the time scales of interest. To better understand this point, let us consider the *inverse* problem, namely, the approximation of a CT waveform by a DT counterpart. As illustrated in Fig. 9.35, the approximation holds well if the CT waveform changes little from one clock cycle to the next, but loses its accuracy if the CT waveform experiences fast changes.

These observations reveal that CPPLLs obey the transfer function of Eq. (9.19) only if their internal states (the control voltage and the VCO phase) do not change rapidly from one input cycle to the next. This occurs if the loop time constant is much longer than the input period. Indeed, this point plays an important role in the design procedure of PLLs (Section 9.7). Discrete-time analyses of CPPLLs can be found in [3], but in practice, loops that are not sufficiently slow exhibit an underdamped behavior or may simply not lock. The CT approximation therefore proves adequate in most practical cases.

As explained in Section 9.2.5 and illustrated in Fig. 9.18(b), a PLL containing a divider of modulus *M* in its feedback path multiplies the input frequency by a factor of *M*. We wish to formulate the dynamics of a type-II frequency-multiplying PLL. We simply consider the product of (9.23) and *K _{VCO}*/

The denominator is similar to that of Eq. (9.19), except that *K _{VCO}* is divided by

As can be seen in Fig. 9.32, the division of *K _{VCO}* by

It is important to recognize that the above example applies to only *slow* phase or frequency modulation at the PLL input such that the output tracks the variation faithfully. For faster modulations, the output phase is an attenuated version of the input and subjected to Eq. (9.32).

The loop filter consisting of *R*_{1} and *C*_{1} in Fig. 9.30 proves inadequate because, even in the locked condition, it does not suppress the ripple sufficiently. For example, suppose, in the locked condition, the Up and Down pulses arrive every *T _{in}* seconds with a small skew due to propagation mismatches within the PFD (Fig. 9.37). Consequently, one switch turns on earlier than the other, allowing its corresponding current source to flow through

A common approach to lowering the ripple is to tie a capacitor directly from the control line to ground. Illustrated in Fig. 9.38, the idea is to provide a low-impedance path for the unwanted charge pump output. That is, a current pulse of width Δ*T* produced by the CP initially flows through *C*_{2}, leading to a change of (*I _{p}*/

How large can *C*_{2} be? The current-to-voltage conversion impedance provided by the loop filter has changed from *R*_{1} + (*C*_{1}*s*)^{−1} to [*R*_{1} + (*C*_{1}*s*)^{−1}]||(*C*_{2}*s*)^{−1}, presenting an additional pole at (*R*_{1}*C _{eq}*)

where *ζ* is chosen equal to to maximize PM. For example, if *C*_{2} = 0.2*C*_{1}, then (*R*_{1}*C _{eq}*)

Unfortunately, with *C*_{2} present, *R*_{1} cannot be arbitrarily large. In fact, if *R*_{1} is so large that the series combination of *R*_{1} and *C*_{1} is overwhelmed by *C*_{2}, then the PLL reduces to the system shown in Fig. 9.27 and characterized by Eq. (9.16). An upper bound derived for *R*_{1} in Appendix I is as follows:

Another loop filter that can reduce the ripple is shown in Fig. 9.40. Here, the ripple at node *X* may be large, but it is suppressed as it travels through the low-pass filter consisting of *R*_{2} and *C*_{2}. If |*R*_{2} + (*C*_{2}*s*)^{−1}| |*R*_{1} + (*C*_{1}*s*)^{−1}| at the frequencies of interest, then the additional pole is given by (*R*_{2}*C*_{2})^{−1}. Following the analysis in Appendix I, the reader can prove that

Thus, (*R*_{2}*C*_{2})^{−1} must remain 5 to 10 times higher than *ω _{z}* so as to yield a reasonable phase margin.

Our study of PLLs in the previous sections has provided a detailed understanding of their basic operation but has neglected various imperfections. In this section, we analyze the effect of nonidealities in the PFD/CP cascade. We also present circuit techniques that combat some of these effects.

The Up and Down pulses produced by the PFD may arrive at different times. As explained in Section 9.3.7 and illustrated in Fig. 9.37, an arrival time mismatch of Δ*T* translates to two current pulses of width Δ*T*, height *I _{p}*, and opposite polarities that are injected by the charge pump at each phase comparison instant. Owing to the short time scales associated with these pulses, only

The reader may wonder how the Up and Down pulses may arrive at different times. In addition to random propagation time mismatches with the PFD, the interface between the PFD and the charge pump may also introduce a systematic skew. For example, consider the arrangement shown in Fig. 9.43(a), where the charge pump is implemented by *M*_{1}-*M*_{4}. Since *S*_{1} is realized by a PMOS device, the corresponding PFD output, *Q _{A}*, must be inverted so that

Does perfect alignment of Up and Down pulses in Fig. 9.43(b) suffice? Not necessarily; the *currents* produced by the PMOS and NMOS sections of the charge pump may still suffer from skews. This is because the time instants at which *M*_{1} and *M*_{2} turn on and off may not be aligned. In other words, the quantity of interest is in fact the skew between the Up and Down *current* waveforms, *I _{D}*

Recall from Chapter 8 that we wish to maximize the tuning range of VCOs while maintaining a moderate value for *K _{VCO}*. It is therefore desirable to design the charge pump so that it produces minimum and maximum voltages as close to the supply rails as possible. In the simple charge pump of Fig. 9.43(b), each current source requires a minimum drain-source voltage and each switch sustains a voltage drop. We say the output compliance is equal to

We now turn our attention to the imperfections introduced by the charge pump. We assume the simple CP implementation of Fig. 9.43(b) for now. The switching transistors, *M*_{1} and *M*_{2}, carry a certain amount of mobile charge in their inversion layers when they are on. This charge is expressed as

As the switches turn on, they absorb this charge and as they turn off, they dispel this charge, in both cases through their source and drain terminals. Since *M*_{1} and *M*_{2} generally have different dimensions and overdrive voltages, they do not cancel each other’s charge absorption or injection, thereby disturbing the control voltage at both turn-on and turn-off points [Fig. 9.45(a)]. We hereafter refer to this effect as charge injection and consider it when switches turn off, bearing in mind that charge absorption plays a similar role.

Another effect relates to the gate-drain overlap capacitance of the switches. As shown in Fig. 9.45(b), the Up and Down pulses couple through *C _{GD}*

After the charge pump turns off, charge sharing between *C*_{2} and *C*_{1} reduces this voltage to

A number of techniques can reduce the effect of charge injection and clock feedthrough. Depicted in Fig. 9.46(a), one approach places the switches near the supply rails [4] so that the feedthrough is somewhat attenuated by the total capacitance seen from *X* and *Y* to ground before disturbing the source voltage of *M*_{3} and *M*_{4}. Charge injection, however, persists because *M*_{3} and *M*_{4} must still dispel their charge when they turn off. This approach is called “source switching” because the switches are tied to the sources of *M*_{3} and *M*_{4}.

Another method incorporates “dummy” switches to suppress both effects [5]. Illustrated in Fig. 9.46(b), the idea is to add transistors configured as capacitors and driven by the complements of Up and Down pulses. The reader can prove that, if *W*_{5} = 0.5*W*_{1} and *W*_{6} = 0.5*W*_{2}, then the clock feedthrough of each switch is cancelled. The charge injection is also cancelled if, additionally, the charge of each switch splits equally between its source and drain terminals. Since this condition is difficult to guarantee, charge injection may be only partially removed.

Figure 9.46(c) shows another arrangement, where the Up and Down currents are created by differential pairs. If *V _{b}*

The two current sources in a charge pump inevitably suffer from random mismatches. Figure 9.47(a) shows an example, where *I _{REF}* is copied onto

where *I _{p}* denotes the mean current. Thus,

The ripple amplitude is equal to Δ*T* · *I _{p}*/

How does the ripple due to Up and Down skew compare with that due to current mismatch? As derived earlier, the former has an amplitude equal to Δ*T* · *I _{p}*/

The random mismatch between the Up and Down currents can be reduced by enlarging the current-source transistors. Recall from analog design that as the device area increases, mismatches experience greater spatial averaging. For example, doubling the area of a transistor—equivalent to placing two transistors in parallel—reduces the threshold voltage mismatch by a factor of . However, larger transistors suffer from a greater amount of charge injection and clock feedthrough.

The Up and Down currents also incur mismatch due to channel-length modulation of the current sources; i.e., different output voltages inevitably lead to opposite changes in the drain-source voltages of the current sources, thereby creating a larger mismatch.

In order to quantify the effect of channel-length modulation, we test the charge pump as shown in Fig. 9.48(a). Both switches are on and the output voltage is swept across the compliance range. In the ideal case, *I _{X}* = 0 for the entire range, but in reality,

While the phase offset or its variation is not critical in RF synthesis, the resulting ripple is. That is, channel-length modulation must be small enough to produce a tolerable ripple amplitude ( = *T _{res}*Δ

It is possible to raise the output impedance of the current sources through the use of “regulated cascodes” [6]. Figure 9.50(a) illustrates such a structure, where an “auxiliary amplifier,” *A*_{0}, senses *V _{P}* and adjusts the gate voltage of

This technique is attractive because it raises the output impedance without consuming additional voltage headroom.

Figure 9.50(b) shows a charge pump employing regulated cascodes. Note that the switches are placed in series with the sources of *M*_{3} and *M*_{4}. If the gain of the auxiliary amplifiers is sufficiently large, the mismatch between the Up and Down currents remains small even if *M*_{3} and *M*_{4} enter the triode region by a small amount.

The principal drawback of this approach stems from the finite response of the auxiliary amplifiers. When *M*_{1} and *M*_{2} turn off, the feedback loops around *M*_{3} and *M*_{4} are broken, allowing the outputs of *A*_{1} and *A*_{2} to approach the supply rails. In the next phase comparison instant, these outputs must return and settle to their proper values—a transient substantially longer than the width of the Up and Down pulses (≈ five gate delays). In other words, *A*_{1} and *A*_{2} may simply not have enough time to settle and boost the output impedance according to Eq. (9.49).

Figure 9.51 depicts another technique [7]. Here, *M*_{1}-*M*_{4} constitute the main charge pump and *M*_{5}-*M*_{8} a replica branch. Note that the bias current of *M _{REF}* is copied onto

A key advantage of this topology over the charge pump in Fig. 9.50(b) is that *A*_{0} need not provide a fast response. This is because, when *M*_{1} and *M*_{2} turn off, the feedback loop consisting of *A*_{0} and *M*_{5} remains intact, thus experiencing a negligible transient.

The performance of the circuit is still limited by random mismatches between the NMOS current sources and between the PMOS current sources. Also, the op amp must operate properly with a nearly rail-to-rail input common-mode range because *V _{cont}* must come as close to the rails as possible.

Figure 9.52(a) shows another example using a servo amplifier [8]. In a manner similar to Fig. 9.51, *A*_{0} forces *V _{X}* close to

The gate switching operation nonetheless exacerbates the problem of Up and Down arrival mismatch. To understand this issue, let us consider the realization shown in Fig. 9.52(b), where the Up and Down pulses have a finite risetime and falltime. We observe that *M*_{1} turns on or off as the Up pulse reaches *V _{DD}* − |

Depicted in Fig. 9.53 is another example that cancels both random and deterministic mismatches between the Up and Down currents [9]. In addition to the main output branch consisting of *I*_{1}, *M*_{1}, *M*_{2}, and *I*_{2}, the circuit incorporates switches *M*_{5} and *M*_{6}, an integrating capacitor, *C _{X}*, and an op amp,

In our study of oscillators in Chapter 8, we analyzed the mechanism by which device noise translates to phase noise. When an oscillator is phase-locked, its output phase noise profile changes. Also, the reference input to the PLL contains phase noise, corrupting the output. We investigate these effects for type-II PLLs.

Our understanding of phase-locking suggests that a PLL continually attempts to make the output phase track the input phase. Thus, if the reference input has no phase noise, the PLL attempts to reduce the output phase noise to zero even if the VCO exhibits its own phase noise. From another perspective, as the VCO phase noise accumulates to an appreciable phase error, the loop detects this error and commands the charge pump to briefly turn on and correct it. (If the VCO experienced no phase drift, it would continue to operate at a certain frequency and phase even if the loop were disabled.)

In order to formulate the PLL output noise due to the VCO phase noise, we first derive the transfer function from the VCO phase to the PLL output phase. To this end, we construct the linear phase model of Fig. 9.55(a), where the excess phase of the input is set to zero to signify a “clean” reference. Beginning from the output, we have

Using the *ζ* and *ω _{n}* expressions developed in Section 9.3.3, we obtain

As expected, this transfer function has the same poles as Eq. (9.19), but it also contains two zeros at the origin, exhibiting a *high-pass* behavior [Fig. 9.55(b)].

This result indicates that the PLL suppresses *slow* variations in the phase of the VCO [small *ω* in Fig. 9.55(b)] but cannot provide much correction for fast variations. In lock, the VCO phase is compared against the input phase and the corresponding error is converted to current, injected into the loop filter to generate a voltage, and finally applied to the VCO so as to counteract its phase variation. Since both the charge pump and the VCO have nearly infinite gain for slowly-varying signals, the negative feedback remains strong for slow phase variations. For fast variations, on the other hand, the loop gain falls and the feedback provides less correction.

From another perspective, the system of Fig. 9.55(a) can be redrawn as shown in Fig. 9.56(a) and hence Fig. 9.56(b). The system *G*(*s*) is equivalent to a cascade of two ideal integrators, thus creating a “virtual ground” at its input (at *φ _{out}*). If

The PLL output phase noise due to the VCO is equal to the magnitude squared of Eq. (9.51) multiplied by the VCO phase noise. As observed in Chapter 8, oscillator phase noise can be expressed as (*α*/*ω*^{3} + *β*/*ω*^{2}), where *α* and *β* encapsulate various factors such as the noise injected by devices and the *Q*, and *ω* is our notation for the offset frequency (Δ*ω* in Chapter 8). Thus,

We say the VCO phase noise is “shaped” by the transfer function.

It is instructive to study the above phase noise behavior for low and high offset frequencies. At low offset frequencies (slow VCO phase variations), the flicker-noise-induced term is dominant:

In fact, if *ω* is sufficiently small, . That is, the phase noise power rises linearly with frequency. The reader can show that Eq. (9.53) reaches a maximum of at if *ζ* = 1. Figure 9.60(a) plots this behavior, indicating that the phase-locked VCO exhibits 12 dB less phase noise at . We recognize that (9.53) approaches *α*/*ω*^{3} at large *ω* because (9.51) tends to unity.

At high offset frequencies, the white-noise-induced term in (9.52) dominates, yielding

Similarly, this function approaches *β*/*ω*^{2} at sufficiently large *ω*. The reader can show that (9.54) reaches a maximum of at *ω* = *ω _{n}* if

Figure 9.61 summarizes our findings. In addition to the free-running VCO phase noise, the curves corresponding to *α*/*ω*^{3} and *β*/*ω*^{2} are also drawn. The overall PLL output phase noise is equal to the sum of *S _{A}* and

The reference phase noise is simply shaped by the input/output transfer function of the PLL. From Eq. (9.19), we write

where *S _{REF}* denotes the reference phase noise. Note that crystal oscillators providing the reference typically display a

We must now make two important observations. First, PLLs performing frequency multiplication “amplify” the low-frequency reference phase noise proportionally. This can be seen from (9.35) and Example 9.19. That is, *S _{out}* =

The phase noise multiplication can also be analyzed in the time domain: if the input edges are (slowly) displaced by Δ*T* seconds (2*π*Δ*T*/*T _{REF}* radians), then the output edges are also displaced by Δ

Second, the total phase noise at the output (the area under the phase noise profile in Fig. 9.63) increases with the loop bandwidth—a trend opposite of that observed for the VCO phase noise. In other words, the choice of the loop bandwidth entails a trade-off between the reference and the VCO phase noise contributions.

As seen in this chapter, the bandwidth of the PLL plays a critical role in the overall performance. Our observations thus far indicate that (1) the settling behavior can be roughly characterized by a time constant in the range of 1/(*ζ ω _{n}*) and 1/(2

But how should the loop bandwidth be defined? We can simply compute the −3-dB bandwidth by equating the magnitude squared of Eq. (9.19) to 1/2:

It follows that

For example, if *ζ* lies in the range of and 1, then *ω*_{−3dB} is between 2.1*ω _{n}* and 2.5

In the design of PLLs, we impose a loop time constant much longer than the input period, *T _{in}*, or a loop bandwidth much smaller than the input frequency to ensure a well-behaved settling. These two constraints, however, are not exactly equivalent. For example, if

whereas the latter yields

Equation (9.59) is a stronger condition and is usually enforced. For higher values of *ζ*, the loop bandwidth approaches 2*ζω _{n}* and is set to approximately one-tenth of

The design of PLLs begins with the building blocks: the VCO is designed according to the criteria and the procedure described in Chapter 8; the feedback divider is designed to provide the required divide ratio and operate at the maximum VCO frequency (Chapter 10); the PFD is designed with careful attention to the matching of the Up and Down pulses; and the charge pump is designed for a wide output voltage range, minimal channel-length modulation, etc. In the next step, a loop filter must be chosen and the building blocks must be assembled so as to form the PLL.

In order to arrive at a well-behaved PLL design, we must properly select the charge pump current and the loop filter components. We begin with two governing equations:

and choose

Since *K _{VCO}* is known from the design of the VCO, we now have two equations and three unknowns, namely,

In this appendix, we derive the phase margin of second-order and third-order type-II PLLs. Consider the open-loop magnitude and phase response of a second-order PLL as shown in Fig. 9.66. The magnitude falls with a slope of −40 dB/dec up to the zero frequency, *ω _{z}* = (

Using Eqs. (9.20) and (9.21) as short-hand notations and noting that , we have

and

The phase margin is therefore given by

For example, if *ζ* = 1, then *PM* = 76° and *ω _{u}*/

Let us now consider the third-order loop of Fig. 9.38. The reader can show that the PFD/CP/filter cascade provides the following transfer function:

where *C _{eq}* =

How should *ω _{p}*

The phase margin can now be calculated as

In most cases of practical interest, 32*ζ*^{2} 1 and hence

Note that this result is valid only if *ζ* ≥ 1 and *ω _{p}*

An alternative approach seeks that value of *ω _{u}* which maximizes the PM in Eq. (9.78) [10]. Differentiation yields

and

The corresponding *ζ* can be obtained by differentiating Eq. (9.80):

approximately equal to 0.783 for *C*_{1} = 5*C*_{2}.

The foregoing study also reveals another important limitation in the choice of the loop parameters: with *C*_{2} present, *R*_{1} cannot be arbitrarily large. After all, if *R*_{1} → ∞, the series combination of *R*_{1} and *C*_{1} vanishes, leaving only *C*_{2} and hence only two ideal integrators in the loop. To determine an upper bound on *R*_{1}, we note that, as *R*_{1} increases, *ω _{p}*

It follows that

and hence

We note that, if *ζ* ≈ 1 and *C*_{2} ≈ 0.2*C*_{1}, this condition is satisfied.

[1] F. M. Gardner, *Phaselock Techniques*, Second Edition, New York: Wiley & Sons, 1979.

[2] B. Razavi, *Design of Analog CMOS Integrated Circuits,* Boston: McGraw-Hill, 2001.

[3] J. P. Hein and J. W. Scott, “z-Domain Model for Discrete-Time PLLs,” *IEEE Trans. Circuits and Systems,* vol. 35, pp. 1393–1400, Nov. 1988.

[4] J. Alvarez et al., “A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors,” *IEEE J. of Solid-State Circuits,* vol. 30, pp. 383–391, April 1995.

[5] J. M. Ingino and V. R. von Kaenel, “A 4-GHz Clock System for a High-Performance System-on-a-Chip Design,” *IEEE J. of Solid-State Circuits,* vol. 36, pp. 1693–1699, Nov. 2001.

[6] B. J. Hosticka, “Improvement of the Gain of CMOS Amplifiers,” *IEEE J. of Solid-State Circuits,* vol. 14, pp. 1111–1114, Dec. 1979.

[7] J.-S. Lee et al., “Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loops,” *Electronics Letters,* vol. 36, pp. 1907–1908, Nov. 2000.

[8] M. Terrovitis et al., “A 3.2 to 4 GHz 0.25 *μ*m CMOS Frequency Synthesizer for IEEE 802.11a/b/g WLAN,” *ISSCC Dig. Tech. Papers,* pp. 98–99, Feb. 2004.

[9] M. Wakayam, “Low offset and low glitch energy charge pump and method of operating same,” US Patent 7057465, April 2005.

[10] H. R. Rategh, H. Samavati, and T. H. Lee, “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” *IEEE J. of Solid-State Circuits,* vol. 35, pp. 780–788, May 2000.

9.1. The mixer phase detector characteristic shown in Fig. 9.5 exhibits a *zero* gain at the peaks, e.g., at Δ*φ* = 0. A PLL using such a PD would therefore suffer from a zero loop gain at these points. Does this mean the PLL would not lock?

9.2. If *K _{VCO}* in the PLL of Fig. 9.10(a) is very high and the PD has the characteristic shown in Fig. 9.5, can we estimate the value of Δ

9.3. Repeat Problem 9.2 if the sign of *K _{VCO}* is changed.

9.4. Determine at what frequencies the output sidebands of Fig. 9.7(a) are located. Are these sidebands or harmonics?

9.5. In the PLL of Fig. 9.8(b), an input change of Δ*φ* exactly yields an output change of Δ*φ*. On the other hand, in the buffer of Fig. 9.8(a), an input change of Δ*V* produces an output change of Δ*V*/(*A*_{0} + 1), where *A*_{0} is the open-loop gain of the op amp. How do we explain this difference?

9.6. Suppose the PLL of Fig. 9.12 is locked. Now, we replace *R*_{1} with an open circuit. What happens at the output as time passes? Consider two cases: a noiseless VCO and a noisy VCO. This example shows that if the VCO (excess) phase does not drift with time, the feedback loop can be broken.

9.7. Determine the transfer function, *ζ*, and *ω _{n}* for the frequency-multiplying PLL of Fig. 9.18(b).

9.8. For the PFD of Fig. 9.20, determine whether or not the average value of *Q _{A}* −

9.9. Compute the peak value of |*H*| in Example 9.17.

9.10. Suppose a PLL designed with *ζ* = 1, a loop bandwidth of *ω _{in}*/25, and a tuning range of 10%. Assume

9.11. A PLL is designed with an input frequency of 1 MHz and an output frequency of 1 GHz. Now suppose the design is modified to operate with an input frequency of 2 MHz. Explain from Eq. (9.43) what happens to the output sidebands if (a) the output frequency remains unchanged, or (b) the output frequency also doubles. Assume in the latter case that *K _{VCO}* must double.

9.12. The ripple on the control voltage creates sidebands around the carrier at the output of a PLL, equivalently disturbing the phase of the VCO. Explain why the PLL suppresses the VCO phase noise (within the loop bandwidth) but not the sidebands due to the ripple.

9.13. Consider the PLL shown in Fig. 9.70, where amplifier *A*_{1} is interposed between the filter and the VCO. If the amplifier exhibits an input-referred flicker noise density given by *α*/*f*, determine the PLL output phase noise.

9.14. A PLL incorporates a VCO having the characteristic shown in Fig. 9.71. It is possible to compensate for the VCO nonlinearity by varying the charge pump current as a function of the control voltage so that the loop dynamics remain relatively constant. Sketch the desired variation of the charge pump current.

9.15. A PLL operates with input and output frequencies equal to *f*_{1}. Suppose the input frequency and hence the output frequency are changed to *f*_{1}/2. Assuming all loop parameters remain unchanged and neglecting the continuous-time approximation issues, explain which one of these arguments is correct and why the other one is not:

(a) The PFD now makes half as many phase comparisons per second, pumping half as much charge into the loop filter. Thus, the loop is less stable.

(b) Equation indicates that *ζ* remains constant and the loop is as stable as before.

9.16. In the loop shown in Fig. 9.72, *V _{ex}* suddenly jumps by Δ

9.17. Two PLL configurations are shown in Fig. 9.73. Assume the SSB mixer *adds* its input frequencies. Also, assume *f*_{1} is a constant frequency provided externally and it is less than *f _{REF}*. The control voltage experiences a small sinusoidal ripple with a frequency of

(a) Determine the output frequencies of the two PLLs.

(b) Determine the spectrum at point *A* due to the ripple.

(c) Now determine the spectrum at nodes *B* and *C*.

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