Glossary
AHDL Altera Hardware Description Language, a proprietary HDL.
algorithm A step-by-step method of solving a problem.
antifuse A connection link that turns into a low impedance when stressed.
ASIC Application-Specific Integrated Circuit, an integrated circuit designed to perform a specific job, though the job might be generic (a microprocessor is an ASIC, for example).
ATPG Automatic Test Pattern Generator.
asynchronous Logic that operates without a reference clock. 90% of the problems the logic designer will face are related to asynchronous signal timing.
autorouting A computerized method of determining signal or element interconnection.
behaviorial A procedural coding style that describes logic without a direct link to the synthesized hardware. This is a more abstract form of logic definition compared with structural gates and continuous assignment statements.
bidirectional A port that acts as both input and output (inout). This port will have output drivers connected to an input port. It is up to the designer to assure that only one output driver is active at a given time.
binary A system with two states, either one or zero.
bit A contraction for binary digit.
bitstream FPGA/CPLD configuration information that is formatted for serial communication.
bitwise Describes an operation where a bit in one vector acts on or is acted on by the corresponding bit in another vector.
blocking A blocking assignment will complete before later statements get executed (i.e., statements that follow the blocking assignment are postponed until the blocking assignment is complete). In a sequential construct, the order of blocking assignments is significant and unwanted latches can be inferred.
Boolean A system of symbolic logic based on the manipulation of symbols and numbers.
Buskeeper A low-current driver circuit that maintains a logic state on a node when the bus is tristated.
buffer A signal driver used to isolate signals or provide power gain for driving low impedance loads.
capacitance The measure of how a circuit or circuit element stores or couples charges.
case A multi-input decision statement. The test cases are prioritized, the earliest case that matches the input will be executed. The case decision is either true or false. The input is tested for an exact match to 0, 1, X, and Z conditions.
casex A case decision that treats Z and X conditions as “don’t care” (X) conditions.
casez A case decision that treats Z conditions as a “don’t care” (X) condition.
checksum A modulo-n result of adding data values. A checksum is used to validate a data packet.
CLB Configurable Logic Block, a basic Xilinx FPGA element consisting of a 3-5 input LUT.
CLM Career Limiting Move.
CMOS Complementary symmetry (i.e., uses both P- and N-style transistors) Metal Oxide Semiconductor.
combinational An asynchronous operation that makes a direct and immediate assignment to the output.
concatenation Items linked together in a continuous and related chain. In Verilog, items enclosed in {}, are linked together and operated on as a single entity.
configuration The process of loading the FPGA with the user’s design file(s).
constraints Conditions and requirements added to a design to provide optimized performance. Constraints include signal path timing requirements, device pin assignments, and logic block relative locations, etc.
core An intellectual property element, a pre-designed function block.
CPLD Complex Programmable Logic Devices. Compared to an FPGA, a CPLD has more complex logic elements and more regimented routing tracks that lead to more deterministic, but less flexible, circuit performance.
CPU Central Processing Unit.
CRC Cyclic Redundancy Checksum. A pseudorandom number correlated to a data stream.
DeMorgan‘s Theorems Two Boolean Logic theorems that convert between OR and AND forms. In Verilog form, here are the two theorems:
~(A | B) = (~A & ~B);
~(A & B) = (~A | ~B);
DFF D-Type (edge-triggered) FlipFlop.
dissipation Waste created during the performance of some useful task. In the context of FPGAs, this is power wasted when signals switch. This causes heating of the FPGA device. The dissipation (heating) is proportional to the signal loading and the switching frequency.
DLL Delay-Locked Loop. A method of controlling clock skew across a device by delaying clocks paths a variable amount until all edges are nearly simultaneous.
DRAM Dynamic Random Access Memory.
EAB Embedded Array Block. This is Altera’s basic RAM block in their CPLDs.
edge-triggered A signal that is evaluated only at the rising and/or falling edge of a reference clock.
EDIF Electronic Design Interchange Format. This standard is administered by the Electronic Industries Association (EIA).
EEPROM Electrically Erasable Programmable Read-Only Memory.
EMI Electro Magnetic Interference. Some of the energy that is wasted during signal switching is radiated into space. If this energy, if not managed, can cause problems for other electronic circuits.
EPROM Electrically Programmable Read-Only Memory.
fanout A measure of the unit-loading of a driver.
feedback A signal wrapped from an output back to the input.
FET Field Effect Transistor.
FG Function Generator. A 3-, 4-, or 5- input look-up table, a basic Xilinx logic element.
FIFO First-In First-Out register set.
flatten The process of merging modules and library parts to create a single homogenous netlist.
flipflop A bistable multivibrator, a circuit where the output is either true or false. The output depends on the input and the input history (memory).
floorplan The arrangement of logic elements in the physical structure of the device.
footprint The arrangement and style of the physical pins and package of a device.
FPGA Field Programmable Gate Array. Compared to a CPLD, the FPGA has more segmented routing and less complex logic elements. This leads to more flexible, but less deterministic, circuit performance.
FSM Finite State Machine.
GAL Generic Array Logic. Early PLDs had active-low or active-high polarity outputs, the GAL allowed programming the polarity of the output.
GIGO Garbage-In, Garbage-Out. A maxim that the quality of the output is directly related to the quality of the input.
glitch A short and unwanted signal transition.
GSR Global Set/Reset. A dedicated and device-wide signal routing and buffering resource.
GTL Gunning Transistor Logic.
GTS Global TriState.
GUI Graphical User Interface.
hazard An overlap or dropout of input signals that cause a glitch.
HDL Hardware Description Language. A text-based method of capturing a design.
hex Short for hexadecimal, a numbering system with 16 values where each power is represented by the single digit 0-9 and A-F.
hierarchy A pyramidal arrangement of modules.
hold time The period of time after a clock edge that an input signal must be stable to assure the flipflop or latch output follows the input correctly.
hysteresis A condition similar to friction where feedback is used to slow an output’s response to an input signal change. Often used to help prevent glitches.
impedance The opposition to a change of signal direction or strength. Impedance is the sum of resistance and reactance.
inout A bidirectional module port.
input A module port that is driven by an external signal or signals.
instance An occurrence of a signal, library part, or module.
instantiate To create an occurrence of a signal, library part, or module.
integer A whole number (no fractional or decimal part). Verilog defines an integer to be at least 32 bits wide.
IP Intellectual Property.
LAB Logic Array Block. This is Altera’s basic logic block in their CPLDs.
latch A level-sensitive storage element. This circuit has feedback which allows it to “remember” its history and maintain a condition based on that history.
latency The time it takes to process inputs to create the output. In a synchronous system this time can be measured in the number of clock cycles required to complete an operation.
LE Logic Element. Built from look-up tables and flipflips. Altera’s LABs are built of structured groups of LEs.
Lint A computer language syntax-checker.
LSB Least Significant Bit.
LUT Look-Up Table.
management The person who provides guidance and direction for a team. The manager of a team sets the limit for team achievement.
metastability When the setup- or hold-time for a flipflop is violated, the output becomes indeterminate, this characteristic of a flipflop is called metastability.
MSB Most Significant Bit.
MUX A multiplexer. A circuit where the output is switched or selected by a control or set of controls.
NAND Not-AND, an AND gate with the output inverted.
net A connection point similar to a trace on a circuit board.
netlist A textual version of a design which includes all elements and their interconnections.
newbie Someone who is new to a technology and therefore clueless.
nonblocking An assignment that can be scheduled without blocking the procedural flow. Nonblocking assignments occur simultaneously and do not interfere with each other, their order in a sequential block is not significant.
nsec Nanosecond (10-9).
oscillator A device that produces an alternating or pulsating output. These circuits are often used to create reference clocks for synchronous circuits. The basic requirements for an oscillator are: 360 degrees of feedback and an overall loop gain of 1. There is an old saying: if you’re trying to design an oscillator, you will get an amplifier, if you’re trying to design an amplifier, you will get an oscillator.
output A module port that drives external signal or signals.
pad A net that connects the FPGA logic to the outside world.
parameter An operating value for a module. This is generally a value that can be changed during compilation.
PCB Printed Circuit Board.
pipeline A method of reducing logic that must be resolved between clock edges. Pipelining increases operating speed at the expense of latency.
PIP Programmable Interconnect Point. Altera’s method of making signal connections.
PLD Programmable Logic Device.
PLL Phase-Locked Loop. A method of synchronizing to a reference frequency.
portability A measure of the ability to transfer a design from one target device to another.
POST Power-On Self Test.
primitive The most basic elements of a design. Verilog primitives are and, nand, nor, or, xor, and xnor. Primitives may also describe the elements of an FPGA/CPLD architecture (pin buffers, clock drivers, LUT’s, etc.).
propagation Signals are represented by charges. It takes time for charges to be distributed across and through circuitry, this time is called propagation.
pull-down A termination resistor, unless the wire is otherwise driven, the resistor pulls the node to a logic low.
pull-up A termination resistor, unless the wire is otherwise driven, the resistor pulls the node to a logic high.
PWB Printed Wiring Board.
RAM Random Access Memory.
reg A data storage element which can be a latch, a flipflop, or a memory cell or cells. The default state of a Verilog reg is X.
RFI Radio Frequency Interference.
route The physical path a signal follows to get to its destination.
RTL Register Transfer Level. RTL assumes a set of hardware constructs are defined in FPGA hardware and library elements. HDL code is mapped to these constructs. RTL constructs include circuit blocks like flipflops, latches, MUXs, etc., all connected together with the FPGA routing resources.
schematic A graphical circuit diagram.
SDF Standard Delay Format, a netlist that includes signal delay information.
sensitivity list Also called an event list or event sensitivity list. This is an index of signals used in a block. This list drives the simulator: the simulator can evaluate signals that change and determine if the signal is used in a block. If the signal is not used, the block does not have to be processed.
setup time The period of time before a clock edge that an input signal must be stable to assure the flipflop or latch output follows the input correctly.
skew The time difference between when a signal is generated in one part of an FPGA and when it arrives at destination(s) at other parts of the FPGA.
slack time The extra time available to allow logic to resolve before a timing violation occurs. Positive slack time is good, negative slack time is bad.
SMT Surface Mount.
SRAM Static Read-Only Memory.
structural A form of HDL coding style where circuit elements are connected together like a schematic.
stuck A form of logic fault. A signal can be stuck at a certain value (like a stuck-at-1 fault) when it should change based on some input change.
synchronous A form of circuitry that uses a clock reference.
synthesis The process of mapping HDL to the available hardware.
ternary Arranged in a group of three.
threshold The voltage level where a signal is resolved into a zero or one value. For TTL, this voltage is approximately 1.4V, for CMOS the voltage is approximately ½ the supply voltage.
tick The accent grave or open quote symbol ( ` ) used by Verilog to identify compiler directives (′define for example). Not to be confused with the close quote symbol ( ‘ ) used in defining numbers (1’b0 for example).
timescale The basic unit of time used during simulation. The default time unit in Verilog is nsec.
TLA Three Letter Acronym.
toggle To change state.
tri A Verilog net that can be driven by only multiple sources.
tristate Three levels of output drive, 0, 1, or Z (open or no drive).
uA Microamp (10-6 Amps).
UART Universal Asynchronous Receiver-Transmitter.
vector Multibit net or register variable. Verilog only supports one-dimensional vectors. This can also be shorthand for test vectors, a set of input and output values used for test.
vendor A supplier of goods or services.
Verilog A HDL simulation language designed by Phil Moorby et al in 1983-1984 for Automated Integrated Design Systems (later called Gateway Design Automation). Gateway was acquired by Cadence in 1989. Cadence placed Verilog into the public domain managed by the Open Verilog International (OVI) in 1990. IEEE Std 1364-1995 Standard Hardware Description Language Based on the Verilog® Hardware description Language was approved in 1995.
VHDL Very high-speed integrated circuit Hardware Description Language. This language has its roots in the Ada programming language and is the main competitor to Verilog.
wire A Verilog net (can be driven by only one source).
X An unknown value.
XNOR Exclusive NOR, the output is an inverted version of the XOR function.
XOR Exclusive OR, the output is true only when the inputs are different.
Z A high impedance value (open or not driven).