Real World FPGA Design with Verilog
Prentice Hall PTR
Upper Saddle River, NJ 07458
www.phptr.com
Library of Congress Cataloging-in-Publication Data
Coffman, Ken.
Real world FPGA design with Verilog / Ken Coffman.
p. cm.
Includes bibliographical references.
ISBN 0-13-099851-6
1. Field programmable gate arrays--Computer-aided design. 2. Verilog (Computer
hardware description language) I. Title.
TK7895.G36 C64 1999
621.39’5--dc21 99-046369
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Trademarks: Verilog is a trademark of Cadence Design Systems, Inc. OrCAD is a registered trademark of OrCAD Systems Corporation. Silos III is a trademark of Simucad Inc. Altera is a trademark and service mark of the Altera Corporation in the United States and other countries. MAX, FLEX, FLEX 10K, FLEX 8000, AHDL, MegaCore, and Altera device part numbers are trademarks and/or service marks of Altera Corporation in the United States and other countries. Xilinx is a registered trademark of Xilinx, Inc. Hardwire, LogiBLOX, VersaBlock, VersaRing are trademarks of Xilinx, Inc. LeonardoSpectrum, LeonardoInsight, HDLInventor, FlowTabs, and Power Tabs are trademarks of Exemplar Logic. All other product names mentioned herein are the trademarks of their respective owners.
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Materials based on or adapted from materials and text owned by Xilinx, Inc., courtesy of Xilinx, Inc. © Xilinx, Inc. 1995–1999. All rights reserved.
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Dedication
This is my first book to reach publication and I dedicate it to my wife, Judy Coffman. In May of 1972 we were married. Since then, she has (mostly) patiently watched me play in rock bands (see www.owlband.com), get my Bachelor’s degree at night school, go to a hundred concerts with my friends, do countless moonlighting projects, write some novels (some with my partner Mark Bothum), promote rock shows (some with my partner Craig Ranta), and now write this technical book. During these years, of course, I was working a day job to pay the bills. All this while the weeds were growing in the yard and the honeydew list was gathering dust.
Thanks for hanging in there, babe. I’ll finish the landscaping as soon as I finish my next book, I promise!
Prentice Hall Modern Semiconductor Design Series
James R. Armstrong and F. Gail Gray
VHDL Design Representation and Synthesis
Jayaram Bhasker
A VHDL Primer, Third Edition
Mark D. Birnbaum
Essential Electronic Design Automation (EDA)
Eric Bogatin
Signal Integrity: Simplified
Douglas Brooks
Signal Integrity Issues and Printed Circuit Board Design
Alfred Crouch
Design-for-Test for Digital IC’s and Embedded Core Systems
Tom Granberg
Handbook of Digital Techniques for High-Speed Design
Howard Johnson and Martin Graham
High-Speed Digital Design: A Handbook of Black Magic
Howard Johnson and Martin Graham
High-Speed Signal Propagation: Advanced Black Magic
William K. Lam
Hardware Design Verification: Simulation and Formal Method-Based Approaches
Farzad Nekoogar and Faranak Nekoogar
From ASICs to SOCs: A Practical Approach
Samir Palnitkar
Design Verification with e
David Pellerin and Scott Thibault
Practical FPGA Programming in C
Christopher T. Robertson
Printed Circuit Board Designer’s Reference: Basics
Chris Rowen
Engineering the Complex SOC
Wayne Wolf
FPGA-Based System Design
Wayne Wolf
Modern VLSI Design: System-on-Chip Design, Third Edition
Brian Young
Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages
Contents
Foreword
Notes on the Current State of the Art
Preface
Digital Design in the Real World
Acknowledgments and Notes on the Second Printing
Chapter 1 Verilog Design in the Real World
Trivial Overheat Detector Example
Synthesizable Verilog Elements
Blocking and Nonblocking Assignments
Miscellaneous Verilog Syntax Items
Chapter 2 Digital Design Strategies and Techniques
Analog Building Blocks for Digital Primitives
Using a LUT to Implement Logic Functions
Discussion of Design Processing Steps
Chapter 3 A Digital Circuit Toolbox
Area/Speed Optimization in Synthesis
Trade-off Between Operating Speed and Latency
Chapter 4 More Digital Circuits: Counters, RAMs, and FIFOs
Linear Feedback Shift Registers
Chapter 5 Verilog Test Fixtures
Chapter 6 Real World Design: Tools, Techniques, and Trade-offs
Compiling with LeonardoSpectrum
Complete Design Flow, 8-Bit Equality Comparator
8-Bit Equality Comparator with Hierarchy
Optimization Options In the Xilinx Environment
Logic Level Timing Report/Post Layout Timing Report
VHDL/Verilog Simulation Options
Chapter 7 A Look at Competing Architectures
Factors that Determine Integrated Circuit Pricing
FPGA Technology Selection Checklist
Chapter 8 Libraries, Reusable Modules, and IP
Keys to Increased Productivity
A Small Diversion to Compare a Schematic to a Verilog Design
Using LogiBLOX Module Generator
Design Reuse, Reusing Your Own Code
Chapter 9 Designing for ASIC Conversion
Design Rules for ASIC Conversion
Afterword—A Look into the Future
Foreword—Notes on the Current State of the Art
When I graduated from the Université du Québec à Chicoutimi with my Engineering degree, then later from the University of Waterloo with my Master’s degree, I thought I was ready to take on the world’s toughest design challenges. Little did I know that the Real World of design had little to do with the ideal laboratory conditions where we bread-boarded our academic designs. For example, once in the Real World, I found it had little use for the ripple-through FIFO with asynchronous control logic I’d spent hours trying to understand. The ripple binary counters, implemented by using the Qbar from the previous bit as the clock input for the next bit, were nowhere to be seen. I think I had heard of metastability, but I was not taught where to pay attention to it, nor how to minimize the problems it causes. I should have learned how to properly implement an edge detector. I thought I knew what a glitch was, but I did not understand when glitches are a problem nor how to eliminate them. I naively believed that designs were implemented using perfect manufacturing processes. As a result, my designs were never functionally correct the first time!
The Real World of design was about to undergo a transformation for which my formal education left me ill-prepared: the apparition of logic synthesis. Minimizing logic using Karnaugh maps was being relegated to the electronic equivalent of the Stone Age. Selecting JK or T flipflops to minimize decode logic was becoming just as relevant. The little green plastic template I used to draw schematics in countless lab reports and final exams was going to join the manual typewriter in the obsolescence paradise.
The skills that turned out to be the most useful I had not learned as part of my engineering curriculum: typing (which my mother forced me to learn throughout high school on our IBM Selectric typewriter) and computer programming (where I was self-taught and still had more to learn). What my engineering background gave me was the ability to learn new tricks and discern work patterns that could be rendered repeatable, then later automated.
This book is all about what I learned through the hardware-design school of hard knocks. Many mistakes could have been avoided, and many hours of mentoring eliminated, if I had had such a textbook and heeded its advice. This book is not just about the Verilog language, and that is its greatest contribution. There are already numerous books about the details of the language. This book is about hardware design in the Real World, where Verilog is simply the implementation tool. I hope that the next edition will feature VHDL as well as Verilog: both are equally capable of (I would even say equally poor at) implementing designs that will meet Real World constraints. This book is also unique in describing in detail the entire FPGA design process: from HDL coding to verification to synthesis to device selection to fitting and place-and-route. Too many books satisfy themselves in showing only the HDL coding aspect.
The most important advice that this book gives is to understand what needs to be done before you start coding. The biggest sin this book commits is in understating the verification task: expect to spend 70% of your design time writing test fixtures and debugging the function of your design before implementing it. Both of these points underscore the importance of planning as well as investing as much effort as possible as early as possible in the design process. In hardware design, progress is not measured by how far along in the design process you are. Progress is measured by how close you are to producing working hardware.
Today’s buzz is about IP and design reuse. This book can be considered to be about design reuse: it is about excellent and safe design practices, not only for FPGAs but for ASICs, too. Even though I have never worked with the author, I would feel confident in reusing his designs in my own. They would be trustworthy. Design reuse is about creating designs that are trustworthy in the Real World. This book should be mandatory reading for every novice FPGA (and ASIC) designer.
Janick Bergeron
www.janick.bergeron.com
[email protected]
Preface: Digital Design in the Real World
The world of digital design is changing quickly. At a breathtaking rate, devices are becoming faster, smaller, and denser. Fifteen years ago the mainstream digital designer was manipulating a few thousand gates using schematics with an occasional ABEL-HDL module tossed into the mix. Now we have programmable devices with millions of real ASIC gates in tiny packages. On the horizon, we see devices with many more millions of gates. It is not practical for the mainstream designer to create systems on chips with schematics (how would you like to deal with a 1,000-page schematic?), so Hardware Description Languages like VHDL and Verilog have come into their own. In spite of strong opinions on both sides of the fence (including my own), the current designscape is bilingual—multilingual if you include the work of those translating C code into hardware and the work of others on more advanced and hybrid languages.
I always thought that VHDL was the bloated/bureaucratic/design-by-committee deal, and Verilog was the KISS/lean-and-mean/hippy/West Coast approach, and that the usual rules-of-engagement required us to perpetuate and widen the rift between them 
Jonathan Bromley
School of Engineering
Oxford Brookes University
SURVIVAL SKILLS
Regardless of personal opinions, the practical designer will make sure that both VHDL and Verilog skills are present on his or her resume. The current half-life of engineering information is about four years and gets shorter every day. This means that half of what you know today will be obsolete in four years. In order to survive, we weary designers have to do two things:
1. Master the parts of our skill that are timeless. This includes physics (the analog aspects of digital design, transmission-line theory, conservation of energy, antenna theory, and power management) and design concepts like synchronization, metastability, and propagation delay.
2. Keep up with the changing technology. Take advantage of free seminars, try to read some of the tidal wave of trade magazines that pile up every month, buy as many books as your Significant Other will tolerate, and pay close attention when smart people are speaking.
The world of digital design is deeply divided. The elite 5%, the ASIC designers, use hardware and software tools that cost hundreds of thousands to millions of dollars a year to maintain. They earn their living creating specialized high-volume designs. If the FPGA designer uses 50K gates, the ASIC designer uses 500K gates. If the FPGA designer is accustomed to four nanoseconds of delay through a primitive, the ASIC designer is accustomed to delays of less than a nanosecond. The ASIC designer is very careful, methodical, and does extensive planning. Errors can cost hundreds of thousands of dollars in silicon turns and schedule delays. The ASIC designer simulates, simulates, and then simulates some more.
By contrast, we FPGA designers are sloppy and impatient. There is little or no cost to experiment, so we program a part and try it. We use tools that are cheap or free on Windows-based PCs or even embed the test equipment in FPGA logic. By comparison to ASIC designers, we are a brutish and undisciplined mob, an unruly 95%. I have written this book for those who would like to join me in this mob.
This is an FPGA synthesis book. It will not make the reader into an ASIC designer, though it does address issues associated with converting an FPGA design to an ASIC. This book is for the newbie FPGA designer who wants a quick and dirty guide to creating FPGA designs that actually stand a chance of surviving in the Real World.
I worked hard on this book, but it is not perfect. If you find an error or want to argue about some of the points that are arguable (of which there are many), I look forward to hearing from you.
Ken Coffman
Mount Vernon, Washington
[email protected]
Acknowledgments
I have had the honor of working with many people who were kind enough to shine some of their brilliance in my direction. People who reviewed the manuscript and made many outstanding suggestions (including some I actually took) include Janick Bergeron, Dr. Sajjan G. Shiva, and David Graf. David Pellerin introduced me to our patient editor Bernard Goodwin; without Dave’s timely guidance and inspiration, this book would not exist. Joan McNamara patiently guided me through the production editing process and Bob Lentz did a great job copy-editing my fractured prose. For the Second Printing, Guy Corp of GrafixCORP (www.grafixcorp.com) did an outstanding job with prepress service and PDF conversion/formatting. A special tip of the hat to Jake McFarland who provided much-needed help with Microsoft Word formatting and the PDF conversion, a very painful process.
Influences in my colorful but not-all-that-illustrious career include Craig Ranta, Rick Penn, G. Scott Bright, Jerrold Gray, Bruce Dippie, Paul Swanson, Dock Brown, Jim Neumiller, Larry Liu, Gary Croft, Mike Kahn, Hal Bridges, Jeff Sanders, Paul Maltseff, Tom Dickens, Michael Irvine, Steve Swedenburg, Tom Dillon, Donn Gabrielson, Geoff Jones, Ken Lomax, Sassan Khajavi, Will Cummings, Lee Pratt and Ed Millett.
The usual suspects on the Usenet newsgroups (see the Resources section) contributed to my thinking and advancing the state of FPGA synthesis. These folks include Paul Menchini, Peter Alfke, Ray Andraka, Edward Arthur, Rajesh Bawankule, Stuart Sutherland, Cliff Cummings, Tom Coonan, Ben Cohen, Steven Knapp, Austin Franklin, Utku Ozcan, and John Cooley. Thanks: Lisa Vartanian, author of metric.c.
Many additional thanks to the folks who provided software and support: Dave Pfost, John Bennett, Patrick Kane, Jeff Sanders, Don Matson of Xilinx, Tom Feist of Exemplar Logic, Richard Jones of Simucad, and Dennis Reynolds and Dave Kresta of Model Technology.
A special nod in the direction of William M. McDonald and Robert Craig (Coolbob) Slater, RIP brothers.
Notes on the Second Printing
It is an honor to have sold out the first printing of my book and have the privilege of creating a second printing. My readers have been kind enough to draw to my attention a number of errors which it is a great relief to finally be able to fix. I wish to thank the sharp-eyed readers who contributed to this printing, who include Rogelio Azuela Matuck, Glade Bacon, Richard Coronado, Joseph Curren, David Graf, David Hawkins, Jan Hofland, Robert Jarnot, David Murray, Matt Noel, Scott Nolan, Tanapong Nopavong, Ted Obuchowicz, Grady Sharpe, Jaime Villela, Mark Wang, Ed Wysocki, Robert Xue and Clive Bolton. Most people who commented have been kind and gracious. Comments, which I greatly appreciate, include “Your book is the best from the practical point of view”, “I found the book a refreshing read”, Your book is good and easy to read”, “It was a breath of fresh air to read such a lively introduction”, “I enjoyed [your book] a great deal”, “an excellent book”, and “[I] really enjoyed [the book’s] style and contents.” If you folks would repeat these nice comments at amazon.com, then I’d truly be in author’s heaven.
There is one person to whom I want to draw special attention. Writing a book is a scary proposition. In spite of my years of experience and rather unbounded arrogance, I always expected there would be a critic or two who would call an irate (and well-deserved) foul on my errors and ignorance. On February 21, 2000 I received an email with this subject: Verilog (A critique of your book…). After a quick look, I spooled it to the printer. I watched the print queue and saw that the email printed out in 24 pages. I’m in for a real flogging now, I thought. However, this email was from a bright and gentlemanly fellow named Stephen Wasson formerly of MorphICs and HighGate Design. Stephen gave me one of the nicest back-handed compliments I’ve ever received when he said: “Correcting the errors in your book was, for me, a great introduction to Verilog”. For those who have found the 1st printing errata at my website (www.bytechservices.com), you will see the long list of errors that Stephen uncovered. I will be eternally grateful that Stephen was polite and gracious in helping me debug my book. For a flavor of his commentary, here is the first paragraph of his email: “Firstly, I’d like to thank you for the marvelously entertaining and highly readable book. As a Verilog newbie, I found it an excellent introduction; as a 28-year design veteran, I found it highly pragmatic; and as the author of a dozen articles, I’m envious that your editors were such good sports to let you get away with such colorful language.” I hereby elect Stephen to the Real World FPGA Design with Verilog Hall of Fame.
Some folks have asked me if I can recommend a VHDL book similar to mine, the best practical VHDL book I know is Essential VHDL RTL Synthesis Done Right by Sundar Rajan. This book is not that easy to find, try http://www.vahana.com/vhdl.htm or email me and I’ll see if I can find you a copy. I also highly recommend Writing Testbenches by Janick Bergeron to add validation expertise to your skill-set. For this book, surf over to www.janick.bergeron.com
I want to mention my long-suffering Office Manager (and wife) Judy who maintains the website (corrections to errors in this printing will be found in an errata section at www.bytechservices.com) and my infinitely-patient editor Bernard Goodwin who is still waiting for me to finish my 2nd book. To all you folks: muchos gracious, now lets all get back to work.
Ken Coffman
[email protected]