112 3. CONTROLLER DESIGNFOR DC-DC CONVERTERSUSINGKHARITONOV’S THEOREM
Table 3.8: Minimum and maximum of close-loop coefficients (Equation (3.15))
Coeffi cient Minimum Maximum
?
3
+ ?
3
?
?
1.0832 × 10
3
+ 5.9932 × 10
3
?
?
1.3969 × 10
3
+ 6.1026 × 10
3
?
?
?
2
+ ?
2
?
?
+ ?
3
?
?
1.1099 × 10
7
+ 2.5627 × 10
8
?
?
+ 5.9932 × 10
3
?
?
1.1281 × 10
7
+ 2.6114 × 10
8
?
?
+ 6.1026 × 10
3
?
?
?
1
+ ?
1
?
?
+ ?
2
?
?
3.9649 × 10
9
+ 6.5557 × 10
10
?
?
+ 2.5627 × 10
8
?
?
4.7268 × 10
9
+ 7.5091 × 10
10
?
?
+ 6.6114 × 10
8
?
?
?
0
+ ?
0
?
?
+ ?
1
?
?
1.8185 × 10
13
+ 5.4098 × 10
14
?
?
+ 6.5557 × 10
10
?
?
1.8415 × 10
13
+ 5.521 × 10
14
?
?
+ 7.5091 × 10
10
?
?
?
0
?
?
5.4098 × 10
14
?
?
5.521 × 10
14
?
?
e following scenario is used to test the close-loop system: output load changes from 5–
25 at t D 100 ms, input voltage’s value changes from 30–40 V at t D 150 ms, and controller
reference voltage changes from 20–15 V at t D 250 ms. Test scenario is summarized in Table 3.9.
Table 3.9: Test scenario for quadratic buck converter
Change In Time Initial Value Final Value
Final
– Initial
× 100
Initial
Rload
100 ms 5 20 +300%
Vin
150 ms 30 40 +28%
Vref 250 ms 20 15
− 25%
Selection of Kp (proportional gain) and Ki (integrator gain) are done using the obtained
acceptable set (Fig. 3.21). For instance, we chose, Kp D 0:2 and Ki D 9:7. e simulation result
for the aforementioned scenario is shown in Fig. 3.22. Figures 3.23–3.25 show a closer view of
Fig. 3.23. You can test other values in the acceptable region.
3.5 CONCLUSION
In this chapter we designed controllers for DC-DC converters using Kharitonov’s theorem.
We showed the design procedure with the aid of three examples. e proposed method can be
applied to other DC-DC converters as well.
3.5. CONCLUSION 113
20
18
16
14
12
10
8
6
4
2
0
0
2 4 6 8 10 12 14 16 18 20
Ki
Kp
Figure 3.21: Acceptable Kp and Ki.
114 3. CONTROLLER DESIGNFOR DC-DC CONVERTERSUSINGKHARITONOV’S THEOREM
30
25
20
15
10
5
0
0 50 100 150 200 250 300 350 400
Time (ms)
Output Voltage (V)
Load Changes
Input Voltage Changes
Reference Voltage Changes
Figure 3.22: Simulation result.
3.5. CONCLUSION 115
20.7
20.6
20.5
20.4
20.3
20.2
20.1
20
19.9
19.8
100 101 102 103 104 105
Time (ms)
Output Voltage (V)
Figure 3.23: Output voltage changes due to load changes.
116 3. CONTROLLER DESIGNFOR DC-DC CONVERTERSUSINGKHARITONOV’S THEOREM
20.5
20
19.5
19
18.5
150 160 170 180 190 200 210 220 230
Time (ms)
Output Voltage (V)
Figure 3.24: Output voltage changes due to input source changes.
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