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Timing Analysis and Simulation for Signal Integrity Engineers
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Timing Analysis and Simulation for Signal Integrity Engineers
by Greg Edlund
Timing Analysis and Simulation for Signal Integrity Engineers
Title Page
Copyright Page
Dedication Page
Contents
Prentice Hall Modern Semiconductor Design Series
Preface
Acknowledgments
About the Author
About the Cover
1. Engineering Reliable Digital Interfaces
2. Chip-to-Chip Timing
3. Inside IO Circuits
4. Modeling 3D Discontinuities
5. Practical 3D Examples
6. DDR2 Case Study
7. PCI Express Case Study
A. A Short CMOS and SPICE Primer
B. A Stroll Through 3D Fields
Endnotes
Index
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