Using a FET (Safely) Instead of Diode

We realize that the catch diode has a significant amount of forward voltage drop, even when we are using a “low-drop” Schottky diode. Further, this forward-drop is relatively constant with respect to current. Looking at diode datasheets we see that, typically, reducing diode current by a factor of 10, only halves the voltage drop of a Schottky. Whereas we know that in a FET, the forward-drop is almost proportional to current, so typically, reducing the current by 10× reduces the voltage drop by about 10×. We can thus visualize that the presence of a diode, even a supposedly low-drop Schottky, will impair the converter’s efficiency, especially at light loads. This will also be more obvious, for almost any load, when the input is high (i.e., low D), since the diode would be conducting for most of the switching cycle, instead of the FET (switch).

We keep hearing of MOSFETs with lower and lower forward-drops (low R_DS) every day, but diode technology seems to have remained relatively stagnant in this regard (perhaps limited by physics). Therefore, it is natural to ask: since both diodes and FETs are essentially semiconductor switches, why can’t we just interchange them? One obvious reason for that is diodes do not have a third (control) terminal that we can use to turn them ON or OFF at will, as required. We conclude that diodes certainly can’t replace FETs, but we should be able to replace a diode with a “synchronous FET,” provided we drive it correctly by means of its control terminal (the Gate).

What do we mean by driving it “correctly”? There are actually several flavors of “correct,” each with its pros and cons as we will see shortly. However, there is certainly an obvious way to drive this synchronous FET. It is commonly called “diode emulation mode.” Here we very simply attempt to make the FET copy basic diode behavior, but also in the process, become one with a much lower forward-drop. That means we need to drive the Gate of the synchronous FET in such a way that the FET conducts exactly when the catch diode it seeks to replace would have conducted, and stop conducting when that diode would have stopped conducting (we will likely need some fairly complex circuitry to do that, but we are not getting into detailed implementation aspects here). Conceptually at least, we presume we can’t go wrong here.

At this point, we have fast-fowarded a bit, and presented “diode emulation mode” waveforms for a synchronous Buck converter in Figure 9.1, showing the Gate drives of the two FETs and the corresponding inductor current. Note that in synchronous topologies in general, commonly used FET designators such as “upper” and “lower,” or “top”and “bottom” are not necessarily indicative of the actual function, and can always change. Therefore, in this chapter we have generally preferred to call the switch (i.e., the control FET) as “Q,” and the synchronous FET as “Qs.” That cannot change!

Figure 9.1: Fixed-frequency, synchronous Buck waveforms.

We note that at “high loads” (i.e., with the entire inductor current waveform above “sea-level”), the waveforms are virtually indistinguishable from the classic “non-synchronous” Buck operating in CCM (though, of course, we expect better efficiency, something not obvious looking at the waveforms). Similarly, at light loads, by applying the Gate voltage waveform for Qs as shown in the figure, we ensure the synchronous FET conducts in such a manner that the waveforms are virtually indistinguishable from a non-synchronous Buck operating in DCM. So, we ask: if these waveforms are true, does that mean we can now go ahead and remove the catch diode altogether?

Not so fast! Since we are dealing with an inductor, with almost counter-intuitive behavior on occasion, we need to be extra careful. We intuitively recognize that a catch diode is “natural” in the sense that it is available when needed — it presents a path to the freewheeling inductor current automatically, without user intervention. Basically, we can’t do anything wrong here because we are not doing anything. As mentioned in Chapter 1, the only thing we do initially is place that diode at the right place, pointing in the right direction. Then we just sit back and rely on the inductor current to set up whatever voltages are necessary to create a path to freewheel through. With all the possible permutations, we thus get our different topologies and configurations. In all cases, if the diode path is available, the inductor will not “complain” in the form of the “killer voltage spike” discussed in Figure 1.6. However, when we use a FET instead of a diode, that is, a synchronous FET, we have an additional control terminal. And with that extra authority also comes additional responsibility. For example, if this FET is somehow OFF at the wrong moment, we could conceivably resurrect the killer voltage spike. Therefore, with these sobering thoughts in mind, we now start re-examining some real-world synchronous FET scenarios with extra diligence. Our focus is based mainly on the fact that in reality, the Gate controls for Q and Qs will not be perfectly matched, and will not turn ON and OFF as precisely as we may have planned (due to driver delays, inherent latencies, process variations, and so on).

Birth of Dead Time

What if Qs turns ON a little before Q has turned OFF? That is potentially disastrous since both the FETs will be ON momentarily (overlap). Just as we were worried about a voltage spike associated with the inductor, now we should be getting equally worried about a current spike coming from the capacitor (in this case the input cap). This potentially dangerous “cross-conduction” spike of current (also called “shoot-through”) will flow from the input cap through both the FETs and return via ground. Note that in a synchronous Boost, discussed later, the shoot-through current flows from the output cap, and since that is usually a higher voltage, the spike is an even bigger problem.

Note: Can we see or measure this current spike? Well, in severe cases, accentuated by bad PCB layout (which can mimic the effects of mismatched Gate drives), cross-conduction could easily cause the FETs to blow up. In less severe (more common) cases, it may be neither obvious nor measurable. If we place the current probe at the “right place,” even the small inductance of the wire loop is usually enough to quell the cross-conduction spike, and so we may not see anything unusual. We have a current spike that we perhaps can’t ever see or measure, but its existence is undeniable in the form of an increased average current drawn from the input voltage source (measured with a DC multimeter, not a scope) and a corresponding decrease in the measured efficiency (more significant at light loads). The quiescent current “I_Q” will be much higher than we had expected. Note that we are defining “quiescent current” here as the current drawn from the input supply when the converter is “idling” — that is, when its FETs are continuing to switch (at constant frequency), but the load connected to the converter happens to be zero. This is the point where the marketing guy often steps in and redefines quiescent current as an idling condition in which the load is zero, and the FETs are no longer switching (perhaps with the help of some dedicated logic pin). With that “slight change” in wording, suddenly, the above-mentioned cross-conduction loss term, along with any normal switching loss terms, is forced to zero, and therefore, the “no-load efficiency” becomes very high — on paper. To get a meaningful or realistic answer from this marketing guy, perhaps we should try asking: “What is the efficiency at 1 mA of load current?”

The solution to the cross-conduction problem is to introduce a little “dead-time” as shown in Figure 9.1. By design, this is a small intended delay, always inserted between one FET going OFF and the other coming ON. In practice, unless excessively large, dead-time just represents a safety buffer against any accidental or unintentional overlap over manufacturing process, temperature variations, diverse PCB layouts (in the case of switchers using external FETs), and so on.

CdV/dt-Induced Turn-On

Note that there is a phenomenon called CdV/dt-induced turn-on that is known to cause cross-conduction, especially in low-voltage VRM-type applications — despite sufficient dead time apparently being present. For example, in a synchronous Buck, if the top N-channel FET turns ON very suddenly, it will produce a high dV/dt on the Drain of the bottom FET. That can cause enough current to flow through the Drain-to-Gate capacitance (Cgd) of the bottom FET, which can produce a noticeable voltage bump on its Gate, perhaps enough to cause it to turn ON momentarily (but may be only a partial turn-on). This will therefore produce an unexpected FET overlap, one apparent perhaps only through an inexplicably low-efficiency reading at light loads. To avoid this scenario, we may need to do one or more of the following: (a) slow down the top FET, (b) have good PCB layout (in the case of controllers driving external FETs) to ensure that the Gate drive of the lower is held firmly down, (c) design the Gate driver of the lower FET to be “stiff,” (d) choose a bottom FET with slightly higher Gate threshold, if possible, (e) choose a bottom FET that has a low Cgd, (f) choose a bottom FET with a very small internal series Gate resistance, (g) choose a bottom FET with high Gate-to-Source capacitance (Cgs), and (h) perhaps even try to position the decoupling capacitor positioned on the input rail slightly far away from the FETs (even a few millimeters of trace inductance can help) so that despite slight overlap, at least the cross-conduction current flowing during the (voltage) overlap time gets limited by the intervening PCB trace inductances.

Counting on the Body-Diode

Dead-time not only improves efficiency by reducing chances of transistor overlap, but also impairs efficiency itself for two other reasons. But before we discuss that, a basic question arises: are we “tempting nature” by introducing this dead-time in the first place?

What if Qs turns ON a little after Q turns OFF? This is also what happens, in effect, when we introduce dead-time. We learned from Chapter 1 that any delay in providing a freewheeling path for the inductor current (i.e., after the main FET turns OFF) can prove fatal — in the form of a killer voltage spike. Admittedly, there may be some parasitic capacitance somewhere in the circuit, hopefully fortuitously present at the right place, which is able to provide a temporary path for a few nanoseconds. But that capacitor being typically very small would charge (or discharge) very quickly, and then the freewheeling inductor current would have no place to go. So, even a few nanoseconds of dead-time could prove disastrous. Luckily that scenario is not a major concern here. The reason is most FETs have an internal “body-diode” (shown in gray in Figure 9.1). So, for example, if the synchronous FET was not conducting exactly when required, as during the dead-times, the inductor current will pass through its body-diode for that tiny interval, as indicated with dashed arrows in Figure 9.1. As a result, no killer voltage spike would be seen, and we would have a switching topology that “abides by the rules of existence” presented in Chapter 1 (aka “don’t mess with the inductor”). However, to retain this advantage, and to indirectly make dead-time feasible, we need to ensure we really are using a synchronous FET with an internal body-diode. That is actually the easy part, since all discrete FETs available in the market have a body-diode inside them. However, a related question is: since a FET is a bidirectional conductor of current (when it is ON), what is the right way to “point” the FET (same question that we had posed for the catch diode)? We quickly realize that to avoid the killer voltage spike and present the body-diode to the inductor current whenever required, we need to go back somewhat to the way our old non-synchronous topology was working, and position the synchronous FET such that its body-diode points in the same direction as the catch diode it seeks to replace. This is the basic rule of all synchronous topologies that we need to keep in mind always.

Later we should observe that the body-diode of the control FET will also be called into play when we deal with “synchronous (complementary) mode drive” instead of the “diode emulation mode drive” currently under discussion. The correct way to connect the control FET is such that its body-diode is always pointing away from the inductor and toward the input source — otherwise the obvious problem would be that current will start flowing uncontrollably from the input source into the inductor, and that would clearly not qualify as a “switching topology” anymore.

Our conclusion is: we need a diode somewhere — we have been unable to replace it entirely. The last remaining question is: if the diode is present in the FET in the form of a body-diode, do we also need an external one in parallel to the FET?

Note: We mentioned above that “parasitic” capacitances can provide a temporary path for a short time. What if we actually put a physical cap at the “right place”? That actually leads to “resonant topologies.” We will not be discussing those in any detail in this book, primarily because they are usually of variable frequency and therefore rarely used commercially, and also because they require a completely new set of “rules of intuition,” which take much more time to develop, especially if you have just learned to think of squares, triangles, and trapezoids.

External (Paralleled) Schottky Diode

First of all, if we place an external diode in parallel to the body-diode, for it to do anything, the current needs to “prefer” that external diode in preference to the body-diode. So, we need the forward-drop of the external diode to be less than that of the body-diode. That is actually the easy part since the body-diode has a rather high forward-drop (more than a Schottky), typically varying from about 0.5 V for small currents to 2.5 V for much higher currents (the drop being even higher for a P-channel FET as compared to an N-channel one). An external Schottky would, in principle, seem to meet our requirement.

Note: However, to ensure that the Schottky is “preferred” in a dynamic (switching) scenario, we need to ensure the external Schottky diode is connected with very thick short traces to the Drain and Source of the FET, otherwise the inductance of the traces will be high enough to prevent current from getting diverted from the body-diode and into the Schottky as desired. The best solution is to have the Schottky integrated into the package of the FET itself, preferably on the same die, for minimizing inductances as much as possible.

Why does the Schottky diode help so much? In an actual test conducted in early 2007 at a major semiconductor manufacturer, adding a Schottky across the internal synchronous FET of a 2.7–16 V synchronous LED Boost IC on the author’s suggestion, led to an almost 10% increase in efficiency at max load. The IC was brought back to the drawing board and redesigned with an integrated Schottky across the synchronous FET (on the same die — the vendor possessed that process technology), and was finally released a few years later as the FAN5340.

The reason for the advantage posed by the Schottky is that the body-diode of a FET has another unfortunate quality besides its high forward-drop, one that we also wish to avoid. It is a “bad” diode in the sense that its PN junction absorbs a lot of minority carriers as it starts to conduct in the forward direction. Thereafter, to get it to turn OFF, all those minority carriers need to be extracted. Till that process is over, the body-diode continues to conduct and does not reverse-bias and block voltage as a good diode is expected to. In other words the “reverse recovery characteristics” of the body-diode of a FET are very poor.

So, this is what can eventually happen in synchronous switching converters without an external Schottky. During the dead-time interval between Q turning OFF and Qs turning ON (i.e., the Q→Qs crossover), we want the body-diode of Qs to conduct immediately. We therefore inject plenty of minority carriers into it (via the diode forward current). However, the full deleterious effects of that stored charge actually show up during the next dead-time interval — when Qs needs to turn OFF just before Q starts to conduct (i.e., the Qs→Q crossover). Now we discover that Qs doesn’t turn OFF quickly enough, and so a shoot-through current spike flows through Q and Qs. This unwanted reverse current ultimately does extract all the minority carriers, and the diode finally does reverse-bias. But during the rather large duration of this shoot-through, we have a significant V×I product occurring inside the body-diode, and therefore high instantaneous dissipation. The average dissipation (over the entire cycle) is almost proportional to the duration of the dead-time since the diode is just not recovering fast enough.

The only way to avoid the above reverse recovery behavior and the resulting shoot-through is to avoid even forward-biasing the body-diode, which basically means we need to bypass it completely. The way to do that is by connecting a Schottky diode across the synchronous FET, which then provides an alternative and preferred path for the current.

Whichever direction we take, we realize that we do have a diode present somewhere on our path — a body-diode or an external Schottky. Since the diode’s forward-drop is certainly higher than that of the FET it is across, the efficiency is adversely affected on that count alone (higher conduction loss). Furthermore, if it is a body-diode, then there is an additional impact on efficiency due to the reverse recovery spike (switching loss).

Eventually, reducing the dead-time should help improve efficiency on both the above-described counts. But doing so will also increase the chances of overlap, which can then adversely affect efficiency from an entirely different angle (crossover loss). In severe cases of overlap, even overall reliability will become a major concern. We are therefore essentially walking a tight-rope here. How much dead-time is necessary and optimum? Some companies have come up with proprietary “adaptive dead-time” schemes to intelligently reduce the dead-time as much as possible, usually in real-time after several cycles of sampling, to achieve just the right amount of dead-time, thus averting overlap and also maximizing the efficiency.

Synchronous (Complementary) Drive

When we look at the top section of Figure 9.1, that is, for “heavy loads,” we see that ignoring what happens during the very small dead-time, we can simply declare that Qs is ON whenever Q is OFF, and vice versa. Their drives are considered “complementary.” Therefore, design engineers just took the Gate drive as applied to Q, put an inverter to it, and applied that to the Gate of Qs (ignore dead-time circuit enhancements here). We call this a “synchronous (or complementary) mode” in contrast to the diode emulation mode discussed previously. This synchronous mode is also sometimes called the “PWM mode.” It worked as expected, just like a conventional non-synchronous topology, at least when the load was high. However, using this simple drive, as the load was lowered, the familiar-looking DCM voltage waveforms were no longer seen. In fact the well-behaved voltage waveforms normally associated with CCM remained unchanged even as the inductor current dipped below “sea-level” (zero). On closer examination, stark differences had emerged in the current waveforms. As shown in the lowermost section of Figure 9.1, two new phases had appeared, both with inductor current pointing in the “negative” direction (i.e., flowing away from the positive output, toward the input). These are marked “C” and “D.” During C, current flows in the reverse direction through Qs, whereas in D it flows in the reverse direction through Q.

This is how the system gets to C and D after B is over.

The key to not getting confused above is to remember that a positive voltage across an inductor (ON-time) produces a positive dI/dt (upward ramp), whereas a negative voltage (OFF-time) causes a negative dI/dt (downward ramp). So, the inductor’s voltage polarity determines the polarity of the rate of change of current (slope dI/dt) — it has nothing to do with the actual polarity of the current itself (I), which can be positive or negative as we have seen above.

What are the main advantages of “synchronous mode”? We get constant frequency, no ringing during the idling time (and therefore more predictable EMI), easier Gate drive circuitry, constant duty cycle (even at light loads), simpler stress (RMS) equations to compute (see Chapter 19). The key advantages of “diode emulation mode” are reduced switching losses (there are no turn-on crossover losses since the instantaneous current is zero at the moment of crossover) and generally more stable though admittedly sluggish response (single-pole open-loop gain; no low-frequency right-half-plane zero, no subharmonic instability).

DCR Sensing

Perhaps it all started with this simple thought: instead of putting a sense resistor in series with the FET, why not put the sense resistor in series with the inductor? We would then obtain full information about the inductor current, rather than just the ON-time or OFF-time slice of it. This could conceivably help us in implementing various new control and protection techniques too. However, that thought process then went a step further by asking: since every inductor has a resistance “built-in” already, called its DCR, could we somehow use that resistance in place of a separate sense resistor? We would then have “lossless current sensing,” since we are at least not introducing any additional loss term into the circuit. The obvious problem here is that the DCR is itself inaccessible: we just can’t put an error amplifier or multimeter “directly across DCR” because DCR lies buried deep within the object we call an “inductor.” However, we want to persist. We ask: is there some way to extract the voltage drop across this DCR from out of the total inductor voltage waveform? The answer is, yes, we can — and that technique is called DCR sensing.

To start with, in Figure 9.4 we present an unusual, but an original and innovative, method to provide basic average current limiting. Though it is not very accurate, it has been used very successfully in very large production volumes on the output of a commercial 70-W AC/DC flyback (for meeting safety approvals). Note that it uses a filter with a very large RC time constant.

Figure 9.4: A DCR-based average current-limiting technique.

The top part of the figure shows how we can implement this current-sense technique with a discrete (external) sense resistor in series with the inductor. In the lower part of the figure, we indicate that this technique will work just fine using the DCR of a Buck inductor too. Why is that? Because, if we have a pure inductor (no DCR) and we average its voltage over a cycle, we will get exactly zero — because in steady state, an inductor has equal and opposite voltseconds during the on-time and off-time — by the very definition of steady state! When we use a real-world inductor, with a certain non-zero DCR, the additional drop during both the ON-time and the OFF-time is I_O×DCR, and that is clearly the term which remains after we average the inductor voltage over one complete cycle or several cycles. That is the DC voltage being applied on the comparator pin in Figure 9.4.

Just for interest, we note that in the 70-W flyback we mentioned above, the “sense resistor” used was the small resistance of the small L (rod inductor) of the LC post filter of the flyback.

Note that this DCR sensing technique uses a very large RC time constant, and so we lose all information about the actual shape of the inductor waveform. That doesn’t matter however, because in this particular case, we just want to implement average current limiting. But we now ask: can we extend the same technique to full current sensing?

In Figure 9.5, we present how this is done rather commonly nowadays. In this case, the RC time constant is not large, but it is in fact matched exactly to the time constant of the L–DCR combination, which means mathematically: RC=L/DCR. We see from the Mathcad graphs embedded in the figure that with this matching, and stated initial conditions, the voltage on the capacitor becomes an exact replica of the voltage across the DCR. Further, for any duty cycle other than the steady-state duty cycle, the manner in which the DCR voltage (and therefore inductor current) changes is also replicated exactly by the capacitor voltage, which means that the two voltages indicated will track each other accurately under all conditions, steady state or otherwise. For example, if the inductor current is momentarily unsteady (as during a line or load transient), the capacitor voltage will not be steady either. But it is interesting that in fact, both the DCR voltage and the cap voltage will increase or decrease by exactly the same amount from this point on. This indicates that both the voltages will change identically (i.e., track each other), and finally settle down identically too, at their common shared steady-state initial voltage condition. Note that the settling/initial value, as indicated in the figure, is I_O×DCR.

Figure 9.5: DCR current sensing explained (with exaggerated DCR).

The advantage of the above fancy version of DCR sensing is that the entire AC and DC information of the inductor current waveform is now available via the sensed capacitor voltage (assuming, however, that the inductor does not saturate somewhere in the process).

Is there any simple intuitive math to explain this time-constant matching and the resulting tracking? Yes, but it is not a rigorous proof, as we will see. Let us start by applying the duality principle. We know that the voltage on a capacitor when charged by a current source is similar to the current through an inductor when “charged” by a voltage source. Assuming steady-state conditions are in effect, and also that the maximum voltage on the capacitor is low compared to the applied on-time and off-time voltages (V_ON and V_OFF, roughly V_IN–V_O and V_O respectively), we get near constant-current sources (V_ON/R and V_OFF/R) charging and discharging the cap during the ON-time and OFF-time, respectively. The question is: what is the cap voltage swing during the ON-time and during the OFF-time. Further, are the swings identical in magnitude, or is there a “leftover delta” remaining at the end of the cycle, indicative of a nonsteady state?

Using

we get

We know from the voltseconds law that

Therefore,

Similarly, for the inductor current, using

we get

We know from the voltseconds law that

Therefore,

We conclude that there is no leftover delta remaining at the end of the cycle for either the inductor current swing or the cap voltage swing. Therefore, both inductor current and cap voltage are in steady state. That is just duality at work (as introduced in Chapter 1).

Let us now compare the capacitor voltage swing and the DCR voltage swing and try to set them equal, so we can get them to be exact copies, rather than merely scaled copies, of each other.

Set

equal to

Therefore,

Or

That is the basic matched time-constant condition for DCR sensing, and we see it follows rather naturally from the simplified intuitive discussion above.

This simple analysis does indicate that the cap voltage is mimicing the inductor current. It tells us quite clearly that the AC portion of the inductor current is certainly being copied by the cap voltage. But what can we say about the DC level? Is the DC cap voltage copying the DC inductor current too? It actually does, but that does not follow from the simple intuitive analysis presented above (or from any complicated s-plane AC analysis you might see in literature). For that we should look at Figure 9.5.

Note that in Figure 9.5, we have used the accurate form of voltages appearing on the capacitor during the ON-time and OFF-time. Those include the small (but decisive) term I_O×DCR, which eventually determines the DC value of the capacitor voltage. The DC value is easy to understand based on the analysis we presented earlier when discussing Figure 9.4. We recall that after we average out the voltseconds, the I_O×DCR term is all we are left with. So clearly, that must be the DC value of the capacitor voltage waveform in the present case too. Philosophically, we recognize that time constants don’t enter the picture when performing DC analysis. The effects of time constants are time bound by definition. So we conclude that both Figures 9.4 and 9.5 must provide the same DC/settling values ultimately.

We realize that with good time-constant matching, the DCR voltage in Figure 9.5 becomes a carbon copy of the capacitor voltage, and vice versa — with both AC and DC values replicated. We ask: is that replication true only in steady conditions or is it also true under transient conditions? We see from Figure 9.5, for the cases of duty cycle other than steady state (i.e., n not equal to 1), that the change in cap voltage is also an exact replica of the change in DCR voltage (referring to the leftover delta at the end of the cycle). That means both the cap voltage and the DCR voltage (corresponding to inductor current) will climb or fall identically under transients, heading eventually toward their (identical) steady-state values. This implies that their relative tracking is always very good, steady state, or otherwise.

However, in reality, DCR sensing is not considered very accurate and should not be relied upon for critical applications. For example, it is well known that the nominal DCR value has a wide spread in production, and the DCR itself varies significantly with temperature. So, the last remaining question is: what are the effects of mismatched time constants (L/DCR and RC)? We have seen that the inductor current reaches steady state based on an initial (DC) condition I=I_O, and corresponding to that, the capacitor voltage reaches steady state with an initial (DC) condition of v=I_O×DCR. We expect that to remain true for any time constant, since after several cycles, the effect of any time constant literally “fades away.” In other words, the DC value of the cap voltage waveform cannot vary on account of mismatched time constants per se (but will obviously change if DCR itself varies). When subjected to a sudden line or load transients, the effect of mismatched time constants will be severe (though only temporarily so). For example, if the capacitance of the RC is very large, the cap voltage will change very little and rather slowly, as compared to the inductor current. But final settling value will be unchanged (for same DCR).

Note that many commercial ICs allow the user to either choose the DCR for cost and efficiency reasons, or use an external sense resistor (in series with the inductor) for higher accuracy.

The Inductorless Buck Cell

The power of “what-if” can be uniquely powerful in power conversion. So, as a variation of classic DCR Sensing, we ask: what if we reposition the lower terminal of the capacitor in Figure 9.5 and connect it to ground, as shown in Figure 9.6?

Figure 9.6: Inductorless Buck and an alternative regulation and current-sensing scheme (shown with exaggerated DCR).

For negligible DCR, we will discover that (for fairly large capacitances) the capacitor voltage will be the same as the voltage on the output capacitor of the Buck converter. That is interesting. But we also notice that by repositioning the cap, the series RC no longer rides on the output rail, but is separate from the LC. The two branches, RC and LC, are independent and in parallel now. This implies we can

Note that this inductorless Buck technique can also be used in non-synchronous converters. But in that case we always need to have the LC present in parallel to the RC. Because in the absence of a synchronous FET actively forcing the switching node (close) to ground during the OFF-time, the current flowing in L becomes responsible for accomplishing that. We have to get voltage applied to the RC to actively toggle repetitively. Otherwise the cap of the RC would just charge up to the input voltage.

Lossless Droop Regulation and Dynamic Voltage Positioning

In Figure 9.7, we start with a conventional Buck. Then we move down to the next schematic and introduce a droop resistor “Rdroop.” This is one of the conventional ways of implementing droop regulation. Note that we are now regulating the point marked V_O+(I_O×Rdroop) instead of regulating V_O, which means that V_O is no longer fixed. Because, for example, if the current I_O rises, V_O+I_O×Rdroop will tend to increase. But since we are holding V_O+I_O×Rdroop constant by means of the regulation loop, the only solution is for V_O to decrease as I_O increases. This is called droop regulation or “dynamic voltage positioning.”

Figure 9.7: Conventional voltage positioning (droop regulation) and a novel lossless inductorless Buck implementation.

Now, we would like to do this with DCR instead of Rdroop, since that would be considered lossless. But DCR is not accessible. However, from Figure 9.6 we have learned that the inductorless Buck cell provides a rail that is exactly equal to V_O+(I_O×DCR). Further, the good news is that this point is accessible. So, if we connect the error amplifier to it, we will achieve the same basic effect as conventional droop regulation (proposed by the author here).

What are the benefits of droop regulation in general? In Figure 9.7, we show the transient response waveforms with and without droop. The advantage of droop is very simply explained as follows:

We see that droop regulation naturally “positions” the output at a “better level” to start the excursion with, so it is more suited to avoiding overshoots and undershoots. This is very useful especially in VRM-type applications, where the allowable regulation window is, indeed, very tight.

Is It a Boost or Is It a Buck-Boost?

Before we discuss the Cuk and Sepic, we need to understand the basic Boost and Buck-Boost topologies better. Looking at Figure 9.12, we will realize that they belong to the same “super-schematic.” We create the difference by the way we choose to extract energy from the circuit. In fact, by using separate output diodes we can generate two outputs simultaneously, from the same circuit (even though we would be able to regulate only one of them).

Figure 9.12: The “super-schematic” from which the Boost and Buck-Boost topologies can be derived and the method of mapping common polarity topologies to their reverse polarity counterparts.

A numerical example will make this clearer. Suppose we take a 12-V input Boost converter and apply a duty cycle of 50% to it. We expect to get a Boosted output rail equal to twice the input voltage, that is, 24 V in our example here (use V_O/V_IN=1/(1−D)). Now, in a Buck-Boost, we would be drawing output energy not from the 24-V Boosted rail and ground, but from between the 24-V Boosted output rail and the 12-V input rail. Eventually, we would call that a negative-to-positive Buck-Boost because, by convention, the rail common to the input and output is the topological ground — and so the 12-V input rail would be renamed the “ground” for the Buck-Boost topology, whereas the input ground of the Boost topology would now become the −12-V input rail of the Buck-Boost. Note that in our example, the Buck-Boost output voltage would then be 24−12=12 V. So, if Figure 9.12 is to be believed, we expect a −12-V to 12-V Buck-Boost to result when switching with a duty cycle of 50%. But that is completely consistent with what we know of a Buck-Boost topology: if we switch it with D=50%, we expect the output voltage to equal the input voltage in magnitude (use V_O/V_IN=D/(1−D)). So, Figure 9.12 must be right. But if not fully convinced, we can repeat the above numerical example for any D, and we will realize that the Buck-Boost and Boost are truly part of the same super-schematic shown in Figure 9.12. No wonder that both the Boost and the Buck-Boost share another valuable property: the center of inductor current in both cases is I_O/(1−D).

In Figure 9.12, we go a step further. Starting with the super-schematic on the left, that would give us a positive-to-positive Boost and a negative-to-positive Buck-Boost, we generate a super-schematic that gives us a negative-to-negative Boost and a positive-to-negative Buck-Boost.

Note: Historically, voltages used to be referred to with the higher potential being labeled ground, and the rest of the circuit “hanging” from it, much like a clothesline. These were “positive-ground” systems. Nowadays, the world has shifted largely to “negative-ground” systems, where the ground is the lower rail. So a modern-day circuit generally resembles a skyline, not a clothesline. However, in creating and recognizing composite topologies, we need to understand how a negative-ground circuit, or cell, can be mapped into its positive-ground equivalent. A simple mapping procedure, outlined in Figure 9.12, is required. Using that procedure, we generate the corresponding positive-ground super-schematic. Finally, since the mapping procedure changes high voltages to low voltages, and vice versa, to get back to our familiar convention of placing higher voltages on top of the page, we flip the positive-ground super-schematic vertically, as shown in Figure 9.12, to arrive at the more conventional way to draw a negative-to-negative Boost (and positive-to-negative Buck-Boost).

Understanding the Cuk, Sepic, and Zeta Topologies

In Figure 9.13, we first start by blindly cascading a Boost with a Buck. In the middle of the circuit, we have a DC rail bridging the two, over which power flows down, from one to the other converter. It uses two switches, and the challenge is to combine those into one. In the following three schematics, we do just that, by connecting to the switching node on either side by a coupling cap. Note that on the right side, we map each composite topology to its reverse voltage counterpart as discussed above. So we can generate a negative-to-positive Cuk or a negative-to-negative Sepic if we so desire.

Note: Though in the standard mapping process, we change an N-channel FET to a P-channel FET, all topologies, mapped or otherwise, can be implemented with either type of FET — we just have to keep track of the Gate voltages required, and if necessary, provision for a bootstrap circuit. Also, we need to pay attention to the direction the internal body-diode is pointing so as to avoid the “killer voltage spike” we often talk about. In an N-channel FET, the body-diode (considered as an arrow from anode to cathode) points from Source to Drain. In a P-channel FET, it points from Drain to Source.

Figure 9.13: Combining the positive and negative Boost cells with positive and negative Buck cells to generate various Boost-Buck composite topologies.

Each circuit actually has three sections: a Boost cell, followed by a Buck cell, followed by a block labeled “Referencing of Output Rails.” This latter block is where we can set virtually any output polarity as discussed previously. However, unlike transformer-based isolation as in a flyback, this re-referencing dramatically alters the path of currents as shown in Figure 9.14. The reason for that is in a transformer, there is no net flow of current between the two separated sections — and the output (Secondary) section can function on its own since both the forward and the return paths get disconnected by the transformer winding. But in capacitor coupling, the current path still exists, and so by re-referencing, that pattern can get completely changed. We therefore get three distinct topologies, with some remarkably different behaviors, but also with great similarities based on their common heritage: the Cuk, Sepic, and Zeta. As mentioned previously, we can look upon the Sepic as a brute-force attempt to correct the polarity inversion of the Cuk. And it worked. Though again, as mentioned previously, this introduced high RMS currents into the output cap.

Figure 9.14: The duty cycle and voltage ratings of components of the Boost-Buck composites.

In Figure 9.14, we calculate the DC voltage level appearing across the coupling capacitor in each composite topology, so we can pick its voltage rating better. The general “rules of construction” by which we have unequivocally generated the paths of currents shown during the ON-times and OFF-times, respectively, are bulleted out in the same figure. We thereby show that, similar to the fundamental Buck-Boost topology, the DC transfer of all these composite topologies is D/(1−D), just as we had inituitively expected. And similarly, the minimum voltage rating of the FET in all cases is the same: V_IN+V_O. Note that in any switching topology, in general, if the switching FET blocks a certain voltage across it when it is OFF, then when it turns ON, that same voltage blocking responsibility gets literally transferred over to the diode, which must therefore be rated identically. In other words, the diode too must be rated V_IN+V_O for all the three Boost-Buck composite topologies under discussion.

In Figure 9.15, we have first drawn the Sepic and Zeta topologies in a more conventional manner. We see that the similarities between the waveforms of these composite topologies are tremendous. It is a result of their common heritage as brought out more clearly in Figure 9.14.

Figure 9.15: Current waveforms in the Boost-Buck composites.

The current waveforms in the figure can be easily guessed based on some simple reasoning described in the next section. From Figure 9.15, we see that the only difference in the current waveforms is in the input and output capacitors. In all the other components, except for the coupling capacitor, both the required voltage and the current ratings are the same for all three topologies. This is also discussed further below.

Generating the Current Waveforms of the Cuk, Sepic, and Zeta Converters

Cuk: We refer to Figure 9.15. The center of ramp of IL2 must be I_O (output current) since it is the constant current flowing in from the output. So,

During the ON-time, this current passes through Cc. In the OFF-time, IL1 flows through the cap in the opposite direction. Since the cap is in steady state, its change in charge during the ON-time must be equal and opposite to the change in charge during the OFF-time. Therefore, the following equality must be true:

Therefore,

The current in Q during the ON-time is the sum of the two currents, IL1 and IL2. So,

The current in the diode during the off-time is also the sum of IL1 and IL2. So, its center of ramp is also I_O/(1−D), as for the switch.

We see that the switch current is the same as for a fundamental Buck-Boost in terms of its height and duration. Note that in a Buck-Boost, there is a single inductor of rating I_O/(1−D). Here we have two inductors, one rated I_O, the other I_OD/(1−D). For example, if we set I_O=1 A and D=0.5, in the fundamental Buck-Boost, the inductor must be rated at least 2 A (ignoring the ramp portion here). In the Cuk, we need two inductors, each rated 1 A. For the same inductance, the total core volume for the Cuk is actually half that of the Buck-Boost, since core volume is proportional to LI². However, if we keep the same current ripple ratio r, then if the current goes from 2 A to 1 A, we need to double the inductance (the usual scaling law for inductors). So for the case of constant r, there is no net change in the total core volume in going from the Buck-Boost to the Cuk. In fact, using two inductors instead of one will provide greater surface area exposed to natural convection, which will help in high-power applications by improving the thermal dissipation. These arguments are valid for the Sepic and Zeta too.

Sepic: We refer to Figure 9.15. The output current flows in spurts through the diode during the OFF-time only (further averaged by the output cap). We have two contributions to the diode current. Together, they must average out to I_O. So,

Coming to the coupling cap, IL1 flows through it in one direction during the OFF-time, and IL2 flows through it in the opposite direction during the ON-time. So, by equality of charge in steady state we get

Solving the two equations above, we get as for the Cuk

The current in Q during the ON-time is the sum of the two currents, IL1 and IL2. So,

The current in the diode during the off-time is also the sum of IL1 and IL2. So, its center of ramp is also I_O/(1−D) as for the switch.

Zeta: We refer to Figure 9.15. Looking at the coupling cap first, we have two currents going through it in opposite directions during the ON-time and OFF-time, respectively. The current during the OFF-time passes through L1 and is the only current component in that. So, it must equal IL1. The current through the cap during the ON-time does not go through L1. But it is the only current component through L2 during the same time. So, it is by definition equal to IL2. We therefore have by charge balance in the coupling cap

Note that the output is in series with L2, and the current in an inductor cannot change suddenly. So, from the current through L2 during the OFF-time, we get

Plugging this into the preceding equation we get

The current in Q during the ON-time is thus the sum of the two currents, IL1 and IL2. So,

The current in the diode during the off-time is also the sum of IL1 and IL2. So, its center of ramp is also I_O/(1−D) as for the switch.

Stresses in the Cuk, Sepic, and Zeta Topologies and Component Selection Criteria

We see a remarkable pattern emerge. The current waveforms of the switch and diode in all three Boost-Buck topologies are identical and are also the same as in the fundamental single-switch single-inductor Buck-Boost. We also know their duty cycle equations and voltage ratings of switch and diode are the same. That lays credence to our initial claim that these are just composites of a Boost (or equivalently of a Buck-Boost) cell and a Buck cell.

Ignoring the AC ripple component here, we see that the switch current is a rectangle of height I_O/(1−D) and width D/f. So its RMS must be

Using D=V_O/(V_O+V_IN), we can also write this as

The average current through the diode is

Note that we have to follow the general design guidelines for a fundamental Buck-Boost topology. We realize that in this case too, the RMS current through the switch is a maximum at Dmax (lowest V_IN). We already know the voltage ratings of the FET and diode in all Boost-Buck composites need to be better than V_O+V_IN (see Figure 9.14). The latter needs to be checked at Dmin (highest V_IN).

The RMS current through the coupling cap needs to be calculated also. In all Boost-Buck composites, we have IL2 flowing through the coupling cap during the ON-time and IL1 flowing in the OFF-time (opposite direction). However, for calculating RMS, the sign of the current does not matter since we use I². So, using our side-to-side segments summation formula of Figure 7.4, we get

Using D=V_O/(V_O+V_IN), we can also write this as

Clearly, this is the highest at lowest input (V_INMIN), and the cap RMS rating should be picked accordingly. We already know the voltage ratings of this cap to be V_O+V_IN or V_IN or V_O respectively, in the Cuk, Sepic, and Zeta topologies (see Figure 9.14). These need to be verified at maximum input (V_INMAX).

For the RMS current ratings of the input and output caps of these Boost-Buck composites, we note that for a Cuk, we can ignore both these RMS currents since they are very small, whereas for the Sepic we can ignore the input cap RMS, and for a Zeta we can ignore the output cap RMS. For the output RMS of the Sepic, we can use the formula given in the Design Table of the Appendix for a Boost (or Buck-Boost) output cap. For the input RMS of the Zeta, we can use the formula for a Buck-Boost input cap. That completes the calculation of stresses for all three composite topologies, and we can pick them appropriately.

As for L1 and L2, as is our usual practice, we target a current ripple ratio r of 0.4 for both these inductors at V_INMIM (Dmax). That gives us the required inductance. We already know their current ratings. Note that the voltage waveform across all inductors L1 and L2 of all three Boost-Buck composites are the same (in CCM). We can see this from Figure 9.14 that in all cases

This was the historical reason why Mr. Cuk decided to try to “save an inductor” by winding L1 and L2 on the same core (in the converter subsequently named after him). To his surprise, he discovered that, depending on how the windings were placed on the core (the coupling coefficients), the ripple current in either the input cap or the output cap, or both, could be reduced very close to zero. This is called “ripple steering.” It is the subject of great academic attention, but is still not really used commercially on a wide scale, perhaps because (a) the input/output cap RMS currents in the Cuk converter are very low to start with, (b) it is hard to guarantee coupling coefficients in mass production (and any non-guaranteed advantage is really no advantage in the commercial arena), and (c) with the advent of low-ESR caps, the heating in the input/output caps of a Cuk converter is virtually negligible to merit any further attention. Note that if this is done, it is commonplace to use the same number of turns for both L1 and L2, and so, their ripples (not their ripple ratios) will become identical. This can pose a problem at light loads because one inductor will go into DCM before the other. It can also cause different voltage stresses on the components than expected. Note that we have assumed CCM all through our previous discussions. However, since ripple steering is not commonly used, we will avoid further discussion on this shared-core approach.

Hidden Auxiliary Rails and Symmetry

In the topmost schematic of Figure 9.13, we mentioned that a brute-force composite of a Boost converter followed by a Buck converter has an intermediate rail of value V_O+V_IN. We added a footnote to say that results when the duty cycle of the Boost stage equals the duty cycle of the Buck stage. In other words, the Gates of the two FETs shown are, virtually speaking, tied together (they go ON and OFF in unison). The math behind that is shown more clearly in Figure 9.18. We see that we have a low-power regulated rail of value V_O appearing across the Boost inductor. Though it is not ground referenced, we can use it in some situations. For example, we can place an LED to indicate that the Boost stage is really switching. We can also try to regulate that auxiliary voltage rail in preference to the main output rail. This can be of use in an opto-less Primary-side sensing scheme in AC–DC power supplies, with the Buck stage replaced by a Forward converter. In the Cuk, Sepic, and Zeta converters too, we have this hidden V_IN+V_O rail, and it can be revived for low power if we want. In the lower half of Figure 9.18, we briefly present a novel AC–DC converter idea from the author, which does not require an input bridge rectifier. It goes to show that when we understand the three basic topologies better, we may not invent a radically new topology, but there is still a lot we can do by just rearranging the building blocks.

Figure 9.18: The brute-force Boost-Buck composite with an auxiliary rail, and the symmetric Boost topology.

Multiple Outputs and the Floating Buck Regulator

Another challenge is to generate multiple outputs from a single converter. In any single-switch power supply, there is always one control loop and one corresponding duty cycle. So, we get one output that is well regulated. Many attempts abound into generating multiple outputs that closely “follow” the main regulated output closely. In Figure 9.19, we collect some of the techniques used in AC–DC power supplies. They are based on the volts/turn law of a transformer, which says that at any moment, a perfect transformer has identical volts per turn on any of its windings. Of course, there is no perfect transformer. We have to counter the effects of DC resistance as we pull current from the windings, and also leakage inductance effects between the windings. The former is tackled by using fairly thick wire, and the latter will include techniques to tightly couple the Secondary windings together. Also, when we draw current from the main winding, it goes through a diode, whose forward-drop depends on current and temperature. For example, if we draw a lot of current, the drop is more. So, the control loop compensates for that drop by pushing the average volts/turn in the transformer higher (by increasing the duty cycle). That causes the other outputs to increase too, even though they do not need that correction. Therefore, one way of compensating for this effect is to have the bottom end of the Secondary winding connect to the cathode of the main output diode, as shown in the figure. Now, as the drop across the diode increases with load, it pulls the other output down somewhat, compensating partially for the higher average volts/turn in the transformer. Other ways include trying to do a sort-of weighted control loop that is lightly affected by outputs other than the main one.

Figure 9.19: Deriving cross-regulated outputs from the main transformer in AC–DC power supplies.

In Figure 9.20, we show a common technique to derive power for Secondary-side housekeeping circuitry in AC–DC power supplies. A winding is thrown across the output choke. That is straightforward. We can do the same with a Buck converter as shown. However, we can then try to have the Buck converter ride on top of the very rail it generates. That changes the Buck topology into a “floating Buck regulator.” We have reduced voltage stresses on the switch and controller IC, and we also have an auxiliary rail to use if desired. In the earlier cases, if we use a turns ratio of 1:1, the voltage on the auxiliary rail will be V_O (same as the main rail). In the floating Buck regulator, the auxiliary voltage is exactly half the voltage of the main rail (i.e., V_O/2).

Figure 9.20: Deriving auxiliary outputs from the output choke/inductor of the Forward/Buck converter and understanding the floating Buck regulator topology.

In AC–DC power supplies, we can put many windings on the transformer, and by the fact that each winding will (or should) have the same volts/turn, we can predict the voltage of other windings placed on the same core as the main controlled-output winding. In principle, we get many regulated outputs. In practice, because of parasitics and leakage inductances, the relative regulation of the output is not very good. There are many ways to handle this as indicated in Figure 9.19.

Hysteretic Controllers

Looking back at Figure 1.2, the bucket regulator and its SCR-based version are early examples of “bang-bang regulators.” A vague control loop exists that turns ON the semiconductor if the voltage falls below a certain threshold and turns it OFF if the voltage exceeds a certain threshold. There is no predictable waveform in the process. But there is also no reason why we can’t try out the same technique (or lack thereof), using a conventional Buck regulator (or even other topologies). At least the new candidate uses an inductor, so it promises much higher efficiency. Whenever the voltage falls below a certain threshold, we would command the controller to switch with its maximum duty cycle. After a while, the output would rise and cross the upper threshold, at which point all switching would stop. This type of controller would have excellent transient response since it turns on full-blast (with full duty cycle) whenever needed, and turns OFF equally dramatically when not needed. We wouldn’t have to worry about complicated poles and zeros. We would likely save a lot of die area in a controller of this type since there is no compensation circuitry or PWM comparator. But the main problem here is possible inductor saturation and “pulse-bunching.” We could get a string of full-width pulses, and then none, creating almost any pattern. We would therefore likely generate highly unpredictable EMI, and audible noise too (from magnetic components and ceramic/film capacitors).

For better results, we would like to have a steady stream of pulses instead of pulse-bunching. Further, to minimize die area and reduce quiescent current, it would also be nice to get rid of the clock entirely. How do we start by doing the latter? We realize that we have an inherent clock present in any converter, based on its switching natural time constants. For example, we know that the inductor current undulates at a regular rate, determined by the applied voltages and the inductance. That is in effect a clock. So, can we use that instead of a formal clock circuit? If so, where can we extract the signal from? If we assume that the output cap of the Buck has no significant ESL, but just resistance (ESR), it has a voltage ripple riding on top of the DC output voltage. The ripple has the same periodicity as the inductor current and also the same duty cycle that we want to drive the switch with. It thus becomes a candidate for trying to invert cause and effect. This cap voltage ripple becomes the (scaled) voltage applied to the feedback pin of the controller IC. So now, if we set min and max thresholds on the feedback pin, we could generate the very inductor waveform that we are sensing — a self-stabilizing chicken and egg situation at an electrical level, one that could last forever. That is the only naturally stable situation that can result with the bare constraints applied. This process is shown in Figure 9.21. We also see how the frequency can be changed by varying the hysteresis between the upper and the lower thresholds. Note that any asymmetry in the thresholds will translate into a DC offset error on the output.

Figure 9.21: Hysteretic control and changing switching frequency.

In reality, we know that ceramic caps in use today have very low ESR. So, the ripple on the output cap of a Buck can be very small and can also vary a lot. So, various techniques have emerged in trying to generate a proper “ESR-ramp” as outlined in Figure 9.21.

One of the problems of these hysteretic Buck regulators is that their frequency can vary a lot. Various techniques exist, some proprietary, to minimize the DC offset mentioned above and also to maintain constant frequency — all hopefully without excessively complex circuitry which would end up negating the very reason for considering hysteretic regulators — low quiescent current, good transient response, and optimized silicon area and cost.

Besides varying the hysteresis band as indicated in Figure 9.21, there is another method for trying to achieve fairly constant frequency using hysteretic controllers. This is called “constant on-time” (COT) control.

For a Buck topology, we can do the following interesting analysis:

So,

Using

In other words, if we force a constant on-time, but one that is inversely proportional to input voltage, then for a given output voltage we will get constant frequency. So, in this type of control, whenever the feedback voltage falls below a set threshold, the FET is turned ON. However, the FET is not turned OFF based on any ESR-based ripple crossing an upper threshold. Instead the FET literally “times out” because the ON-pulse is generated by a simple, one-shot flip-flop (a monostable multivibrator). Remember that this hysteretic implementation also has no clock. After the FET turns OFF, then after a small, arbitrary, guaranteed OFF-time, if the feedback voltage is still below the set threshold, another one-shot pulse will follow, otherwise the pulse will be skipped. And so on. Eventually, the converter will settle down somewhat close to a steady stream of pulses. With a simple input-feedforward circuit, the width of the one-shot can be varied inversely with respect to input voltage. So finally, the frequency will be roughly constant with respect to both line and load variations.

Can we invoke constant frequency in a hysteretic Boost? Here is the math.

We can thus eliminate T_ON

Or

Using

Or

In other words, in a Boost, if we fix T_OFF for a given input voltage, and then vary T_OFF such that it is proportional with respect to the input voltage, then for a given V_O, f is a constant. This would be a constant frequency, constant off-time (also confusingly called “COT”) Boost regulator.

Note that in Chapter 12, we discuss the causes of the RHP (right half plane) zero in the Boost and Buck-Boost topologies (operating in CCM). The intuitive reason for that is under a sudden load demand, the output dips momentarily, and therefore the duty cycle increases. But in the process, the off-time decreases. Since in both these topologies, energy is delivered to the output only during the off-time, a smaller off-time leaves less time for the new energy requirement to be met, which temporarily causes the output to dip even further before things get back to normal. So clearly, fixing a certain minimum off-time will help. The RHP zero is not present when operating in constant off-time mode. Further, in a Boost, we can get constant-frequency operation too as described above.

Don’t even bother to do the math for creating a constant-frequency hysteretic Buck-Boost. The requirement is neither constant on-time nor constant off-time, but a complicated function of both V_IN and V_O. Therefore, its implementation, if any, will just sacrifice the expected simplicity of hysteretic control.

Pulse-Skipping Mode

All the above discussions assume CCM, in which the duty cycle is almost constant with respect to load and inversely proportional to input voltage (in a Buck). So, what happens to a COT Buck converter if the load is decreased? The one-shot generator will continue to produce CCM-based one-shot pulses, whereas in conventional DCM, the pulse width decreases rapidly with load, if not forcibly disallowed. So in effect, with COT at light loads, we would end up pumping far more energy per pulse than demanded by natural DCM. The control loop will therefore see the output rising suddenly, and try to arrest that rise by skipping several pulses in succession. We thus get “pulse-skipping mode.” There are many ways to implement this feature, but the basic advantage is reduced switching losses, which are a major factor in the low-efficiency readings at light loads of synchronous converters, with complementary drives in particular. IC designers also try to take further advantage of the relatively long OFF-times, and “de-bias” some of their circuits, to reduce the quiescent current of the IC too, and maximize efficiency at light loads. For example, the FET Gate drives may no longer be held down “hard,” but rather softly so. And so on. The challenge, however, is to wake up all hibernating circuits very rapidly when the load demand increases, so as not to cause output glitches as the converter moves from pulse-skipping mode to full CCM operation. One cause of output glitches is due to the system, considered purely as a power processing stage, transitioning between an artificially enforced mode and natural CCM operation. At the transition boundary, the energy levels in the capacitors and inductor need to restabilize to their new steady-state values. Till that happens, the output will either overshoot or undershoot. However, one of the best ways of avoiding this particular type of output glitch is the “duty cycle brickwall” method of implementing pulse-skipping. This is the least intrusive method and simply sets a minimum duty cycle for the converter to obey. As the load is decreased, DCM is initially entered and the duty cycle starts to progressively decrease as load is further reduced. But at some point, the duty cycle hits a brickwall, and is not allowed to shrink further. The system then, very naturally, starts skipping pulses to maintain energy balance. If however the load is increased, equally naturally, the system exits this pulse-skipping mode. The way to tradeoff output ripple and efficiency is to carefully position this brickwall, by defining the appropriate “m-factor” below.

A typical value of m could be between 50% and 85%. This forces a natural minimum duty cycle, and the converter goes in and out of pulse-skipping mode smoothly.

Achieving Transformer Reset in Forward Converters

Finally, to close with the somewhat mundane, and also tie up some remaining loose ends, we return to the single-ended Forward converter with an energy recovery (tertiary) winding. In Figure 9.22, we indicate that the position of the energy recovery winding diode can affect converter efficiency too. This was previously touched upon in Chapter 7. In a conventional single-ended Forward converter, by using a 1:1 ratio between the Primary (“PRI”) winding and the tertiary (“TER”) winding, we ensure that the rising slope of the magnetization current V_IN/L_PRI is equal in magnitude to the falling slope V_IN/L_TER, since L_PRI=L_TER. So, we need to ensure a maximum duty cycle of 50%, which leaves just enough time, even in the worst case, for the magnetization current to slope down to the value it started the cycle off with (zero in this case). That is termed transformer “reset.” By achieving reset, we ensure the transformer can operate in steady state with no flux-staircasing. The impact of this is that the voltage stress on the FET is exactly 2×V_INMAX under all load conditions. However, a 50% max duty cycle is easily achieved by popular controllers like the UC3844, by using a frequency doubler circuit. Basically, the internal clock of the IC runs at 2×f_SW, and every alternate cycle is blanked out. During that blanked-out interval, the FET is forced OFF. So, in effect, the max ON-time (the nonblanked-out interval) can never exceed the OFF-time, and reset is assured.

Figure 9.22: Position of the energy recovery diode can affect Forward converter efficiency.

In Figure 9.23, we also show how the “active clamp Forward converter” works, and its relative pros and cons. Similar to the asymmetric half-bridge (i.e., the two-switch Forward converter, see Table 7.1), it doesn’t have an additional energy recovery winding. But nor is it restricted to a max of 50% duty cycle. In this case, it is of paramount importance to fix the maximum duty cycle by using a well-designed control circuit, since D_MAX determines the max voltage stress on the FET: V_INMAX/(1−D_MAX). If D_MAX approaches 1, the voltage stress will approach infinity. Observe that the clamp circuit basically runs like a synchronous Buck-Boost stage, the “output” of which is the voltage of the clamp capacitor. So, as in any Buck-Boost, we can predict that the output rail (the voltage on the clamp capacitor in this case) is

Figure 9.23: The active clamp Forward converter.

With that we close our sojourn into the exciting world of “new topologies,” as we wait for more to be discovered. However one thing remains clear. Figure 1.15 is still irrefutable — there are only three fundamental topologies. The rest are, on deeper thought, variants or combinations of the basic three. This chapter should have made that quite clear by now. The key to understanding “new” or exotic topologies also lies therein.